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| XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS March 2007 Rev 2.0.0 GENERAL DESCRIPTION The XRT94L33 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/de-mapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 interfaces directly to the optical transceiver The XRT94L33 processes the section, line and path overhead in the SONET/SDH data stream and also performs ATM and PPP PHY-layer processing. The processing of path overhead bytes within the STS-1s or TUG-3s includes 64 bytes for storing the J1 bytes. Path overhead bytes can be accessed through the microprocessor interface or via serial interface. The XRT94L33 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. These De-Synchronizer circuits do not need any external clock reference for its operation. The SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software. Individual POH bytes for the transmitted SONET/SDH signal are mapped either from the XRT94L33 memory map or from external interface. A1, A2 framing pattern, C1 byte and H1, H2 pointer byte are generated. The SONET/SDH receive blocks receive SONET STS-3 signal or SDH STM-1 signal and perform the necessary transport and path overhead processing. The XRT94L33 provides a line side APS (Automatic Protection Switching) interface by offering redundant receive serial interface to be switched at the frame boundary. The XRT94L33 provides 3 Mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers. A PRBS test pattern generation and detection is implemented to measure the bit-error performance. A general-purpose microprocessor interface is included for control, configuration and monitoring. APPLICATIONS * * * Network switches Add/Drop Multiplexer W-DCS Digital Cross Connect Systems FEATURES * Provides DS3/ E3 mapping/de-mapping for up to 3 tributaries through SONET STS-1 or SDH AU3 and/or TUG-3/AU-4 containers Generates and terminates SONET/SDH section, line and path layers Integrated SERDES with Clock Recovery Circuit Provides SONET descrambling frame scrambling and * * * * Integrated Clock Synthesizer that generates 155 MHz and 77.76 MHz clock from an external 12.96/19.44/77.76 MHz reference clock Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit that de-jitter gapped clock to meet 0.05UIpp jitter requirements Access to Line or Section DCC Level 2 Performance Monitoring for E3 and DS3 Supports mixing of STS-1E and DS3 or E3 and DS3 tributaries UTOPIA Level 2 interface for ATM or level 2P for Packets E3 and DS3 framers for both Transmit and Receive directions Complete Transport/Section Overhead Processing and generation per Telcordia and ITU standards Single PHY and Multi-PHY operations supported Full line APS applications support for redundancy * * * * * * * * * * * * * * Loopback support for both SONET/SDH as well as E3/DS3/STS-1 Boundary scan capability with JTAG IEEE 1149 8-bit microprocessor interface 3.3 V 5% Power Supply; 5 V input signal tolerance -40C to +85C Operating Temperature Range Available in a 504 Ball TBGA package E Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * Fax (510) 668-7017 * www.exar.com XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Block Diagram of the XRT94L33 To OC3 Telecom Bus Interface SONET/SDH TOH SONET/SDH POH Boundry Scan 20 0 Rev2...0...0 200 To F.O. OC3 TxRx SDH MUX Microprocessor Interface SONET/SDH POH DS3/E3 Mapper Jitter Attenuator & Clock Sm oothing DS3/E3 Fram er ATM Processor PLCP PPP Processor To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf Telecom Bus Interface Pointer Justify HDLC Controller STS-1 Tx/Rx TO H & POH STS-1 Channel 0 SO NET/SDH PO H DS3/E3 Mapper Jitter Attenuator & Clock Sm oothing DS3/E3 Fram er ATM Processor PLCP PPP Processor UTOPIA II/IIp Interface To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf Telecom Bus Interface Pointer Justify HDLC Controller STS-1 Tx/Rx TOH & POH STS-1 Channel 1 SO NET/SDH PO H DS3/E3 Mapper Jitter Attenuator & Clock Sm oothing DS3/E3 Fram er ATM Processor PLCP PPP Processor To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf Telecom Bus Interface Pointer Justify HDLC Controller STS-1 Tx/Rx TOH & POH STS-1 Channel 2 ORDERING INFORMATION PART NUMBER XRT94L33IB PACKAGE TYPE 27 x 27 504 Lead TBGA OPERATING TEMPERATURE RANGE -40C to +85C 1.0 XRT94L33 REGISTERS FOR SONET ATM/PPP APPLICATIONS 1.1 THE OVERALL REGISTER MAP WITHIN THE XRT94L33 The XRT94L33 employs a direct Addressing Scheme. The Address Locations for each of the "Register Groups" (or Register pages) is presented in the Table below. Table 1: The Address Register Map for the XRT94L33 ADDRESS LOCATION 0x0000 - 0x00FF 0x0100 0x0101 Reserved Operation Control Register - Byte 3 Operation Control Register - Byte 2 0x00 0x00 REGISTER NAME OPERATION CONTROL BLOCK REGISTERS DEFAULT VALUE 2 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Reserved Operation Control Register - Byte 0 Operation Status Register - Byte 3 (Device ID) Operation Status Register - Byte 2 (Revision ID) Reserved Operation Interrupt Status Register - Byte 0 Reserved Operation Interrupt Enable Register - Byte 0 Reserved Operation Block Interrupt Status Register - Byte 1 Operation Block Interrupt Status Register - Byte 0 Reserved Operation Block Interrupt Enable Register - Byte 1 Operation Block Interrupt Enable Register - Byte 0 Reserved Reserved Mode Control Register - Byte 0 Reserved Loop-back Control Register - Byte 0 Channel Interrupt Indicator - Receive SONET POH Processor Block Reserved Channel Interrupt Indicator - DS3/E3 framer Block Channel Interrupt Indicator - Receive STS-1 POH Processor Block Channel Interrupt Indicator - Receive STS-1 TOH Processor Block Reserved Channel Interrupt Indicator - STS-1/DS3/E3 Mapper Block Reserved Reserved Reserved Reserved Reserved Reserved Interface Control Register - Byte 1 0x00 0x00 0xE3 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x11 0x00 0x00 0x0102 0x0103 0x0104 0x0105 0x0106 - 0x010A 0x010B 0x010C - 0x010E 0x010F 0x0110 - 0x0111 0x0112 0x0113 0x0114 - 0x0115 0x0116 0x0117 0x0118 - 0x0119 0x011A 0x011B 0x011C - 0x011E 0x011F 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A - 0x012F 0x0130 0x0131 0x0132 3 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x0133 0x0134 0x0135 0x0136 0x0137 0x0138 0x0139 0x013A 0x013B 0x013C 0x013D 0x013E 0x013F 0x0140 - 0x0146 0x0147 0x0148 - 0x0149 0x014A 0x014B 0x014C -0x014E 0x014F 0x0150 0x0151 -0x0152 0x0153 0x0154 0x0155 - 0x0156 0x0157 0x0158 0x0159 0x015A 0x015B 0x015C 0x015D Interface Control Register - Byte 0 STS-3/STM-1 Telecom Bus Control Register - Byte 3 STS-3/STM-1 Telecom Bus Control Register - Byte 2 Reserved STS-3/STM-1 Telecom Bus Control Register - Byte 0 Reserved Interface Control Register - Byte 2 - STS-3 Telecom Bus 2 Interface Control Register - Byte 1 - STS-3 Telecom Bus 1 Interface Control Register - Byte 0 - STS-3 Telecom Bus 0 Interface Control Register - STS-1 Telecom Bus Interrupt Register Interface Control Register - STS-1 Telecom Bus Interrupt Status Register Interface Control Register - STS-1 Telecom Bus Interrupt Register # 2 Interface Control Register - STS-1 Telecom Bus Interrupt Enable Register Reserved Operation General Purpose Input/Output Register Reserved Reserved Operation General Purpose Input/Output Direction Register - Byte 0 Reserved Reserved Operation Output Control Register - Byte 1 Reserved Operation Output Control Register - Byte 0 Operation Slow Speed Port Control Register - Byte 1 Reserved Operation Slow Speed Port Control Register -Byte 0 Operation - DS3/E3/STS-1 Clock Frequency Out of Range Detection - Direction Register Reserved Operation - DS3/E3/STS-1 Clock Frequency - DS3 Out of Range Detection Threshold Register Operation - DS3/E3/STS-1 Clock Frequency - STS-1/E3 Out of Range Detection Threshold Register Reserved Operation - DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 4 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS - Byte 0 0x015E 0x015F 0x0160 - 0x017F 0x0180 0x0181 0x0182 - 0x0193 0x0194 0x0195 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D 0x019E 0x019F 0x01A0 - 0x01FF Reserved Operation - DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register - Byte 0 Reserved APS Mapping Register APS Control Register Reserved APS Status Register Reserved APS Status Register APS Status Register APS Interrupt Register Reserved APS Interrupt Register APS Interrupt Register APS Interrupt Register Reserved APS Interrupt Enable Register APS Interrupt Enable Register Reserved LINE INTERFACE CONTROL REGISTERS 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0302 0x0303 0x0304 - 0x0306 0x0307 0x0308 -0x030A 0x030B 0x030C - 0x030E 0x030F 0x0310 - 0x0382 0x0383 Receive Line Interface Control Register - Byte 1 Receive Line Interface Control Register - Byte 0 Reserved Receive Line Status Register Reserved Receive Line Interrupt Register Reserved Receive Line Interrupt Enable Register Reserved Transmit Line Interface Control Register RECEIVE/TRANSMIT UTOPIA INTERFACE REGISTERS 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0384 - 0x0502 Reserved 0x00 5 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x0503 0x0504 - 0x0512 0x0513 0x0514 - 0x0516 0x0517 0x0518 - 0x0582 0x0583 0x0584 - 0x0592 0x0593 0x0594 - 0x0596 0x0597 0x0598 - 0x1102 Receive UTOPIA Control Register - Byte 0 Reserved Receive UTOPIA Port Address Reserved Receive UTOPIA Port Number Reserved Transmit UTOPIA Control Register - Byte 0 Reserved Transmit UTOPIA Port Address Reserved Transmit UTOPIA Port Number Reserved RECEIVE STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS 0x1103 0x1104 - 0x1105 0x1106 0x1107 0x1108 0x1109 0x110A 0x110B 0x110C 0x110D 0x110E 0x110F 0x1110 0x1111 0x1112 0x1113 0x1114 0x1115 0x1116 0x1117 Receive STS-3 Transport Control Register - Byte 0 Reserved Receive STS-3 Transport Status Register - Byte 1 Receive STS-3 Transport Status Register - Byte 0 Reserved Receive STS-3 Transport Interrupt Status Register - Byte 2 Receive STS-3 Transport Interrupt Status Register - Byte 1 Receive STS-3 Transport Interrupt Status Register - Byte 0 Reserved Receive STS-3 Transport Interrupt Enable Register - Byte 2 Receive STS-3 Transport Interrupt Enable Register - Byte 1 Receive STS-3 Transport Interrupt Enable Register - Byte 0 Receive STS-3 Transport B1 Error Count - Byte 3 Receive STS-3 Transport B1 Error Count - Byte 2 Receive STS-3 Transport B1 Error Count - Byte 1 Receive STS-3 Transport B1 Error Count - Byte 0 Receive STS-3 Transport B2 Error Count - Byte 3 Receive STS-3 Transport B2 Error Count - Byte 2 Receive STS-3 Transport B2 Error Count - Byte 1 Receive STS-3 Transport B2 Error Count - Byte 0 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 0 Rev2...0...0 200 0x8F 0x00 0x00 0x00 0x00 0x00 0x8F 0x00 0x00 0x00 0x00 0x00 6 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive STS-3 Transport REI-L Error Count - Byte 3 Receive STS-3 Transport REI-L Error Count - Byte 2 Receive STS-3 Transport REI-L Error Count - Byte 1 Receive STS-3 Transport REI-L Error Count - Byte 0 Reserved Reserved Receive STS-3 Transport K1 Byte Value Reserved Receive STS-3 Transport K2 Byte Value Reserved Receive STS-3 Transport S1 Byte Value Reserved Receive STS-3 Transport - In-Sync Threshold Value Reserved Receive STS-3 Transport - LOS Threshold Value - MSB Receive STS-3 Transport - LOS Threshold Value - LSB Reserved Receive STS-3 Transport - SF Set Monitor Interval - Byte 2 Receive STS-3 Transport - SF Set Monitor Interval - Byte 1 Receive STS-3 Transport - SF Set Monitor Interval - Byte 0 Reserved Receive STS-3 Transport - SF Set Threshold - Byte 1 Receive STS-3 Transport - SF Set Threshold - Byte 0 Reserved Receive STS-3 Transport - SF Clear Threshold - Byte 1 Receive STS-3 Transport - SF Clear Threshold - Byte 0 Reserved Receive STS-3 Transport - SD Set Monitor Interval - Byte 2 Receive STS-3 Transport - SD Set Monitor Interval - Byte 1 Receive STS-3 Transport - SD Set Monitor Interval - Byte 0 Reserved Receive STS-3 Transport - SD Set Threshold - Byte 1 Receive STS-3 Transport - SD Set Threshold - Byte 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1118 0x1119 0x111A 0x111B 0x111C 0x111D - 0 x111E 0x111F 0x1120 - 0x1122 0x1123 0x1124 - 0x1126 0x1127 0x1128 - 0x112A 0x112B 0x112C, 0x112D 0x112E 0x112F 0x1130 0x1131 0x1132 0x1133 0x1134 - 0x1135 0x1136 0x1137 0x1138, 0x1139 0x113A 0x113B 0x113C 0x113D 0x113E 0x113F 0x1140, 0x1141 0x1142 0x1143 7 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x1144, 0x1145 0x1146 0x1147 0x1148 - 0x114A 0x114B 0x114C, 0x114E 0x114F 0x1150, 0x1151 0x1152 0x1153 0x1154, 0x1155 0x1156 0x1157 0x1158 0x1159 0x115A 0x115B 0x115C 0x115D 0x115E 0x115F 0x1160 - 0x1162 0x1163 0x1164 - 0x1166 0x1167 0x1168 - 0x116A 0x116B 0x116C - 0x1179 0x117A 0x117B 0x117C 0x117D 0x117E Reserved Receive STS-3 Transport - SD Clear Threshold - Byte 1 Receive STS-3 Transport - SD Clear Threshold - Byte 0 Reserved Receive STS-3 Transport - Force SEF Condition Reserved Receive STS-3 Transport - Receive J0 Trace Buffer Control Reserved Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 1 Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 0 Reserved Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 1 Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 0 Reserved Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 2 Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 1 Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 2 Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 1 Receive STS-3 Transport - Receive SF Clear Monitor - Byte 0 Reserved Receive STS-3 Transport - Auto AIS Control Register Reserved Receive STS-3 Transport - Serial Port Control Register Reserved Receive STS-3 Transport - Auto AIS (in Downstream STS-1s) Control Register Reserved Receive STS-3 Transport - TOH Capture Indirect Address Receive STS-3 Transport - TOH Capture Indirect Address Receive STS-3 Transport - TOH Capture Indirect Data Receive STS-3 Transport - TOH Capture Indirect Data Receive STS-3 Transport - TOH Capture Indirect Data 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x00 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x000 0x00 0x00 0x00 0x00 0x00 0x00 8 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive STS-3 Transport - TOH Capture Indirect Data Reserved 0x00 0x00 0x117F 0x1180 - 0x11FF RECEIVE STS-3/STM-1 TOH PROCESSOR BLOCK - RECEIVE J0 (SECTION) TRACE MESSAGE BUFFER 0x1300 - 0x133F 0x1340 - 0x13FF Receive STS-3/STM-1 TOH Processor Block - Receive J0 (Section) Trace Message Buffer - Expected and Received Reserved TRANSMIT STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS 0x1800 - 0x1901 0x1902 0x1903 0x1904 - 0x1915 0x1916 0x1917 0x1918 - 0x191D 0x191E 0x191F 0x1920 - 0x1921 0x1923 0x1924 - 0x1925 0x1926 0x1927 0x1928 - 0x192A 0x192B 0x192C - 0x192D 0x192E 0x192F 0x1930 - 0x1931 0x1933 0x1934 - 0x1936 0x1937 0x1938 - 0x193A 0x193B 0x193C - 0x193E 0x193F Reserved Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 Transmit STS-1 Transport - SONET Transmit Control Register - Byte 0 Reserved Reserved Transmit STS-3 Transport - Transmit A1 Error Mask - Low Register - Byte 0 Reserved Reserved Transmit STS-3 Transport - Transmit A2 Error Mask - Low Register - Byte 0 Reserved Transmit STS-3 Transport - B1 Byte Error Mask Register Reserved Reserved Transmit STS-3 Transport - Transmit B2 Byte Error Mask Register - Byte 0 Reserved Transmit STS-3 Transport - Transmit B2 Bit Error Mask Register - Byte 0 Reserved Transmit STS-3 Transport - K1K2 (APS) Value Register - Byte 1 Transmit STS-3 Transport - K1K2 (APS) Value Register - Byte 0 Reserved Transmit STS-3 Transport - RDI-L Control Register Reserved Transmit STS-3 Transport - M0M1 Byte Value Register Reserved Transmit STS-3 Transport - S1 Byte Value Register Reserved Transmit STS-3 Transport - F1 Byte Value Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 9 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x1940 - 0x1942 0x1943 0x1944 0x1945 0x1946 0x1947 0x1948 - 0x194A 0x194B 0x194C - 0x194E 0x194F 0x1950 - 0x1952 0x1953 0x1954 -0x19FF Reserved Transmit STS-3 Transport - E1 Byte Value Register Reserved Reserved Reserved Transmit STS-3 Transport - E2 Byte Value Register Reserved Transmit STS-3 Transport - J0 Byte Value Register Reserved Transmit STS-3 Transport - J0 Byte Control Register Reserved Transmit STS-3 Transport - Serial Port Control Register Reserved 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 TRANSMIT STS-3 TOH PROCESSOR BLOCK - TRANSMIT J0 (SECTION) TRACE MESSAGE BUFFER 0x1B00 - 0x1B3F 0x1B40 - 0x1BFF Transmit STS-3 TOH Processor Block - Transmit J0 (Section) Trace Message Buffer Reserved REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS 0x1600 - 0x1702 0x1703 0x1704 - 0x1705 0x1706 0x1707 0x1708 0x1709 0x170A 0x170B 0x170C 0x170D 0x170E 0x170F 0x1710 0x1711 0x1712 Reserved Redundant Receive STS-3 Transport Control Register - Byte 0 Reserved Redundant Receive STS-3 Transport Status Register - Byte 1 Redundant Receive STS-3 Transport Status Register - Byte 0 Reserved Redundant Receive STS-3 Transport Interrupt Status Register - Byte 2 Redundant Receive STS-3 Transport Interrupt Status Register - Byte 1 Redundant Receive STS-3 Transport Interrupt Status Register - Byte 0 Reserved Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 2 Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 1 Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 0 Redundant Receive STS-3 Transport B1 Error Count - Byte 3 Redundant Receive STS-3 Transport B1 Error Count - Byte 2 Redundant Receive STS-3 Transport B1 Error Count - Byte 1 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 10 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Redundant Receive STS-3 Transport B1 Error Count - Byte 0 Redundant Receive STS-3 Transport B2 Error Count - Byte 3 Redundant Receive STS-3 Transport B2 Error Count - Byte 2 Redundant Receive STS-3 Transport B2 Error Count - Byte 1 Redundant Receive STS-3 Transport B2 Error Count - Byte 0 Redundant Receive STS-3 Transport REI-L Error Count - Byte 3 Redundant Receive STS-3 Transport REI-L Error Count - Byte 2 Redundant Receive STS-3 Transport REI-L Error Count - Byte 1 Redundant Receive STS-3 Transport REI-L Error Count - Byte 0 Reserved Reserved Redundant Receive STS-3 Transport K1 Value Reserved Redundant Receive STS-3 Transport K2 Value Reserved Redundant Receive STS-3 Transport S1 Value Reserved Redundant Receive STS-3 Transport - In-Sync Threshold Value Reserved Redundant Receive STS-3 Transport - LOS Threshold Value - MSB Redundant Receive STS-3 Transport - LOS Threshold Value - LSB Reserved Redundant Receive STS-3 Transport - SF Set Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - SF Set Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - SF Set Monitor Interval - Byte 0 Reserved Redundant Receive STS-3 Transport - SF Set Threshold - Byte 1 Redundant Receive STS-3 Transport - SF Set Threshold - Byte 0 Reserved Redundant Receive STS-3 Transport - SF Clear Threshold - Byte 1 Redundant Receive STS-3 Transport - SF Clear Threshold - Byte 0 Reserved Redundant Receive STS-3 Transport - SD Set Monitor Interval - Byte 2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1713 0x1714 0x1715 0x1716 0x1717 0x1718 0x1719 0x171A 0x171B 0x171C 0x171D - 0 x171E 0x171F 0x1720 - 0x1722 0x1723 0x1724 - 0x1726 0x1727 0x1728 - 0x172A 0x172B 0x172C, 0x172D 0x172E 0x172F 0x1730 0x1731 0x1732 0x1733 0x1734 - 0x1735 0x1736 0x1737 0x1738, 0x1739 0x173A 0x173B 0x173C 0x173D 11 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x173E 0x173F 0x1740, 0x1741 0x1742 0x1743 0x1744, 0x1745 0x1746 0x1747 0x1748 - 0x174A 0x174B 0x174C, 0x174E 0x174F 0x1750, 0x1751 0x1752 0x1753 0x1754, 0x1755 0x1756 0x1757 0x1758 0x1759 0x175A 0x175B 0x175C 0x175D 0x175E 0x175F 0x1760 - 0x1762 0x1763 Redundant Receive STS-3 Transport - SD Set Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - SD Set Monitor Interval - Byte 0 Reserved Redundant Receive STS-3 Transport - SD Set Threshold - Byte 1 Redundant Receive STS-3 Transport - SD Set Threshold - Byte 0 Reserved Redundant Receive STS-3 Transport - SD Clear Threshold - Byte 1 Redundant Receive STS-3 Transport - SD Clear Threshold - Byte 0 Reserved Redundant Receive STS-3 Transport - Force SEF Condition Reserved Redundant Receive STS-3 Transport - Receive J0 Trace Buffer Control Reserved Redundant Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 1 Redundant Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 0 Reserved Redundant Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 1 Redundant Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 0 Reserved Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - Receive SF Clear Monitor - Byte 0 Reserved Redundant Receive STS-3 Transport - Auto AIS Control Register 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x00 0xFF 0xFF 0xFF 0x00 0x00 12 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Reserved Redundant Receive STS-3 Transport - Serial Port Control Register Reserved Redundant Receive STS-3 Transport - Auto AIS (in Downstream STS-1s) Control Register Reserved Redundant Receive STS-3 Transport - TOH Capture Indirect Address Redundant Receive STS-3 Transport - TOH Capture Indirect Address Redundant Receive STS-3 Transport - TOH Capture Indirect Data Redundant Receive STS-3 Transport - TOH Capture Indirect Data Redundant Receive STS-3 Transport - TOH Capture Indirect Data Redundant Receive STS-3 Transport - TOH Capture Indirect Data Reserved RECEIVE SONET POH PROCESSOR BLOCK CONTROL REGISTERS 0x00 0x00 0x00 0x000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1764 - 0x1766 0x1767 0x1768 - 0x176A 0x176B 0x176C - 0x1779 0x177A 0x177B 0x177C 0x177D 0x177E 0x177F 0x1780 - 0x17FF Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Reserved Receive SONET Path - Control Register - Byte 1 Receive SONET Path - Control Register - Byte 0 Reserved Receive SONET Path - Status Register - Byte 1 Receive SONET Path - Status Register - Byte 0 Reserved Receive SONET Path - Interrupt Status Register - Byte 2 Receive SONET Path - Interrupt Status Register - Byte 1 Receive SONET Path - Interrupt Status Register - Byte 0 Reserved Receive SONET Path - Interrupt Enable Register - Byte 2 Receive SONET Path - Interrupt Enable Register - Byte 1 Receive SONET Path - Interrupt Enable Register - Byte 0 Reserved Receive SONET Path - SONET Receive RDI-P Register Reserved Receive SONET Path - Received Path Label Register Receive SONET Path - Expected Path Label Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN000 - 0xN181 0xN182 0xN183 0xN184, 0xN185 0xN186 0xN187 0xN188 0xN189 0xN18A 0xN18B 0xN18C 0xN18D 0xN18E 0xN18F 0xN190 - 0xN192 0xN193 0xN194, 0xN195 0xN196 0xN197 13 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN198 0xN199 0xN19A 0xN19B 0xN19C 0xN19D 0xN19E 0xN19F 0xN1A0 - 0xN1A2 0xN1A3 0xN1A4, 0xN1A5 0xN1A6 0xN1A7 0xN1A8 - 0xN1AA 0xN1AB 0xN1AC - 0xN1B2 0xN1B3 0xN1B4 - 0xN1BA 0xN1BB 0xN1BC - 0xN1BE 0xN1BF 0xN1C0 - 0xN1C2 0xN1C3 0xN1C4 - 0xN1D2 0xN1D3 0xN1D4 - 0xN1D6 0xN1D7 0xN1D8 - 0xN1DA 0xN1DB 0xN1DC - 0xN1DE 0xN1DF 0xN1E0 - 0xN1E2 Receive SONET Path - B3 Error Count Register - Byte 3 Receive SONET Path - B3 Error Count Register - Byte 2 Receive SONET Path - B3 Error Count Register - Byte 1 Receive SONET Path - B3 Error Count Register - Byte 0 Receive SONET Path - REI-P Error Count Register - Byte 3 Receive SONET Path - REI-P Error Count Register - Byte 2 Receive SONET Path - REI-P Error Count Register - Byte 1 Receive SONET Path - REI-P Error Count Register - Byte 0 Reserved Receive SONET Path - Receiver J1 Control Register Reserved Receive SONET Path - Pointer Value - Byte 1 Receive SONET Path - Pointer Value - Byte 0 Reserved Receive SONET Path - Loss of Pointer - Concatenation Status Register Reserved Receive SONET Path - AIS - Concatenation Status Register Reserved Receive SONET Path - AUTO AIS Control Register Reserved Receive SONET Path - Serial Port Control Register Reserved Receive SONET Path - SONET Receive Auto Alarm Register - Byte 0 Reserved Receive SONET Path - Receive J1 Capture Register Reserved Receive SONET Path - Receive B3 Capture Register Reserved Receive SONET Path - Receive C2 Capture Register Reserved Receive SONET Path - Receive G1 Byte Capture Register Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 14 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive SONET Path - Receive F2 Byte Capture Register Reserved Receive SONET Path - Receive H4 Byte Capture Register Reserved Receive SONET Path - Receive Z3 Byte Capture Register Reserved Receive SONET Path - Receive Z4 (K3) Byte Capture Register Reserved Receive SONET Path - Receive Z5 Byte Capture Register Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN1E3 0xN1E4 - 0xN1E6 0xN1E7 0xN1E8 - 0xN1EA 0xN1EB 0xN1EC - 0xN1EE 0xN1EF 0xN1F0 - 0xN1F2 0xN1F3 0xN1F4 - 0xN1FF RECEIVE SONET POH PROCESSOR BLOCK - RECEIVE J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Receive SONET POH Processor Block - Receive J1 (Path) Trace Message Buffer - Expected and Received Reserved RECEIVE ATM CELL PROCESSOR/ PPP CELL PROCESSOR BLOCK CONTROL REGISTERS Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Receive ATM Control - Receive ATM Control Register - Byte 3 Receive ATM Control - Receive ATM Control Register - Byte 2 Receive ATM Control - Receive ATM Control Register - Byte 1 Receive ATM Cell/PPP Control - Receive ATM Control Register - Byte 0 Reserved Receive ATM Status Register- Channel 0 Reserved Receive ATM Interrupt Status Register - Byte 1 Receive ATM Cell/PPP Processor Interrupt Status Register - Byte 0 Reserved Receive ATM Cell Processor Block Interrupt Enable Register - Byte 1 Receive ATM Cell/PPP Processor Block Interrupt Enable Register - Byte 0 Receive PPP Processor - Receive Good PPP Packet Count Register - Byte 3 Receive PPP Processor - Receive Good PPP Packet Count Register - Byte 2 Receive PPP Processor - Receive Good PPP Packet Count Register - Byte 1 Receive ATM Cell Insertion/Extraction Memory Control Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN500 - 0xN53F 0xN540 - 0xN5FF 0xN700 0xN701 0xN702 0xN703 0xN704 - 0xN706 0xN707 0xN708 - 0xN709 0xN70A 0xN70B 0xN70C - 0xN70D 0xN70E 0xN70F 0xN710 0xN711 0xN712 0xN713 15 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive PPP Processor - Receive Good PPP Packet Count Register - Byte 0 0xN714 Receive ATM Cell Insertion/Extraction Memory Data Register - Byte 3 Receive PPP Processor - Receive FCS Error Count Register - Byte 3 0xN715 Receive ATM Cell Insertion/Extraction Memory Data Register - Byte 2 Receive PPP Processor - Receive FCS Error Count Register - Byte 2 0xN716 Receive ATM Cell Insertion/Extraction Memory Data Register - Byte 1 Receive PPP Processor - Receive FCS Error Count Register - Byte 1 0xN717 Receive ATM Cell Insertion/Extraction Memory Data Register - Byte 0 Receive PPP Processor - Receive FCS Error Count Register - Byte 0 0xN718 Receive ATM Programmable User Defined Field Register - Byte 3 Receive PPP Processor - Receive ABORT Count Register - Byte 3 0xN719 Receive ATM Programmable User Defined Field Register - Byte 2 Receive PPP Processor - Receive ABORT Count Register - Byte 2 0xN71A Receive ATM Programmable User Defined Field Register - Byte 1 Receive PPP Processor - Receive ABORT Count Register - Byte 1 0xN71B Receive ATM Programmable User Defined Field Register - Byte 0 Receive PPP Processor - Receive ABORT Count Register - Byte 0 0xN71C 0xN71D 0xN71E 0xN71F 0xN720 0xN721 0xN722 0xN723 0xN724 0xN725 0xN726 0xN727 0xN728 0xN729 0xN72A 0xN72B 0xN72C 0xN72D Receive PPP Processor - Receive RUNT PPP Count Register - Byte 3 Receive PPP Processor - Receive RUNT PPP Count Register - Byte 2 Receive PPP Processor - Receive RUNT PPP Count Register - Byte 1 Receive PPP Processor - Receive RUNT PPP Count Register - Byte 0 Receive ATM Controller - Test Cell Header - Byte 1 Receive ATM Controller - Test Cell Header - Byte 2 Receive ATM Controller - Test Cell Header - Byte 3 Receive ATM Controller - Test Cell Header - Byte 4 Receive ATM Controller - Test Cell Error Counter - Byte 3 Receive ATM Controller - Test Cell Error Counter - Byte 2 Receive ATM Controller - Test Cell Error Counter - Byte 1 Receive ATM Controller - Test Cell Error Counter - Byte 0 Receive ATM Controller - Receive ATM Cell Count - Byte 3 Receive ATM Controller - Receive ATM Cell Count - Byte 2 Receive ATM Controller - Receive ATM Cell Count - Byte 1 Receive ATM Controller - Receive ATM Cell Count - Byte 0 Receive ATM Controller - Receive ATM Discard Cell Count - Byte 3 Receive ATM Controller - Receive ATM Discard Cell Count - Byte 2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 0 Rev2...0...0 200 16 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive ATM Controller - Receive ATM Discard Cell Count - Byte 1 Receive ATM Controller - Receive ATM Discard Cell Count - Byte 0 Receive ATM Controller - Receive ATM Correctable HEC Cell Counter - Byte 3 Receive ATM Controller - Receive ATM Correctable HEC Cell Counter - Byte 2 Receive ATM Controller - Receive ATM Correctable HEC Cell Counter - Byte 1 Receive ATM Controller - Receive ATM Correctable HEC Cell Counter - Byte 0 Receive ATM Controller - Receive ATM Uncorrectable HEC Cell Counter - Byte 3 Receive ATM Controller - Receive ATM Uncorrectable HEC Cell Counter - Byte 2 Receive ATM Controller - Receive ATM Uncorrectable HEC Cell Counter - Byte 1 Receive ATM Controller - Receive ATM Uncorrectable HEC Cell Counter - Byte 0 -Channel 0 Reserved Receive ATM Controller - Receive ATM Filter # 0 Control Register Receive ATM Controller - Receive ATM Filter # 0 Pattern - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 0 Pattern - Header Byte 2 Receive ATM Controller - Receive ATM Filter # 0 Pattern - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 0 Pattern - Header Byte 4 Receive ATM Controller - Receive ATM Filter # 0 Check - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 0 Check - Header Byte 2 Receive ATM Controller - Receive ATM Filter # 0 Check - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 0 Check - Header Byte 4 Receive ATM Controller - Filter # 0 - Filtered Cell Count Register - Byte 3 Receive ATM Controller - Filter # 0 - Filtered Cell Count Register - Byte 2 Receive ATM Controller - Filter # 0 - Filtered Cell Count Register - Byte 1 Receive ATM Controller - Filter # 0 - Filtered Cell Count Register - Byte 0 Reserved Receive ATM Controller - Receive ATM Filter # 1 Control Register Receive ATM Controller - Receive ATM Filter # 1 Pattern - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 1 Pattern - Header Byte 2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN72E 0xN72F 0xN730 0xN731 0xN732 0xN733 0xN734 0xN735 0xN736 0xN737 0xN738 - 0xN742 0xN743 0xN744 0xN745 0xN746 0xN747 0xN748 0xN749 0xN74A 0xN74B 0xN74C 0xN74D 0xN74E 0xN74F 0xN750 - 0xN752 0xN753 0xN754 0xN755 17 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN756 0xN757 0xN758 0xN759 0xN75A 0xN75B 0xN75C 0xN75D 0xN75E 0xN75F 0xN760 - 0xN762 0xN763 0xN764 0xN765 0xN766 0xN767 0xN768 0xN769 0xN76A 0xN76B 0xN76C 0xN76D 0xN76E 0xN76F 0xN770 - 0xN772 0xN773 0xN774 0xN775 0xN776 0xN777 0xN778 0xN779 Receive ATM Controller - Receive ATM Filter # 1 Pattern - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 1 Pattern - Header Byte 4 Receive ATM Controller - Receive ATM Filter # 1 Check - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 1 Check - Header Byte 2 Receive ATM Controller - Receive ATM Filter # 1 Check - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 1 Check - Header Byte 4 Receive ATM Controller - Filter # 1 - Filtered Cell Count Register - Byte 3 Receive ATM Controller - Filter # 1 - Filtered Cell Count Register - Byte 2 Receive ATM Controller - Filter # 1 - Filtered Cell Count Register - Byte 1 Receive ATM Controller - Filter # 1 - Filtered Cell Count Register - Byte 0 Reserved Receive ATM Controller - Receive ATM Filter # 2 Control Register Receive ATM Controller - Receive ATM Filter # 2 Pattern - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 2 Pattern - Header Byte 2 Receive ATM Controller - Receive ATM Filter # 2 Pattern - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 2 Pattern - Header Byte 4 Receive ATM Controller - Receive ATM Filter # 2 Check - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 2 Check - Header Byte 2 Receive ATM Controller - Receive ATM Filter # 2 Check - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 2 Check - Header Byte 4 Receive ATM Controller - Filter # 2 - Filtered Cell Count Register - Byte 3 Receive ATM Controller - Filter # 2 - Filtered Cell Count Register - Byte 2 Receive ATM Controller - Filter # 2 - Filtered Cell Count Register - Byte 1 Receive ATM Controller - Filter # 2 - Filtered Cell Count Register - Byte 0 Reserved Receive ATM Controller - Receive ATM Filter # 3 Control Register Receive ATM Controller - Receive ATM Filter # 3 Pattern - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 3 Pattern - Header Byte 2 Receive ATM Controller - Receive ATM Filter # 3 Pattern - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 3 Pattern - Header Byte 4 Receive ATM Controller - Receive ATM Filter # 3 Check - Header Byte 1 Receive ATM Controller - Receive ATM Filter # 3 Check - Header Byte 2 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 18 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive ATM Controller - Receive ATM Filter # 3 Check - Header Byte 3 Receive ATM Controller - Receive ATM Filter # 3 Check - Header Byte 4 Receive ATM Controller - Filter # 3 - Filtered Cell Count Register - Byte 3 Receive ATM Controller - Filter # 3 - Filtered Cell Count Register - Byte 2 Receive ATM Controller - Filter # 3 - Filtered Cell Count Register - Byte 1 Receive ATM Controller - Filter # 3 - Filtered Cell Count Register - Byte 0 Reserved TRANSMIT ATM CELL PROCESSOR/ PPP PROCESSOR BLOCK REGISTERS 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN77A 0xN77B 0xN77C 0xN77D 0xN77E 0xN77F 0xN780 - 0xN901 Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Transmit ATM Cell Processor Control Register - Byte 3 Transmit ATM Cell Processor Control Register - Byte 2 Transmit ATM Cell Processor Control Register - Byte 1 Transmit ATM Cell/PPP Processor Control Register - Byte 0 Transmit ATM Status Register Reserved Transmit ATM Cell/PPP Processor Interrupt Status Register Reserved Transmit ATM Cell/PPP Processor Interrupt Enable Register Reserved Transmit ATM Cell Insertion/Extraction Memory Control Register Transmit ATM Cell Insertion/Extraction Memory - Byte 3 Transmit ATM Cell Insertion/Extraction Memory - Byte 2 Transmit ATM Cell Insertion/Extraction Memory - Byte 1 Transmit ATM Cell Insertion/Extraction Memory - Byte 0 Transmit ATM Cell - Idle Cell Header Byte # 1 Register Transmit ATM Cell - Idle Cell Header Byte # 2 Register Transmit ATM Cell - Idle Cell Header Byte # 3 Register Transmit ATM Cell - Idle Cell Header Byte # 4 Register Reserved Transmit ATM Cell - Idle Cell Payload Byte Register Transmit ATM Cell - Test Cell Header Byte # 1 Register Transmit ATM Cell - Test Cell Header Byte # 2 Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF00 0xNF01 0xNF02 0xNF03 0xNF04 0xNF05 - 0xNF0A 0xNF0B 0xNF0C - 0xNF0E 0xNF0F 0xNF10 - 0xNF12 0xNF13 0xNF14 0xNF15 0xNF16 0xNF17 0xNF18 0xNF19 0xNF1A 0xNF1B 0xNF1C - 0xNF1E 0xNF1F 0xNF20 0xNF21 19 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xNF22 0xNF23 0xNF24 - 0xNF27 0xNF28 0xNF29 0xNF2A 0xNF2B 0xNF2C 0xNF2D 0xNF2E 0xNF2F 0xNF30 0xNF31 0xNF32 0xNF33 0xNF34 0xNF35 0xNF36 0xNF37 0xNF38 - 0xNF42 0xNF43 0xNF44 0xNF45 0xNF46 0xNF47 0xNF48 0xNF49 0xNF4A 0xNF4B 0xNF4C 0xNF4D 0xNF4E Transmit ATM Cell - Test Cell Header Byte # 3 Register Transmit ATM Cell - Test Cell Header Byte # 4 Register Reserved Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Transmit ATM Cell - Discard Cell Count Register - Byte 3 Transmit ATM Cell - Discard Cell Count Register - Byte 2 Transmit ATM Cell - Discard Cell Count Register - Byte 1 Transmit ATM Cell - Discard Cell Count Register - Byte 0 Transmit ATM Cell - HEC Byte Error Count Register - Byte 3 Transmit ATM Cell - HEC Byte Error Count Register - Byte 2 Transmit ATM Cell - HEC Byte Error Count Register - Byte 1 Transmit ATM Cell - HEC Byte Error Count Register - Byte 0 Transmit ATM Cell - Parity Error Count Register - Byte 3 Transmit ATM Cell - Parity Error Count Register - Byte 2 Transmit ATM Cell - Parity Error Count Register - Byte 1 Transmit ATM Cell - Parity Error Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 0 Control Register Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 1 Control Register Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 2 Control Register Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 3 Control Register Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF4F 0xNF50 - 0xNF52 0xNF53 0xNF54 0xNF55 0xNF56 0xNF57 0xNF58 0xNF59 0xNF5A 0xNF5B 0xNF5C 0xNF5D 0xNF5E 0xNF5F 0xNF60 - 0xNF62 0xNF63 0xNF64 0xNF65 0xNF66 0xNF67 0xNF68 0xNF69 0xNF6A 0xNF6B 0xNF6C 0xNF6D 0xNF6E 0xNF6F 0xNF70 - 0xNF72 0xNF73 0xNF74 21 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xNF75 0xNF76 0xNF77 0xNF78 0xNF79 0xNF7A 0xNF7B 0xNF7C 0xNF7D 0xNF7E 0xNF7F 0xNF80 - 0xN102 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTERS Note: N represents the "Channel Number" and ranges in value from 0x05 to 0x07 Receive STS-1 Transport Control Register - Byte 0 Reserved Receive STS-1 Transport Status Register - Byte 1 Receive STS-1 Transport Status Register - Byte 0 Reserved Receive STS-1 Transport Interrupt Status Register - Byte 2 Receive STS-1 Transport Interrupt Status Register - Byte 1 Receive STS-1 Transport Interrupt Status Register - Byte 0 Reserved Receive STS-1 Transport Interrupt Enable Register - Byte 2 Receive STS-1 Transport Interrupt Enable Register - Byte 1 Receive STS-1 Transport Interrupt Enable Register - Byte 0 Receive STS-1 Transport B1 Error Count - Byte 3 Receive STS-1 Transport B1 Error Count - Byte 2 Receive STS-1 Transport B1 Error Count - Byte 1 Receive STS-1 Transport B1 Error Count - Byte 0 Receive STS-1 Transport B2 Error Count - Byte 3 Receive STS-1 Transport B2 Error Count - Byte 2 Receive STS-1 Transport B2 Error Count - Byte 1 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN103 0xN104 - 0xN105 0xN106 0xN107 0xN108 0xN109 0xN10A 0xN10B 0xN10C 0xN10D 0xN10E 0xN10F 0xN110 0xN111 0xN112 0xN113 0xN114 0xN115 0xN116 22 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive STS-1 Transport B2 Error Count - Byte 0 Reserved Receive STS-1 Transport REI-L Error Count - Byte 3 Receive STS-1 Transport REI-L Error Count - Byte 2 Receive STS-1 Transport REI-L Error Count - Byte 1 Receive STS-1 Transport REI-L Error Count - Byte 0 Reserved Receive STS-1 Transport - Received K1 Byte Value Reserved Receive STS-1 Transport - Received K2 Byte Value Reserved Receive STS-1 Transport - Received S1 Byte Value Reserved Receive STS-1 Transport - LOS Threshold Value - MSB Receive STS-1 Transport - LOS Threshold Value - LSB Reserved Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SF Set Threshold - Byte 1 Receive STS-1 Transport - Receive SF Set Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SF Clear Threshold - Byte 1 Receive STS-1 Transport - Receive SF Clear Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SD Set Threshold - Byte 1 Receive STS-1 Transport - Receive SD Set Threshold - Byte 0 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN117 0xN118 0xN119 0xN11A 0xN11B 0xN11C 0xN11D - 0xN11E 0xN11F 0xN120 - 0xN122 0xN123 0xN124 - 0xN126 0xN127 0xN128 - 0xN12D 0xN12E 0xN12F 0xN130 0xN131 0xN132 0xN133 0xN134, 0xN135 0xN136 0xN137 0xN138 - 0xN139 0xN13A 0xN13B 0xN13C 0xN13D 0xN13E 0xN13F 0xN140 - 0xN141 0xN142 0xN143 0xN144, 0xN145 23 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN146 0xN147 0xN14B - 0xN14A 0xN14B 0xN14C - 0xN14E 0xN14F 0xN150 - 0xN151 0xN152 0xN153 0xN154, 0xN155 0xN156 0xN157 0xN158 0xN159 0xN15A 0xN15B 0xN15C 0xN15D 0xN15E 0xN15F 0xN160 - 0xN162 0xN163 0xN164 - 0xN16A 0xN16B 0xN16C - 0xN182 0xN183 0xN184 - 0xN185 0xN186 0xN187 0xN188 0xN189 0xN18A 0xN18B Receive STS-1 Transport - Receive SD Clear Threshold - Byte 1 Receive STS-1 Transport - SD Clear Threshold - Byte 0 Reserved Receive STS-1 Transport - Force SEF Condition Reserved Receive STS-1 Transport - Receive J0 Trace Buffer Control Register Reserved Receive STS-1 Transport - Receive SD Burst Error Count Tolerance - Byte 1 Receive STS-1 Transport - Receive SD Burst Error Count Tolerance - Byte 0 Reserved Receive STS-1 Transport - Receive SF Burst Error Count Tolerance - Byte 1 Receive STS-1 Transport - Receive SF Burst Error Count Tolerance - Byte 0 Reserved Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Auto AIS Control Register Reserved Receive STS-1 Transport - Auto AIS (in Downstream STS-1s) Control Register Reserved Receive STS-1 Path - Control Register - Byte 2 Reserved Receive STS-1 Path - Control Register - Byte 1 Receive STS-1 Path - Status Register - Byte 0 Reserved Receive STS-1 Path - Interrupt Status Register - Byte 2 Receive STS-1 Path - Interrupt Status Register - Byte 1 Receive STS-1 Path - Interrupt Status Register - Byte 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 24 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Reserved Receive STS-1 Path - Interrupt Enable Register - Byte 2 Receive STS-1 Path - Interrupt Enable Register - Byte 1 Receive STS-1 Path - Interrupt Enable Register - Byte 0 Reserved Receive STS-1 Path - SONET Receive RDI-P Register Reserved Receive STS-1 Path - Received Path Label Value (C2 Byte) Register Receive STS-1 Path - Expected Path Label Value (C2 Byte) Register Receive STS-1 Path - B3 Error Count Register - Byte 3 Receive STS-1 Path - B3 Error Count Register - Byte 2 Receive STS-1 Path - B3 Error Count Register - Byte 1 Receive STS-1 Path - B3 Error Count Register - Byte 0 Receive STS-1 Path - REI-P Error Count Register - Byte 3 Receive STS-1 Path - REI-P Error Count Register - Byte 2 Receive STS-1 Path - REI-P Error Count Register - Byte 1 Receive STS-1 Path - REI-P Error Count Register - Byte 0 Reserved Receive STS-1 Path - Pointer Value - Byte 1 Receive STS-1 Path - Pointer Value - Byte 0 Reserved Receive STS-1 Path - AUTO AIS Control Register Reserved Receive STS-1 Path - Serial Port Control Register Reserved Receive STS-1 Path - SONET Receive Auto Alarm Register - Byte 0 Reserved Receive STS-1 Path - Receive J1 Byte Capture Register Reserved Receive STS-1 Path - Receive B3 Byte Capture Register Reserved Receive STS-1 Path - Receive C2 Byte Capture Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN18C 0xN18D 0xN18E 0xN18F 0xN190 - 0xN192 0xN193 0xN194, 0xN195 0xN196 0xN197 0xN198 0xN199 0xN19A 0xN19B 0xN19C 0xN19D 0xN19E 0xN19F 0xN1A0 - 0xN1A5 0xN1A6 0xN1A7 0xN1A8 - 0xN1BA 0xN1BB 0xN1BC - 0xN1BE 0xN1BF 0xN1C0 - 0xN1C2 0xN1C3 0xN1C4 -0xN1D2 0xN1D3 0xN1D4 - 0xN1D6 0xN1D7 0xN1D8 - 0xN1DA 0xN1DB 25 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN1DC - 0xN1DE 0xN1DF 0xN1E0 - 0xN1E2 0xN1E3 0xN1E4 - 0xN1E6 0xN1E7 0xN1E8 - 0xN1EA 0xN1EB 0xN1EC - 0xN1EE 0xN1EF 0xN1F0 - 0xN1F2 0xN1F3 0xN1F4 - 0xN1FF Reserved Receive STS-1 Path - Receive G1 Byte Capture Register Reserved Receive STS-1 Path - Receive F2 Byte Capture Register Reserved Receive STS-1 Path - Receive H4 Byte Capture Register Reserved Receive STS-1 Path - Receive Z3 Byte Capture Register Reserved Receive STS-1 Path - Receive Z4 (K3) Byte Capture Register Reserved Receive STS-1 Path - Receive Z5 Byte Capture Register Reserved Receive STS-1 TOH Processor Block - Receive J0 (Path) Trace Message Buffer Note: N represents the "Channel Number" and ranges in value from 0x05 to 0x07 Receive STS-1 POH Processor Block - Receive J0 (Path) Trace Message Buffer - Expected and Received Reserved 0x00 0x00 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN300 - 0xN33F 0xN340 - 0xN3FF RECEIVE STS-1 POH PROCESSOR BLOCK - RECEIVE J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the "Channel Number" and ranges in value from 0x05 to 0x07 Receive STS-1 POH Processor Block - Receive J1 (Path) Trace Message Buffer - Expected and Received Reserved DS3/E3 MAPPER BLOCK REGISTER Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Unused Mapper Control Register - Byte 2 Mapper Control Register - Byte 1 Mapper Control Register - Byte 0 Unused Receive Mapper Status Register - Byte 1 Receive Mapper Status Register - Byte 0 Unused Receive Mapper Interrupt Status Register - Byte 0 0x00 0x00 0x03 0x80 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0xN500 - 0xN53F 0xN540 - 0xN5FF 0xNA00 - 0xNB00 0xNB01 0xNB02 0xNB03 0xNB04, 0xNB05 0xNB06 0xNB07 0xNB08 - 0xNB0A 0xNB0B 26 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Unused Receive Mapper Interrupt Enable Register - Byte 0 Unused T3/E3 Routing Register Byte Reserved TRANSMIT SONET POH PROCESSOR BLOCK REGISTERS 0x00 0x00 0x00 0x00 0x00 0xNB0C - 0xNB0E 0xNB0F 0xNB10 - 0xNB12 0xNB13 0xNB14 - 0xNBFF Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04) Reserved Transmit SONET Path - SONET Control Register - Byte 1 Transmit SONET Path - SONET Control Register - Byte 0 Reserved Transmit SONET Path - Transmitter J1 Byte Value Register Reserved Transmit SONET Path - B3 Byte Control Register Transmit SONET Path - B3 Byte Mask Register Reserved Transmit SONET Path - Transmit C2 Byte Value Register Reserved Transmit SONET Path - Transmit G1 Byte Value Register Reserved Transmit SONET Path - Transmit F2 Byte Value Register Reserved Transmit SONET Path - Transmit H4 Byte Value Register Reserved Transmit SONET Path - Transmit Z3 Byte Value Register Reserved Transmit SONET Path - Transmit Z4 Byte Value Register Reserved Transmit SONET Path - Transmit Z5 Byte Value Register Reserved Transmit SONET Path - Transmit Path Control Register - Byte 0 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN800 - 0xN981 0xN982 0xN983 0xN984 - 0xN8992 0xN993 0xN994 - 0xN995 0xN996 0xN997 0xN998 - 0xN99A 0xN99B 0xN99C - 0xN99E 0xN99F 0xN9A0 - 0xN9A2 0xN9A3 0xN9A4 - 0xN9A6 0xN9A7 0xN9A8 - 0xN9AA 0xN9AB 0xN9AC - 0xN9AE 0xN9AF 0xN9B0 - 0xN9B2 0xN9B3 0xN9B4 - 0xN9B6 0xN9B7 0xN9B8 - 0xN9BA 27 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN9BB 0xN9BC - 0xN9BE 0xN9BF 0xN9C0 - 0xN9C2 0xN9C3 0xN9C4 - 0xN9C5 0xN9C6 0xN9C7 0xN9C8 0xN9C9 0xN9CA 0xN9CB 0xN9CC - 0xN9CE 0xN9CF 0xN9D0 - 0xN9FF Transmit SONET Path - Transmit J1 Control Register Reserved Transmit SONET Path - Transmit Arbitrary H1 Pointer Register Reserved Transmit SONET Path - Transmit Arbitrary H2 Pointer Register Reserved Transmit SONET Path - Transmit Pointer Byte Register - Byte 1 Transmit SONET Path - Transmit Pointer Byte Register - Byte 0 Reserved Transmit SONET Path - RDI-P Control Register - Byte 2 Transmit SONET Path - RDI-P Control Register - Byte 1 Transmit SONET Path - RDI-P Control Register - Byte 0 Reserved Transmit SONET Path - Transmit Path Serial Port Control Register Reserved 20 0 Rev2...0...0 200 0x00 0x00 0x94 0x00 0x00 0x00 0x02 0x0A 0x00 0x40 0xC0 0xA0 0x00 0x00 0x00 TRANSMIT SONET POH PROCESSOR BLOCK - TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Transmit SONET POH Processor Block - Transmit J1 (Path) Trace Message Buffer Reserved TRANSMIT STS-1 TOH AND POH PROCESSOR BLOCK REGISTERS Note: N represents the "Channel Numbers" and ranges in value from 0x05 to 0x07) Reserved Transmit STS-1 Transport - SONET Transmit Control Register - Byte 1 Transmit STS-1 Transport - SONET Transmit Control Register - Byte 0 Reserved Transmit STS-1 Transport - B1 Byte Error Mask Register Reserved Transmit STS-1 Transport - Transmit B2 Bit Error Mask Register - Byte 0 Reserved Transmit STS-1 Transport - K1K2 (APS) Value Register - Byte 1 Transmit STS-1 Transport - K1K2 (APS) Value Register - Byte 0 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xND00 - 0xND3F 0xND40 - 0xNEFF 0xN800 - 0xN901 0xN902 0xN903 0xN904 - 0xN922 0xN923 0xN924 - 0xN92A 0xN92B 0xN92C - 0xN92D 0xN92E 0xN92F 0xN930 - 0xN932 28 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transmit STS-1 Transport - RDI-L Control Register Reserved Transmit STS-1 Transport - M0M1 Value Register Reserved Transmit STS-1 Transport - S1 Byte Value Register Reserved Transmit STS-1 Transport - F1 Byte Value Register Reserved Transmit STS-1 Transport - E1 Byte Value Register Reserved Transmit STS-1 Transport - E2 Byte Value Register Reserved Transmit STS-1 Transport - J0 Byte Value Register Reserved Transmit STS-1 Transport - J0 Byte Control Register Reserved Transmit STS-1 Path - SONET Control Register - Byte 1 Transmit STS-1 Path - SONET Control Register - Byte 0 Reserved Transmit STS-1 Path - Transmitter J1 Byte Value Register Reserved Transmit STS-1 Path - B3 Byte Control Register Transmit STS-1 Path - B3 Byte Mask Register Reserved Transmit STS-1 Path - Transmit C2 Byte Value Register Reserved Transmit STS-1 Path - Transmit G1 Byte Value Register Reserved Transmit STS-1 Path - Transmit F2 Byte Value Register Reserved Transmit STS-1 Path - Transmit H4 Value Register Reserved Transmit STS-1 Path - Transmit Z3 Value Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN933 0xN934 - 0xN936 0xN937 0xN938 - 0xN93A 0xN93B 0xN93C - 0xN93E 0xN93F 0xN940 - 0xN942 0xN943 0xN944 - 0xN946 0xN947 0xN948 - 0xN94A 0xN94B 0xN94C - 0xN94E 0xN94F 0xN950 - 0xN981 0xN982 0xN983 0xN984 - 0xN992 0xN993 0xN994 - 0xN995 0xN996 0xN997 0xN998 - 0xN99A 0xN99B 0xN99C - 0xN99E 0xN99F 0xN9A0 - 0xN9A2 0xN9A3 0xN9A4 - 0xN9A6 0xN9A7 0xN9A8 - 0xN9AA 0xN9AB 29 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN9AC - 0xN9AE 0xN9AF 0xN9B0 - 0xN9B2 0xN9B3 0xN9B4 - 0xN9B6 0xN9B7 0xN9B8 - 0xN9BA 0xN9BB 0xN9BC - 0xN9BE 0xN9BF 0xN9C0 - 0xN9C2 0xN9C3 0xN9C4 - 0xN9C5 0xN9C6 0xN9C7 0xN9C8 0xN9C9 0xN9C2 0xN9CB 0xN9CC - 0xN9CE 0xN9CF 0xN9D0 -0xN9FF Reserved Transmit STS-1 Path - Transmit Z4 Value Register Reserved Transmit STS-1 Path - Transmit Z5 Value Register Reserved Transmit STS-1 Path - Transmit Path Control Register - Byte 0 Reserved Transmit STS-1 Path - Transmit J1 Control Register Reserved Transmit STS-1 Path - Transmit Arbitrary H1 Pointer Register Reserved Transmit STS-1 Path - Transmit Arbitrary H2 Pointer Register Reserved Transmit STS-1 Path - Transmit Pointer Byte Register - Byte 1 Transmit STS-1 Path - Transmit Pointer Byte Register - Byte 0 Reserved Transmit STS-1 Path - RDI-P Control Register - Byte 2 Transmit STS-1 Path - RDI-P Control Register - Byte 1 Transmit STS-1 Path - RDI-P Control Register - Byte 0 Reserved Transmit STS-1 Path - Transmit Path Serial Port Control Register Reserved 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x94 0x00 0x00 0x00 0x02 0x0A 0x00 0x40 0xC0 0xA0 0x00 0x00 0x00 TRANSMIT STS-1 TOH PROCESSOR BLOCK - TRANSMIT J0 (PATH) TRACE MESSAGE BUFFER Note: N represents the "Channel Number" and ranges in value from 0x05 to 0x07 Transmit STS-1 POH Processor Block - Transmit J0 (Path) Trace Message Buffer Reserved 0x00 0x00 0xNB00 - 0xNB3F 0xNB40 - 0xNBFF TRANSMIT STS-1 POH PROCESSOR BLOCK - TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the "Channel Number" and ranges in value from 0x05 to 0x07 Transmit STS-1 POH Processor Block - Transmit J1 (Path) Trace Message Buffer Reserved DS3/E3 FRAMER BLOCK REGISTERS Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 0x00 0x00 0xND00 - 0xND3F 0xND40 - 0xNDFF 30 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Operating Mode Register I/O Control Register Reserved Block Interrupt Enable Register Block Interrupt Status Register Reserved Test Register Reserved RxDS3 Configuration and Status Register RxE3 Configuration and Status Register # 1 - G.832 RxE3 Configuration and Status Register # 2 - G.751 0x23 0xA0 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0xN300 0xN301 0xN302 - 0xN303 0xN304 0xN305 0xN306 - 0xN30B 0xN30C 0xN30D - 0xN30F 0xN310 0xN311 RxDS3 Status Register RxE3 Configuration and Status Register # 2 - G.832 RxE3 Configuration and Status Register # 2 - G.751 0x67 0xN312 RxDS3 Interrupt Enable Register RxE3 Interrupt Enable Register # 1 - G.832 RxE3 Interrupt Enable Register # 1 - G.751 0x00 0xN313 RxDS3 Interrupt Status Register RxE3 Interrupt Enable Register # 2 - G.832 RxE3 Interrupt Enable Register # 2 - G.751 0x00 0xN314 RxDS3 Sync Detect Enable Register RxE3 Interrupt Status Register # 1 - G.832 RxE3 Interrupt Status Register # 1 - G.751 0x00 0xN315 RxE3 Interrupt Status Register # 2 - G.832 RxE3 Interrupt Status Register # 2 - G.751 0x00 0xN316 0xN317 0xN318 RxDS3 FEAC Register RxDS3 FEAC Interrupt Enable/Status Register RxDS3 LAPD Control Register RxE3 LAPD Control Register 0x7E 0x00 0x00 0xN319 RxDS3 LAPD Status Register RxE3 LAPD Status Register 0x00 0xN31A RxE3 NR Byte Register - G.832 RxE3 Service Bit Register -G.751 0x00 0xN31B 0xN31C RxE3 GC Byte Register - G.832 RxE3 TTB-0 Register - G.832 0x00 0x00 31 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN31D 0xN31E 0xN31F 0xN320 0xN321 0xN322 0xN323 0xN324 0xN325 0xN326 0xN327 0xN328 0xN329 0xN32A 0xN32B 0xN32C 0xN32D - 0xN32E 0xN32F 0xN330 RxE3 TTB-1 Register - G.832 RxE3 TTB-2 Register - G.832 RxE3 TTB-3 Register -G.832 RxE3 TTB-4 Register -G.832 RxE3 TTB-5 Register -G.832 RxE3 TTB-6 Register - G.832 RxE3 TTB-7 Register - G.832 RxE3 TTB-8 Register - G.832 RxE3 TTB-9 Register - G.832 RxE3 TTB-10 Register - G.832 RxE3 TTB-11 Register -G.832 RxE3 TTB-12 Register - G.832 RxE3 TTB-13 Register - G.832 RxE3 TTB-14 Register - G.832 RxE3 TTB-15 Register -G.832 RxE3 SSM Register -G.832 Reserved RxDS3 Pattern Register TxDS3 Configuration Register TxE3 Configuration Register - G.832 TxE3 Configuration Register - G.751 0xN331 0xN332 0xN333 TxDS3 FEAC Configuration and Status Register TxDS3 FEAC Register TxDS3 LAPD Configuration Register TxE3 LAPD Configuration Register 0xN334 TxDS3 LAPD Status/Interrupt Register TxE3 LAPD Status/Interrupt Register 0xN335 TxDS3 M-Bit Mask Register TxE3 GC Byte Register - G.832 TxE3 Service Bits Register - G.751 0xN336 TxDS3 F-Bit Mask # 1 Register TxE3 MA Byte Register - G.832 0xN337 TxDS3 F-Bit Mask # 2 Register TxE3 NR Byte Register - G.832 0x00 0x00 0x00 0x00 0x00 0x7E 0x08 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 32 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TxDS3 F-Bit Mask # 3 Register TxE3 TTB-0 Register - G.832 0x00 0xN338 0xN339 TxDS3 F-Bit Mask # 4 Register TxE3 TTB-1 Register - G.832 0x00 0xN33A 0xN33B 0xN33C 0xN33D 0xN33E 0xN33F 0xN340 0xN341 0xN342 0xN343 0xN344 0xN345 0xN346 0xN347 0xN348 TxE3 TTB-2 Register - G.832 TxE3 TTB-3 Register - G.832 TxE3 TTB-4 Register - G.832 TxE3 TTB-5 Register - G.832 TxE3 TTB-6 Register - G.832 TxE3 TTB-7 Register - G.832 TxE3 TTB-8 Register -G.832 TxE3 TTB-9 Register - G.832 TxE3 TTB-10 Register - G.832 TxE3 TTB-11 Register - G.832 TxE3 TTB-12 Register - G.832 TxE3 TTB-13 Register - G.832 TxE3 TTB-14 Register - G.832 TxE3 TTB-15 Register -G.832 TxE3 FA1 Error Mask Register - G.832 TxE3 FAS Error Mask Upper Register - G.751 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xN349 TxE3 FA2 Error Mask Register - G.832 TxE3 FAS Error Mask Lower Register - G.751 0x00 0xN34A TxE3 BIP-8 Mask Register - G.832 TxE3 BIP-4 Mask Register - G.751 0x00 0xN34B 0xN34C 0xN34D 0xN34E 0xN34F 0xN350 0xN351 0xN352 0xN353 0xN354 Tx SSB Register - G.832 TxDS3 Pattern Register Receive DS3/E3 AIS/PDI-P Alarm Enable Register PMON Excessive Zero Count Register - MSB PMON Excessive Zero Count Register- LSB PMON LCV Event Count Register - MSB PMON LCV Event Count Register - LSB PMON Framing Bit/Byte Error Count Register - MSB PMON Framing Bit/Byte Error Count Register - LSB PMON Parity Error Event Count Register - MSB 0x00 0x0C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 33 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xN355 0xN356 0xN357 0xN358 0xN359 0xN35A 0xN35B 0xN35C 0xN35D 0xN35E 0xN35F 0xN360 - 0xN367 0xN368 0xN369 0xN36A - 0xN36B 0xN36C 0xN36D 0xN36E 0xN36F 0xN370 0xN371 0xN372 0xN373 0xN374 - 0xN37F 0xN380 0xN381 0xN382 0xN383 0xN384 0xN385 - 0xN389 0xN390 0xN391 0xN392 PMON Parity Error Event Count Register - LSB PMON FEBE Event Count Register- MSB PMON FEBE Event Count Register - LSB PMON CP-Bit Error Count Register - MSB PMON CP-Bit Error Count Register - LSB PMON PLCP BIP-8 Error Count Register - MSB PMON PLCP BIP-8 Error Count Register - LSB PMON PLCP Framing Byte Error Count Register - MSB PMON PLCP Framing Byte Error Count Register - LSB PMON PLCP FEBE Error Count Register - MSB PMON PLCP FEBE Error Count Register - LSB Reserved PMON PRBS Bit Error Count Register - MSB PMON PRBS Bit Error Count Register - LSB Reserved PMON Holding Register One Second Error Status Register One Second - LCV Count Accumulator Register - MSB One Second - LCV Count Accumulator Register - LSB One Second - Parity Error Accumulator Register - MSB One Second - Parity Error Accumulator Register - LSB One Second - CP Bit Error Accumulator Register - MSB One Second - CP Bit Error Accumulator Register - LSB Reserved Reserved Line Interface Scan Register Reserved Transmit LAPD Byte Count Register Receive LAPD Byte Count Register Reserved Receive PLCP Configuration and Status Register Receive PLCP Interrupt Enable Register Receive PLCP Interrupt Status Register 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 34 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Reserved Transmit PLCP A1 Byte Error Mask Register Transmit PLCP A2 Byte Error Mask Register Transmit PLCP BIP-8 Error Mask Register Transmit PLCP G1 Byte Register Reserved Transmit LAPD Memory Indirect Address Register Transmit LAPD Memory Indirect Data Register Receive LAPD Memory Indirect Address Register Receive LAPD Memory Indirect Data Register Reserved Receive DS3/E3 Configuration Register - Secondary Frame Synchronizer Block - Byte 1 Receive DS3/E3 Configuration Register - Secondary Frame Synchronizer Block - Byte 0 Receive DS3/E3 AIS/PDI-P Alarm Enable Register - Secondary Frame Synchronizer Block Reserved Receive DS3/E3 Interrupt Enable Register - Secondary Frame Synchronizer Block Receive DS3/E3 Interrupt Status Register - Secondary Frame Synchronizer Block RECEIVE STS-3C POH PROCESSOR BLOCK 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x10 0x00 0x00 0x00 0x00 0xN393 - 0xN397 0xN398 0xN399 0xN39A 0xN39B 0xN39C - 0xN3AF 0xN3B0 0xN3B1 0xN3B2 0xN3B3 0xN3B4 - 0xN3EF 0xN3F0 0xN3F1 0xN3F2 0xN3F3 - 0xN3F7 0xN3F8 0xN3F9 0x1000 - 0x1181 0x1182 0x1183 0x1184 - 0x1185 0x1186 0x1187 0x1188 0x1189 0x118A 0x118B 0x118C 0x118D Reserved Receive STS-3c Path - Control Register - Byte 1 Receive STS-3c Path - Control Register - Byte 0 Reserved Receive STS-3c Path - Status Register - Byte 1 Receive STS-3c Path - Status Register - Byte 0 Reserved Receive STS-3c Path - Interrupt Status Register - Byte 2 Receive STS-3c Path - Interrupt Status Register - Byte 1 Receive STS-3c Path - Interrupt Status Register - Byte 0 Reserved Receive STS-3c Path - Interrupt Enable Register - Byte 2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 35 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x118E 0x118F 0x1190 - 0x1192 0x1193 0x1194 - 0x1195 0x1196 0x1197 0x1198 0x1199 0x119A 0x119B 0x119C 0x119D 0x119E 0x119F 0x11A0 - 0x11A2 0x11A3 0x11A4 - 0x11A5 0x11A6 0x11A7 0x11A8 - 0x11AA 0x11AB 0x11AC - 0x11B2 0x11B3 0x11B4 - 0x11BA 0x11BB 0x11BC - 0x11BE 0x11BF 0x11C0 - 0x11C2 0x11C3 0x11C4 -0x11D2 0x11D3 0x11D4 - 0x11D6 Receive STS-3c Path - Interrupt Enable Register - Byte 1 Receive STS-3c Path - Interrupt Enable Register - Byte 0 Reserved Receive STS-3c Path - SONET Receive RDI-P Register Reserved Receive STS-3c Path - Receive Path Label Byte (C2) Register Receive STS-3c Path - Expected Path Label Byte (C2) Register Receive STS-3c Path - B3 Error Count Register - Byte 3 Receive STS-3c Path - B3 Error Count Register - Byte 2 Receive STS-3c Path - B3 Error Count Register - Byte 1 Receive STS-3c Path - B3 Error Count Register - Byte 0 Receive STS-3c Path - REI-P Error Count Register - Byte 3 Receive STS-3c Path - REI-P Error Count Register - Byte 2 Receive STS-3c Path - REI-P Error Count Register - Byte 1 Receive STS-3c Path - REI-P Error Count Register - Byte 0 Reserved Receive STS-3c Path - Receive J1 Byte Control Register Reserved Receive STS-3c Path - Pointer Value Register - Byte 1 Receive STS-3c Path - Pointer Value Register - Byte 0 Reserved Receive STS-3c Path - Loss of Pointer - Concatenation Status Register Reserved Receive STS-3c Path - AIS - Concatenation Status Register Reserved Receive STS-3c Path - Auto AIS Control Register Reserved Receive STS-3c Path - Serial Port Control Register Reserved Receive STS-3c Path - SONET Receive Auto Alarm Register - Byte 0 Reserved Receive STS-3c Path - Receive J1 Byte Capture Register Reserved 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 36 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive STS-3c Path - Receive B3 Byte Capture Register Reserved Receive STS-3c Path - Receive C2 Byte Capture Register Reserved Receive STS-3c Path - Receive G1 Byte Capture Register Reserved Receive STS-3c Path - Receive F2 Byte Capture Register Reserved Receive STS-3c Path - Receive H4 Byte Capture Register Reserved Receive STS-3c Path - Receive Z3 Byte Capture Register Reserved Receive STS-3c Path - Receive Z4 (K3) Byte Capture Register Reserved Receive STS-3c Path - Receive Z5 Byte Capture Register Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x11D7 0x11D8 - 0x11DA 0x11DB 0x11DC - 0x11DE 0x11DF 0x11E0 - 0x11E2 0x11E3 0x11E4 - 0x11E6 0x11E7 0x11E8 - 0x11EA 0x11EB 0x11EC - 0x11EE 0x11EF 0x11F0 - 0x11F2 0x11F3 0x11F4 - 0x11FF RECEIVE STS-3C POH PROCESSOR BLOCK - RECEIVE J1 (PATH) TRACE MESSAGE BUFFER - STS-3C 0x1500 - 0x153F 0x1540 - 0x15FF Receive STS-3c POH Processor Block - Receive J1 (Path) Trace Message Buffer Reserved TRANSMIT STS-3C POH PROCESSOR BLOCK 0x1900 - 0x1981 0x1982 0x1983 0x1984 - 0x1992 0x1993 0x1994 - 0x1996 0x1997 0x1998 - 0x199A 0x199B 0x199C - 0x199E 0x199F 0x19A0 - 0x19A2 0x19A3 Reserved Transmit STS-3c Path - SONET Control Register - Byte 1 Transmit STS-3c Path - SONET Control Register- Byte 0 Reserved Transmit STS-3c Path - Transmit J1 Byte Value Register Reserved Transmit STS-3c Path - B3 Byte Mask Register Reserved Transmit STS-3c Path - Transmit C2 Byte Value Register Reserved Transmit STS-3c Path - Transmit G1 Byte Value Register Reserved Transmit STS-3c Path - Transmit F2 Byte Value Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 37 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0x19A4 -0x19A6 0x19A7 0x19A8 - 0x19AA 0x19AB 0x19AC - 0x19AE 0x19AF 0x19B0 - 0x19B2 0x19B3 0x19B4 - 0x19B6 0x19B7 0x19B8 - 0x19BA 0x19BB 0x19BC -0x19BE 0x19BF 0x19C0 - 0x19C2 0x19C3 0x19C4 - 0x19C5 0x19C6 0x19C7 0x19C8 0x19C9 0x19CA 0x19CB 0x19CC -0x19CE 0x19CF 0x19D0 - 0x1AFF Reserved Transmit STS-3c Path - Transmit H4 Byte Value Register Reserved Transmit STS-3c Path - Transmit Z3 Byte Value Register Reserved Transmit STS-3c Path - Transmit Z4 Byte Value Register Reserved Transmit STS-3c Path - Transmit Z5 Byte Value Register Reserved Transmit STS-3c Path - Transmit Path Control Register - Byte 0 Reserved Transmit STS-3c Path- Transmit J1 Byte Control Register Reserved Transmit STS-3c Path - Transmit Arbitrary H1 Byte Pointer Register Reserved Transmit STS-3c Path - Transmit Arbitrary H2 Byte Pointer Register Reserved Transmit STS-3c Path - Transmit Pointer Byte Register -Byte 1 Transmit STS-3c Path - Transmit Pointer Byte Register - Byte 0 Reserved Transmit STS-3c Path - RDI-P Control Register - Byte 2 Transmit STS-3c Path -RDI-P Control Register - Byte 1 Transmit STS-3c Path - RDI-P Control Register - Byte 0 Reserved Transmit STS-3c Path - Transmit Path Serial Port Control Register Reserved 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 TRANSMIT STS-3C POH PROCESSOR BLOCK - TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER 0x1D00 - 0x1D3F 0x1D40 - 0x1DFF Transmit STS-3c POH Processor Block -Transmit J1 (Path) Trace Message Buffer Reserved 0x00 0x00 38 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.2 THE OPERATION CONTROL BLOCK The Operation Control Block is responsible for the following functions. * Control of the Interrupt Structure (at the Highest Level within the XRT94L33) * Control of the Clock Synthesizer block * Control of the STS-3/STM-1 Telecom Bus Interface * Control of the STS-1 Telecom Bus Interfaces The register map for the Operation Control block is presented in the Table below. Additionally, a detailed description of each of the "Operation Control" Block registers is presented below. 1.2.1 OPERATION CONTROL BLOCK REGISTER Table 2: Operation Control Register Address Map INDIVIDUAL REGISTER ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 - 0x0A 0x0B 0x0C - 0x0E 0x0F 0x10 - 0x11 0x12 0x13 0x14 - 0x15 0x16 0x17 0x18 - 0x19 0x1A 0x1B 0x1C - 0x1E 0x1F ADDRESS LOCATION 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 - 0x010A 0x010B 0x010C - 0x010E 0x010F 0x0110 - 0x0111 0x0112 0x0113 0x0114 - 0x0115 0x0116 0x0117 0x0118 - 0x0119 0x0111A 0x011B 0x011C - 0x011E 0x011F REGISTER NAME DEFAULT VALUE Operation Control Register - Byte 3 Operation Control Register - Byte 2 Reserved Operation Control Register - Byte 0 Operation Status Register - Byte 3 (Device ID) Operation Status Register - Byte 2 (Revision ID) Reserved Operation Interrupt Status Register - Byte 0 Reserved Operation Interrupt Enable Register - Byte 0 Reserved Operation Block Interrupt Status Register - Byte 1 Operation Block Interrupt Status Register - Byte 0 Reserved Operation Block Interrupt Enable Register - Byte 1 Operation Block Interrupt Enable Register - Byte 0 Reserved Reserved Mode Control Register - Byte 0 Reserved Loop-back Control Register - Byte 0 0x00 0x00 0x00 0x00 0xE3 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 39 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B - 0x2F 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E ADDRESS LOCATION 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A 0x012B - 0x012F 0x012E 0x012F 0x0130 0x0131 0x0132 0x0133 0x0134 0x0135 0x0136 0x0137 0x0138 0x0139 0x013A 0x013B 0x013C 0x013D 0x013E REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUE Channel Interrupt Indicator - Receive SONET POH Processor Block Reserved Channel Interrupt Indicator - DS3/E3 framer Block Channel Interrupt Indicator - Receive STS-1 POH Processor Block Channel Interrupt Indicator - Receive STS-1 TOH Processor Block Reserved Channel Interrupt Indicator - STS-1/DS3/E3 Mapper Block Reserved Reserved Reserved Reserved Unused Reserved Reserved Reserved Reserved Interface Control Register - Byte 1 Interface Control Register - Byte 0 STS-3/STM-1 Telecom Bus Control Register - Byte 3 STS-3/STM-1 Telecom Bus Control Register - Byte 2 Reserved STS-3/STM-1 Telecom Bus Control Register - Byte 0 Reserved Interface Control Register - Byte 2 - STS-1 Telecom Bus 2 Interface Control Register - Byte 1 - STS-1 Telecom Bus 1 Interface Control Register - Byte 0 - STS-1 Telecom Bus 0 Interface Control Register - STS-1 Telecom Bus Interrupt Register Interface Control Register - STS-1 Telecom Bus Interrupt Status Register Interface Control Register - STS-1 Telecom Bus Interrupt 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 40 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION Register # 2 REGISTER NAME DEFAULT VALUE INDIVIDUAL REGISTER ADDRESS 0x3F 0x40 - 0x45 0x46 0x47 0x48 - 0x49 0x4A 0x4B 0x4C - 0x4F 0x50 0x51 - 0x52 0x53 0x54 0x55 - 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 - 0x7F 0x80 0x81 0x82 - 0x93 0x94 0x013F 0x0140 - 0x0145 0x0146 0x0147 0x0148 - 0x0149 0x014A 0x014B 0x014C - 0x014F 0x0150 0x0151 -0x0152 0x0153 0x0154 0x0155 - 0x0156 0x0157 0x0158 0x0159 0x015A 0x015B 0x015C 0x015D 0x015E 0x015F 0x0160 - 0x017F 0x0180 0x0181 0x0182 - 0x0193 0x0194 Interface Control Register - STS-1 Telecom Bus Interrupt Enable Register Reserved Reserved Operation General Purpose Input/Output Register Reserved Reserved Operation General Purpose Input/Output Direction Register Reserved Operation Output Control Register - Byte 1 Reserved Operation Output Control Register - Byte 0 Operation Slow Speed Port Control Register - Byte 1 Reserved Operation Slow Speed Port Control Register -Byte 0 Operation - DS3/E3/STS-1 Clock Frequency Out of Range Detection - Direction Register Reserved Operation - DS3/E3/STS-1 Clock Frequency - DS3 Out of Range Detection Threshold Register Operation - DS3/E3/STS-1 Clock Frequency - STS-1/E3 Out of Range Detection Threshold Register Reserved Operation - DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register - Byte 0 Reserved Operation - DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register - Byte 0 Reserved APS Mapping Register APS Control Register Reserved APS Status Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 41 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 - 0xFF ADDRESS LOCATION 0x0195 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D 0x019E 0x019F 0x01A0 - 0x01FF Reserved APS Status Register APS Status Register APS Interrupt Register Reserved APS Interrupt Register APS Interrupt Register APS Interrupt Register Reserved APS Interrupt Enable Register APS Interrupt Enable Register Reserved REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 42 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS OPERATION CONTROL REGISTER DESCRIPTIONS 1.2.2 Table 3: Operation Control Register - Byte 3 (Address Location= 0x0100) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 Unused R/O 0 R/O 0 R/W 0 BIT 3 BIT 2 BIT 1 R/W 0 BIT 0 R/W 0 Configuration Control [1:0] BIT NUMBER Bit 7 - Bit 2 Bit 1 - Bit 0 NAME Unused Configuration Control [1:0] TYPE R/O R/W DESCRIPTION Please set to "0" for normal operation. Configuration Control [1:0]: This READ/WRITE bit-field permits the user to determine the configuration of the XRT94L33. The XRT94L33 can be configured for both Mapper applications and ATM/PPP applications. For Mapper applications, please refer to our "3channel DS3/E3/STS-1 To STS-3/STM-1 Mapper IC Datasheet". For ATM/PPP applications, the XRT94L33 can have the following configurations: Configuration Control [1:0] 00 Operation Modes If the user set these bits to "00", the user is allowing the XRT94L33 to be configured as the following: a. A single STS-3c ATM UNI and two-channel DS3/E3 ATM/PPP/HDLC/Clear Channel device A single STS3-c ATM UNI and two-channel STS-1 ATM UNI device. A single STS-3c PPP and two-channel DS3/E3 ATM/PPP/HDLC/Clear Channel device A single STS3-c PPP and two-channel STS1 PPP device. b. c. d. 01 If the user set these bits to "01", the user is allowing the XRT94L33 to be configured as a 3 channel DS3/E3 ATM UNI/PPP/HDLC/Clear Channel to STS3 device (See Figure 1) 10 If the user set these bits to "10", the user is allowing the XRT94L33 to be configured as either a 3-channel STS-1/DS3/E3 to ATM/PPP device (See Figure 2) or as a 3 channel DS3/E3 to HDLC/CC device (See Figure 3). 11 If the user set these bits to "11", the user is allowing the XRT94L33 to be configured as a 3 channel ATM/PPP to STS-3 device (See Figure 4). 43 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Figure 1: Functional Block Diagram for 3-channel DS3/E3 ATM UNI/PPP to STS-3 Applications From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 44 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Figure 2: Functional Block Diagram for 3-channel DS3/E3/STS-1 ATM UNI/PPP Applications Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx PPP Tx PPP Processor Processor Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx PPP Rx PPP Processor Processor Block Block Channel 0 Figure 3: Functional Block Diagram for 3-channel DS3/E3 HDLC/Clear Channel Applications Tx Tx Overhead Overhead Data Input Data Input Interface Interface Block Block Tx Payload Tx Payload Data Input Data Input Interface Interface Block Block Tx HDLC Tx HDLC Controller Controller Block Block Tx PMDL/ Tx PMDL/ FEAC FEAC Controller Controller Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Rx Payload Rx Payload Data Output Data Output Interface Interface Block Block Rx HDLC Rx HDLC Controller Controller Block Block Rx Rx Overhead Overhead Data Output Data Output Interface Interface Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx PMDL/ Rx PMDL/ FEAC FEAC Controller Controller Block Block Channel 0 Figure 4: Functional Block Diagram for STS-3 ATM UNI/PPP Applications 45 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS From Channel 1 & 2 Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block 20 0 Rev2...0...0 200 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx PPP Tx PPP Processor Processor Block Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx Cell Tx Cell Processor Processor Block Block Tx ATM/ Tx ATM/ PPP PPP Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx Cell Rx Cell Processor Processor Block Block Rx ATM/ Rx ATM/ PPP PPP Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx PPP Rx PPP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block Table 4: Operation Control Register - Byte 2 (Address Location= 0x0101) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Interrupt Write Clear/RUR R/O 0 R/O 0 R/W 0 BIT 1 Enable Interrupt Clear R/W 0 BIT 0 Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER Bit 7 - Bit 3 Bit 2 NAME Unused Interrupt Write to Clear/RUR TYPE R/O R/W DESCRIPTION Please set to "0" for normal operation. Interrupt - Write to Clear/RUR Select: This READ/WRITE bit-field permits the user to configure all of the "SourceLevel" Interrupt Status bits (within the XRT94L33) to either be "Write to Clear" (WTC) or "Reset-upon-Read" (RUR) bits. 0 - Configures all "Source-Level" Interrupt Status register bits to function as "Reset-upon-Read" (RUR). 1 - Configures all "Source-Level" Interrupt Status register bits to function as "Write-to-Clear" (WTC). Bit 1 Enable Interrupt Clear R/W Enable Auto-Clear of Interrupts Select: This READ/WRITE bit-field permits the user to configure the XRT94L33 to automatically disable all interrupts that are activated. 0 - Configures the chip to NOT automatically disable any Interrupts following their activation. 1 - Configures the chip to automatically disable all Interrupts following their 46 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS activation. Bit 0 Interrupt Enable R/W Interrupt Enable: This READ/WRITE bit-field permits the user to configure the XRT94L33 to generate interrupt requests to the Microprocessor. 0 - Configures the chip to NOT generate interrupt to the Microprocessor. All interrupts are disabled and the Microprocessor must poll the register bits. 1 - Configures the chip to generate interrupts the Microprocessor. 47 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 5: Operation Control Register - Byte 0 (Address Location= 0x0103) BIT 7 Transmit UTOPIA PLL OFF R/W 1 BIT 6 Receive UTOPIA PLL OFF R/W 1 R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 BIT 2 PPP/ATM BIT 1 BIT 0 SW RESET R/O 0 R/W 0 20 0 Rev2...0...0 200 R/W 0 BIT NUMBER 7 NAME Transmit UTOPIA PLL OFF Receive UTOPIA PLL OFF Unused PPP/ATM TYPE R/W DESCRIPTION 6 R/W 5-3 2 R/O R/W PPP/ATM UNI Mode Select: This READ-WRITE bit-field permits the user to configure the XRT94L33 to operate in either the ATM UNI or PPP Mode. 0 - Configures the UTOPIA/POS-PHY bus to operate in the UTOPIA (ATM) Mode. 1 - Configures the UTOPIA/POS-PHY Bus to operate in the POS-PHY Mode. 1 Bit 0 Unused SW Reset R/O R/W Please set to "0" for normal operation Software Reset - SONET Block: This READ/WRITE bit-field permits the user to command a software reset to the SONET/SDH block. If the user invokes a software reset to the SONET/SDH blocks then all of the internal state machines will be reset to their default conditions; and each of the Receive STS-1/STS-3 TOH Processor blocks will undergo a re-frame operation. A "0" to "1" transition, within this bit-field commands this Software Reset. Note: This Software Reset does not reset the command registers to their default state. This can only be achieved by executing a "Hardware RESET" (e.g., by pulling the RESET_L* input pin "LOW"). This Software Reset does not affect the DS3/E3 Framer blocks. The Software Reset bit-field, for the DS3/E3 Framer block can be found in each of the 3 "DS3/E3 Operating Mode" registers (Address Location= 0xNF00). 48 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 6: Operation Status Register - Byte 3 (Address Location= 0x0104) BIT 7 R/O 1 BIT 6 R/O 1 BIT 5 R/O 1 BIT 4 R/O 0 BIT 3 Device ID Value R/O 0 R/O 0 R/O 1 R/O 1 BIT 2 BIT 1 BIT 0 BIT NUMBER 7-0 NAME Device ID Value TYPE R/O Device ID Value: DESCRIPTION This READ-ONLY bit-field is set to the value "0xE3" and permits the user's software code to uniquely identify this device as being the XRT94L33. Table 7: Operation Status Register - Byte 2 (Address Location= 0x0105) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 1 Revision Number Value BIT NUMBER 7-0 NAME Revision Number Value TYPE R/O Revision NumberValue: DESCRIPTION This READ-ONLY bit-field is set to the value that corresponds to its revision number. Revision A silicon will be set to the value "0x01". This register permits the user's software code to uniquely identify the revision number of this device. 49 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 8: Operation Interrupt Status Register - Byte 0 (Address Location= 0x010B) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 TB Parity Error Interrupt Status RUR/WTC 0 20 0 Rev2...0...0 200 BIT NUMBER Bit 7 - Bit 1 Bit 0 NAME Unused TB Parity Error Interrupt Status TYPE R/O RUR/ WTC DESCRIPTION Please set to "0" for normal operation Telecom Bus Parity Error Interrupt Status: This "RESET-upon-READ" bit-field indicates whether or not the "Detection of 155.52Mbps Telecom Bus - Parity Error" interrupt has occurred since the last read of this register bit. 0 - Indicates that the "Detection of 155.52Mbps Telecom Bus - Parity Error" interrupt has NOT occurred since the last read of this register bit. 1 - Indicates that the "Detection of 155.52Mbps Telecom Bus - Parity Error" interrupt has occurred since the last of this register bit. Note: This register bit is only active if the 155.52Mbps port is configured to operate via the Telecom Bus. Table 9: Operation Interrupt Enable Register - Byte 0 (Address Location= 0x010F) BIT 7 BIT 6 BIT 5 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 Telecom Bus Parity Error Interrupt Enable R/W 0 BIT NUMBER Bit 7 - Bit 1 Bit 0 NAME Unused TB Parity Error Interrupt Enable TYPE R/O R/W DESCRIPTION Please set to "0" for normal operation Telecom Bus Parity Error Interrupt Enable: This "READ/WRITE" bit-field permits the user to either enable or disable the "Detection of 155.52Mbps Telecom Bus - Parity Error" interrupt. 0 - Disables the "Detection of 155.52Mbps Telecom Bus - Parity Error" interrupt. 1 - Enables the "Detection of 155.52Mbps Telecom Bus - Parity Error" interrupt. Note: This register bit is only active if the 155.52Mbps port is configured to operate via the Telecom Bus. 50 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 10: Operation Block Interrupt Status Register - Byte 1 (Address Location= 0x0112) BIT 7 Op Control Block Interrupt Status R/O 0 BIT 6 DS3/E3 Mapper Block Interrupt Status R/O 0 BIT 5 Unused BIT 4 Rx STS-1 TOH Block Interrupt Status R/O 0 BIT 3 Rx STS-1 POH Block Interrupt Status R/O 0 BIT 2 DS3/E3 Framer Block Interrupt Status R/O 0 BIT 1 Rx Line Interface Block Interrupt Status R/O 0 BIT 0 Unused R/O 0 R/O 0 BIT NUMBER 7 NAME Op Control Block Interrupt Status TYPE R/O DESCRIPTION Operation Control Block Interrupt Status: This READ-ONLY bit-field indicates whether or not an Operation Control Block-related Interrupt is awaiting service. 0 - No Operation Control Block Interrupts are awaiting service. 1 - At least one "Operation Control Block" Interrupt is awaiting service. 6 DS3/E3 Mapper Block Interrupt Status R/O DS3/E3 Mapper Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a Mapper Blockrelated Interrupt is awaiting service. 0 - No Mapper Block interrupt is awaiting service. 1 - At least one "Mapper Block" Interrupt is awaiting service. 5 4 Unused Rx STS-1 TOH Block Interrupt Status R/O R/O STS-1 Receive Transport Overhead (TOH) Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not an "Receive STS-1 TOH Processor" Block Interrupt is awaiting service. 0 - No "Receive STS-1 TOH Processor" block interrupt is awaiting service. 1 - At least one "Receive STS-1 TOH Processor" block interrupt is awaiting service. Note: This bit-field is in-active if the XRT94L33 has been configured to operate in the SDH Mode. 3 Rx STS-1 POH Block Interrupt Status R/O Receive STS-1 Path Overhead (POH) Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not an "Receive STS-1 POH Processor" Block Interrupt is awaiting service. 0 - No "Receive STS-1 POH Processor" block interrupt is awaiting service. 1 - At least one "Receive STS-1 POH Processor" block interrupt is awaiting service. Note: This bit-field is in-active if the XRT94L33 has been configured to operate in the SDH Mode. 2 DS3/E3 Framer Block Interrupt Status R/O DS3/E3 Framer Block Interrupt Status This READ-ONLY bit-field indicates whether or not a "DS3/E3 Framer 51 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Block" interrupt is awaiting service. 0 - No "DS3/E3 Framer" block interrupt is awaiting service. 1 - At least one "DS3/E3 Framer" block interrupt is awaiting service. 1 Rx Line Interface Block Interrupt Status R/O Receive Line Interface Block Interrupt Status This READ-ONLY bit-field indicates whether or not a "Receive Line Interface Block" interrupt is awaiting service. 0 - No "Receive Line Interface" block interrupt is awaiting service. 1 - At least one "Receive Line Interface" block interrupt is awaiting service. 0 Unused R/O 20 0 Rev2...0...0 200 52 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 11: Operation Block Interrupt Status Register - Byte 0 (Address Location= 0x0113) BIT 7 Receive ATM Cell Processor Block Interrupt Status R/O 0 BIT 6 Receive STS-3/ STM-1 TOH Block Interrupt Status R/O 0 BIT 5 Receive SONET/ VC-3 POH Block Interrupt Status R/O 0 BIT 4 Receive PPP Processor Block Interrupt Status R/O 0 BIT 3 Transmit ATM Cell Processor Block Interrupt Status R/O 0 R/O 0 BIT 2 Unused BIT 1 BIT 0 Transmit PPP Processor Block Interrupt Status R/O 0 R/O 0 BIT NUMBER 7 NAME Receive ATM Cell Processor Block Interrupt Status TYPE R/O DESCRIPTION Receive ATM Cell Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "Receive ATM Cell Processor Block" interrupt is awaiting service. 0 - No "Receive ATM Cell Processor Block" Interrupt is awaiting service. 1 - At least one "Receive ATM Cell Processor Block" interrupt is awaiting service. 6 Receive STS-3/ STM-1 TOH Block Interrupt Status R/O Receive STS-3/STM-1 TOH Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "Receive STS3/STM-1 TOH Processor Block" interrupt is awaiting service. 0 - No "Receive STS-3/STM-1 TOH Processor Block" Interrupt is awaiting service. 1 - At least one "Receive STS-3/STM-1 TOH Processor Block" interrupt is awaiting service. 5 Receive SONET/ VC-3 POH Block Interrupt Status R/O Receive SONET/VC-3 POH Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "Receive SONET/VC-3 POH Processor Block" interrupt is awaiting service. 0 - No "Receive SONET/VC-3 POH Processor Block" Interrupt is awaiting service. 1 - At least one "Receive SONET/VC-3 POH Processor Block" Interrupt is awaiting service. 4 Receive PPP Processor Block Interrupt Status R/O Receive PPP Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "Receive PPP Processor Block" interrupt is awaiting service. 0 - No "Receive PPP Processor Block" Interrupt is awaiting service. 1 - At least one "Receive PPP Processor Block" interrupt is awaiting service. 3 Transmit ATM Cell Processor Block Interrupt Status R/O Transmit ATM Cell Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "Transmit ATM Cell Processor Block" interrupt is awaiting service. 0 - No "Transmit ATM Cell Processor Block" Interrupt is awaiting service. 1 - At least one "Transmit ATM Cell Processor Block" interrupt is awaiting service. 53 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 2-1 0 Unused Transmit PPP Processor Block Interrupt Status R/O R/O Transmit PPP Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "Transmit PPP Processor Block" interrupt is awaiting service. 0 - No "Transmit PPP Processor Block" Interrupt is awaiting service. 1 - At least one "Transmit PPP Processor Block" Interrupt is awaiting service. 20 0 Rev2...0...0 200 54 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 12: Operation Block Interrupt Enable Register - Byte 1 (Address Location= 0x0116) BIT 7 Op Control Block Interrupt Enable R/W 0 BIT 6 DS3/E3 Mapper Block Interrupt Enable R/W 0 BIT 5 Unused BIT 4 Rx STS-1 TOH Block Interrupt Enable R/W 0 BIT 3 Rx STS-1 POH Block Interrupt Enable R/W 0 BIT 2 DS3/E3 Framer Block Interrupt Enable R/W 0 BIT 1 Rx Line Interface Block Interrupt Enable R/W 0 BIT 0 Unused R/O 0 R/O 0 BIT NUMBER 7 NAME Op Control Block Interrupt Enable TYPE R/W DESCRIPTION Operation Control Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the Operation Control Block for interrupt generation. If the user writes a "0" to this register bit and disables the "Operation Control Block" (for interrupt generation), then all "Operation Control Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Operation Control Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Operation Control Block" interrupts within the device. 1 - Enables the "Operation Control Block" at the "Block-Level" for interrupt generation 6 DS3/E3 Mapper Block Interrupt Enable R/W DS3/E3 Mapper Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Mapper Block for interrupt generation. If the user writes a "0" to this register bit and disables the "Mapper Block" (for interrupt generation), then all "Mapper Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Mapper Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Mapper Block" interrupts within the device. 1 - Enables the "Mapper Block" at the "Block-Level" 5 4 Unused Rx STS-1 TOH Block Interrupt Enable R/O R/W Receive STS-1 TOH (Transport Overhead) Processor Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Receive STS-1 TOH Processor Block for interrupt generation. If the user writes a "0" to this register bit and disables the "Receive STS-1 TOH Processor Block" (for interrupt generation), then all "Receive STS-1 TOH Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive STS-1 TOH Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Receive STS-1 TOH Processor Block" interrupts within the device. 1 - Enables the "Receive STS-1 TOH Processor Block" at the "Block-Level". Note: This bit-field is inactive if the XRT94L33 has been configured to operate in the SDH Mode. 3 Rx STS-1 POH Block Interrupt Enable R/W Receive STS-1 POH (Path Overhead) Processor Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Receive 55 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Enable 20 0 Rev2...0...0 200 STS-1 POH Processor Block for interrupt generation. If the user writes a "0" to this register bit and disables the "Receive STS-1 POH Processor Block" (for interrupt generation), then all "Receive STS-1 POH Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive STS-1 POH Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Receive STS-1 POH Processor Block" interrupts within the device. 1 - Enables the "Receive STS-1 POH Processor Block" at the "Block-Level". Note: This bit-field is inactive if the XRT94L33 has been configured to operate in the SDH Mode. 2 DS3/E3 Framer Block Interrupt Enable R/W DS3/E3 Framer Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the DS3/E3 Framer Block for interrupt generation. If the user writes a "0" to this register bit and disables the "DS3/E3 Framer Block" (for interrupt generation), then all "DS3/E3 Framer Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "DS3/E3 Framer Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "DS3/E3 Framer Block" interrupts within the device. 1 - Enables the "DS3/E3 Framer Block" at the "Block-Level". 1 Rx Line Interface Block Interrupt Enable R/W Receive Line Interface Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Receive Line Interface Block for interrupt generation. If the user writes a "0" to this register bit and disables the "Receive Line Interface Block" (for interrupt generation), then all "Receive Line Interface Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive Line Interface Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Receive Line Interface Block" interrupts within the device. 1 - Enables the "Receive Line Interface Block" at the "Block-Level". 0 Unused R/O 56 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 13: Operation Block Interrupt Enable Register - Byte 0 (Address Location= 0x0117) BIT 7 Receive ATM Cell Processor Block Interrupt Enable R/W 0 BIT 6 Receive STS-3/ STM-1 TOH Block Interrupt Enable R/W 0 BIT 5 Receive SONET/ VC-3 POH Block Interrupt Enable R/W 0 BIT 4 Receive PPP Processor Block Interrupt Enable R/W 0 BIT 3 Transmit ATM Cell Processor Block Interrupt Enable R/W 0 R/O 0 BIT 2 Unused BIT 1 BIT 0 Transmit PPP Processor Block Interrupt Enable R/O 0 R/W 0 BIT NUMBER 7 NAME Receive ATM Cell Processor Block Interrupt Enable TYPE R/W DESCRIPTION Receive ATM Cell Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive ATM Cell Processor Block" for interrupt generation. If the user writes a "0" to this register bit and disables the "Receive ATM Cell Processor Block" (for interrupt generation), then all "Receive ATM Cell Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive ATM Cell Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disables all "Receive ATM Cell Processor Block" interrupts within the device. 1 - Enables the "Receive ATM Cell Processor Block at the "Block Level" for interrupt generation. 6 Receive STS-3/STM-1 TOH Block Interrupt Enable R/W Receive STS-3/STM-1 TOH Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive STS-3/STM-1 TOH Processor Block" for interrupt generation. If the user writes a "0" to this register bit and disables the "Receive STS-3/STM-1 TOH Processor Block" (for interrupt generation), then all "Receive STS-3/STM-1 TOH Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive STS-3/STM-1 TOH Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disables all "Receive STS-3/STM-1 TOH Processor Block" interrupts within the device. 1 - Enables the "Receive STS-3/STM-1 TOH Processor Block" at the "Block Level" for interrupt generation. 5 Receive SONET/ VC-3 POH Block Interrupt Enable R/W Receive SONET/VC-3 POH Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive SONET/VC-3 POH Processor Block" for interrupt generation. If the user writes a "0" into this register bit and disables the "Receive SONET/VC-3 POH Processor Block" (for interrupt generation), then all "Receive SONET/VC-3 Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, then he/she will still need to enable the individual "Receive SONET/VC-3 POH Processor Block" Interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disables all "Receive SONET/VC-3 POH Processor Block" Interrupts 57 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS within the device. 1 - Enables the "Receive SONET/VC-3 POH Processor Block" at the "Block Level" for interrupt generation. 4 Receive PPP Processor Block Interrupt Enable R/W Receive PPP Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive PPP Processor Block" for interrupt generation. If the user writes a "0" to this register bit and disables the "Receive PPP Processor Block" (for interrupt generation), then all "Receive PPP Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive PPP Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disables all "Receive PPP Processor Block" interrupts within the device. 1 - Enables the "Receive PPP Processor Block" at the "Block Level" for interrupt generation. 3 Transmit ATM Cell Processor Block Interrupt Enable R/W Transmit ATM Cell Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit ATM Cell Processor Block" for interrupt generation. If the user writes a "0" to this register bit and disables the "Transmit ATM Cell Processor Block" (for interrupt generation), then all "Transmit ATM Cell Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Transmit ATM Cell Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disables all "Transmit ATM Cell Processor Block" interrupts within the device. 1 - Enables the "Transmit ATM Cell Processor Block" at the "Block Level" for interrupt generation. 2 -1 0 Unused Transmit PPP Processor Block Interrupt Enable R/O R/W Transmit PPP Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit PPP Processor Block" for interrupt generation. If the user writes a "0" to this register bit and disables the "Transmit PPP Processor Block" (for interrupt generation), then all "Transmit PPP Processor Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Transmit PPP Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disables all "Transmit PPP Processor Block" interrupts within the device. 1 - Enables the "Transmit PPP Processor Block" at the "Block Level" for interrupt generation. 20 0 Rev2...0...0 200 58 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 14: Mode Control Register - Byte 0 (Address Location= 0x011B) BIT 7 Disable Jitter Attenuator Fast Lock R/W 0 BIT 6 TBUS0_IS _SDH R/W 0 BIT 5 V1_PULS E_EN R/W 0 BIT 4 TBUS0_ MASTER R/W 0 R/O 0 BIT 3 BIT 2 Reserved BIT 1 BIT 0 AU-3/TUG-3* Mapping Select R/O 0 R/W 0 R/O 0 BIT NUMBER 7 NAME DISFASTLOCK TYPE R/W DESCRIPTION Disable Jitter Attenuator Fast lock: This READ/WRITE bit field is used to disable the fast lock feature for the Jitter Attenuator block 0 - Fast Lock feature is enabled 1 - Fast Lock feature is disabled Note: To configure the XRT94L33 such that it will comply with the Telcordia GR-253-CORE APS Recovery time requirements of 50ms, then the "Fast Lock" feaure MUST be enabled within the Jitter Attenuator block, by setting this bit-field to "0" 6 TBUS0_IS_SDH R/W Telecom Bus 0 operating in SDH Mode This bit is used to qualify and process a Highrate SDH signal for Subrate Telecom Bus 0 operation. 0- Clearing this bit will disable SDH format signal validation on Telecom Bus 0. Subrate Telecom Bus 0 RxD[7:0] data bus ouput will be disabled. 1 - Setting this bit will enable SDH format signal validation on Telecom Bus 0. It enables RxD[7:0] data bus output upon reception of a valid SDH signal format structure. Note: This bit must be enabled in SDH mode for Subrate Telecom Bus 0 operation. This bit is ignored and does not apply in SONET mode of operation. 5 V1_PULSE_EN R/W V1 Pulse Enable This bit provides the option of using an additional pulse on the Telecom Drop Bus RxD_C1J1 output pin and Telecom Add Bus TxA_C1J1 pin to denote the location or onset of V1 Byte within the Synchronous Payload Envelope/Virtual Container of the SONET/SDH frame whenever the Telecom Bus is processing the Virtual Tributary Group/Virtual Container multi-frame boundary 0 - Telecom Bus 0 in STS-3/STM-1 mode will not indicate a V1 pulse on RxD_CIJ1V1 output pin and TxA_C1J1V1 pin to indicate VT/VC multi-frame boundary. 1 - Telecom Bus 0 in STS-3/STM-1 mode has V1 pulse added on RxD_CIJ1V1 output pin and TxA_C1J1V1 pin to indicate VT/VC multi-frame boundary 4 TBUS0_MASTER R/W Select Phase Timing Reference This bit selects TxA_C1J1V1 and TxA_PL phase timing reference when operating the Subrate Add Telecom Bus 0 in Rephase OFF mode. 0 - Add Telecom Bus 0 timing in Slave Mode. TxA_C1J1V1 and TxA_PL pins are inputs. 59 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 1 - Add Telecom Bus 0 timing in Master Mode. TxA_C1J1V1 and TxA_PL pins are outputs. 3-1 0 Unused AU-3/TUG-3* R/O R/W Reserved AU-3/TUG-3 Mapping Select: This READ/WRITE bit-field is used to to specify how the DS3/E3 data, associated with Channels 0, 1 and 2 are mapped into an SDH signal, as indicated below. 0 - DS3/E3 Channels are mapped into a VC-3, a TU-3, and then finally a TUG-3 structure, when being mapped into an STM-1 signal. 1 - DS3/E3 Channels are mapped into a VC-3 and then an AU-3 when being mapped into an STM-1 signal. Note: This register bit is only active if the XRT94L33 has been configured to operate in the SDH Mode. 60 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 15: Loop-back Control Register - Byte 0 (Address Location= 0x011F) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Loop-back[3:0] R/W 0 R/W 0 BIT 0 BIT NUMBER 7-4 3-0 NAME Unused Loop-back[3:0] TYPE R/O R/W Loop-back Mode[3:0] DESCRIPTION These four READ/WRITE bits-fields permit the user to configure the XRT94L33 to operate in a variety of loop-back modes, as is tabulated below. Loop-back[3:0] 0000 0001 Resulting Loop-back Mode Normal Mode (e.g., No Loop-back Mode) Remote Line Loop-back: In this mode, all data that is received by the "Receive STS-3/STM-1 PECL Interface" block will be routed to the "Transmit STS-3/STM-1 PECL Interface" block. Note: If the user invokes this loop-back, then he/she must configure the Transmit STS-3/STM-1 PECL Interface to operate in the Loop-timing mode by setting Bit 6 within the Receive Line Interface Control Register - Byte 1, to "1" (Address Location: 0x0302). 0010 Local Transport Loop-back: In this mode, all data that is being output via the "Transmit STS-3 TOH Processor" block will also be routed to the "Receive STS-3 TOH Processor" block. 0011 Local Path Loop-back: In this mode, all data that is output by the Transmit SONET POH Processor block (e.g., towards the "Transmit STS-3 TOH Processor" block) will be routed to the "Receive SONET POH Processor" block. Note: This mode effect all 3 Transmit SONET POH Processor and Receive SONET POH Processor blocks. 0100 - 1111 Reserved - Do Not Use 61 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 16: Channel Interrupt Indicator - Receive SONET POH Processor Block (Address Location= 0x0120) BIT 7 BIT 6 Unused BIT 5 BIT 4 Rx STS-3c POH Processor Block Interrupt R/O 0 R/O 0 BIT 3 Rx SDH POH Block Interrupt BIT 2 Rx SONET POH Block Interrupt Ch 2 R/O 0 BIT 1 Rx SONET POH Block Interrupt Ch 1 R/O 0 BIT 0 Rx SONET POH Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused Rx STS-3c POH Block Interrupt TYPE DESCRIPTION R/O Receive STS-3c POH Processor Block Interrupt: This READ/ONLY bit-field indicates whether or not the "Receive STS-3c POH Processor" block, associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Receive STS-3c POH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Receive STS-3c POH Processor block, associated with Channel 0 is currently declaring an Interrupt. Note: This register bit is only active if the XRT94L33 has been configured to support an STS-3c signal via Channel 0. 3 Rx SDH POH Block Interrupt R/O Receive SDH POH Processor Block Interrupt: This READ/ONLY bit-field indicates whether or not the "Receive SDH POH Processor" block, associated with Channel 3 is declaring an Interrupt, as described below. 0 - The Receive SDH POH Processor block, associated with Channel 3 is NOT declaring an Interrupt. 1 - The Receive SDH POH Processor block, associated with Channel 3 is currently declaring an interrupt. 2 Rx SONET POH Block Interrupt Channel 2 R/O Receive SONET POH Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Receive SONET POH Processor" block, associated with Channel 2 is declaring an Interrupt, as described below. 0 - The Receive SONET POH Processor block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The Receive SONET POH Processor block, associated with Channel 2 is currently declaring an interrupt. 1 Rx SONET POH Block Interrupt Channel 1 R/O Receive SONET POH Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Receive SONET POH Processor" block, associated with Channel 1 is declaring an Interrupt, as described below. 0 - The Receive SONET POH Processor block, associated with Channel 9 is NOT declaring an Interrupt. 1 - The Receive SONET POH Processor block, associated with Channel 9 is currently declaring an interrupt. 62 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Rx SONET POH Block Interrupt Channel 0 R/O Receive SONET POH Processor Block Interrupt : This READ/ONLY bit-field indicates whether or not the "Receive SONET POH Processor" block, associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Receive SONET POH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Receive SONET POH Processor block, associated with Channel 0 is currently declaring an interrupt. 0 63 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 17: Channel Interrupt Indicator - DS3/E3 Framer Block (Address Location= 0x0122) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 DS3/E3 Framer Block Interrupt Ch 2 R/O 0 BIT 1 DS3/E3 Framer Block Interrupt Ch 1 R/O 0 BIT 0 DS3/E3 Framer Block Interrupt Ch 0 R/O 0 20 0 Rev2...0...0 200 BIT NUMBER 7 -3 2 NAME Unused DS3/E3 Framer Block Interrupt Ch 2 TYPE R/O R/O DESCRIPTION DS3/E3 Framer Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "DS3/E3 Framer" block, associated with Channel 2 is declaring an Interrupt, as described below. 0 - The DS3/E3 Framer block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The DS3/E3 Framer block, associated with Channel 2 is currently declaring an interrupt. 1 DS3/E3 Framer Block Interrupt Ch 1 R/O DS3/E3 Framer Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "DS3/E3 Framer" block, associated with Channel 1 is declaring an Interrupt, as described below. 0 - The DS3/E3 Framer block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The DS3/E3 Framer block, associated with Channel 1 is currently declaring an interrupt. 0 DS3/E3 Framer Block Interrupt Ch 0 R/O DS3/E3 Framer Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "DS3/E3 Framer" block, associated with Channel 0 is declaring an Interrupt, as described below. 0 - The DS3/E3 Framer block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The DS3/E3 Framer block, associated with Channel 0 is currently declaring an interrupt. 64 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 18: Channel Interrupt Indicator - Receive STS-1 POH Processor Block (Address Location= 0x0123) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Rx STS-1 POH Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 Rx STS-1 POH Block Interrupt Ch 1 R/O 0 BIT 0 Rx STS-1 POH Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused Rx STS-1 POH Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION Receive STS-1 POH Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Receive STS-1 POH Processor" block, associated with Channel 2 is declaring an Interrupt, as described below. 0 - The Receive STS-1 POH Processor block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The Receive STS-1 POH Processor block, associated with Channel 2 is currently declaring an interrupt. 1 Rx STS-1 POH Block Interrupt Channel 1 R/O Receive STS-1 POH Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Receive STS-1 POH Processor" block, associated with Channel 1 is declaring an Interrupt, as described below. 0 - The Receive STS-1 POH Processor block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The Receive STS-1 POH Processor block, associated with Channel 1 is currently declaring an interrupt. 0 Rx STS-1 POH Block Interrupt Channel 0 R/O Receive STS-1 POH Processor Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "Receive STS-1 POH Processor" block, associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Receive STS-1 POH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Receive STS-1 POH Processor block, associated with Channel 0 is currently declaring an interrupt. 65 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 19: Channel Interrupt Indicator - Receive STS-1 TOH Processor Block (Address Location= 0x0124) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Rx STS-1 TOH Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 Rx STS-1 TOH Block Interrupt Ch 1 R/O 0 BIT 0 Rx STS-1 TOH Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused Rx STS-1 TOH Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION Receive STS-1 TOH Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Receive STS-1 TOH Processor" block, associated with Channel 2 is declaring an Interrupt, as described below. 0 - The Receive STS-1 TOH Processor block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The Receive STS-1 TOH Processor block, associated with Channel 2 is currently declaring an interrupt. 1 Rx STS-1 TOH Block Interrupt Channel 1 R/O Receive STS-1 TOH Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Receive STS-1 TOH Processor" block, associated with Channel 1 is declaring an Interrupt, as described below. 0 - The Receive STS-1 TOH Processor block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The Receive STS-1 TOH Processor block, associated with Channel 1 is currently declaring an interrupt. 0 Rx STS-1 TOH Block Interrupt Channel 0 R/O Receive STS-1 TOH Processor Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "Receive STS-1 TOH Processor" block, associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Receive STS-1 TOH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Receive STS-1 TOH Processor block, associated with Channel 0 is currently declaring an interrupt. 66 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 20: Channel Interrupt Indicator -DS3/E3 Mapper Block (Address Location= 0x0126) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 DS3/E3 Mapper Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 DS3/E3 Mapper Block Interrupt Ch 1 R/O 0 BIT 0 DS3/E3 Mapper Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused DS3/E3 Mapper Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION DS3/E3 Mapper Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "DS3/E3 Mapper" block, associated with Channel 2 is declaring an Interrupt, as described below. 0 - The DS3/E3 Mapper block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The DS3/E3 Mapper block, associated with Channel 2 is currently declaring an interrupt. 1 DS3/E3 Mapper Block Interrupt Channel 1 R/O DS3/E3 Mapper Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "DS3/E3 Mapper" block, associated with Channel 1 is declaring an Interrupt, as described below. 0 - The DS3/E3 Mapper block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The DS3/E3 Mapper block, associated with Channel 1 is currently declaring an interrupt. 0 DS3/E3 Mapper Block Interrupt Channel 0 R/O DS3/E3 Mapper Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "DS3/E3 Mapper" block, associated with Channel 0 is declaring an Interrupt, as described below. 0 - The DS3/E3 Mapper block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The DS3/E3 Mapper block, associated with Channel 0 is currently declaring an interrupt. 67 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 21: Channel Interrupt Indicator -Transmit ATM Cell Processor Block (Address Location= 0x0127) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Transmit ATM Cell Processor Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 Transmit ATM Cell Processor Block Interrupt Ch 1 R/O 0 BIT 0 Transmit ATM Cell Processor Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused Transmit ATM Cell Processor Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION Transmit ATM Cell Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Transmit ATM Cell Processor Block", associated with Channel 2 is declaring an Interrupt, as described below. 0 - The transmit ATM Cell Processor Block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The transmit ATM Cell Processor Block, associated with Channel 2 is currently declaring an interrupt. 1 Transmit ATM Cell Processor Block Interrupt Channel 1 R/O Transmit ATM Cell Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Transmit ATM Cell Processor Block", associated with Channel 1 is declaring an Interrupt, as described below. 0 - The transmit ATM Cell Processor Block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The transmit ATM Cell Processor Block, associated with Channel 1 is currently declaring an interrupt. 0 Transmit ATM Cell Processor Block Interrupt Channel 0 R/O Transmit ATM Cell Processor Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "Transmit ATM Cell Processor Block" associated with Channel 0 is declaring an Interrupt, as described below. 0 - The transmit ATM Cell Processor Block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The transmit ATM Cell Processor Block, associated with Channel 0 is currently declaring an interrupt. 68 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 22: Channel Interrupt Indicator -Receive ATM Cell Processor Block (Address Location= 0x0128) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Receive ATM Cell Processor Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 Receive ATM Cell Processor Block Interrupt Ch 1 R/O 0 BIT 0 Receive ATM Cell Processor Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused Receive ATM Cell Processor Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION Receive ATM Cell Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Receive ATM Cell Processor Block", associated with Channel 2 is declaring an Interrupt, as described below. 0 - The Receive ATM Cell Processor Block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The Receive ATM Cell Processor Block, associated with Channel 2 is currently declaring an interrupt. 1 Receive ATM Cell Processor Block Interrupt Channel 1 R/O Receive ATM Cell Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Receive ATM Cell Processor Block", associated with Channel 1 is declaring an Interrupt, as described below. 0 - The Receive ATM Cell Processor Block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The Receive ATM Cell Processor Block, associated with Channel 1 is currently declaring an interrupt. 0 Receive ATM Cell Processor Block Interrupt Channel 0 R/O Receive ATM Cell Processor Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "Receive ATM Cell Processor Block" associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Receive ATM Cell Processor Block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Receive ATM Cell Processor Block, associated with Channel 0 is currently declaring an interrupt. 69 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 23: Channel Interrupt Indicator -Transmit PPP Processor Block (Address Location= 0x0129) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Transmit PPP Processor Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 Transmit PPP Processor Block Interrupt Ch 1 R/O 0 BIT 0 Transmit PPP Processor Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused Transmit PPP Processor Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION Transmit PPP Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Transmit PPP Processor Block", associated with Channel 2 is declaring an Interrupt, as described below. 0 - The Transmit PPP Processor Block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The Transmit PPP Processor Block, associated with Channel 2 is currently declaring an interrupt. 1 Transmit PPP Processor Block Interrupt Channel 1 R/O Transmit PPP Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Transmit PPP Processor Block", associated with Channel 1 is declaring an Interrupt, as described below. 0 - The Transmit PPP Processor Block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The Transmit PPP Processor Block, associated with Channel 1 is currently declaring an interrupt. 0 Transmit PPP Processor Block Interrupt Channel 0 R/O Transmit PPP Processor Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "Transmit PPP Processor Block" associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Transmit PPP Processor Block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Transmit PPP Processor Block, associated with Channel 0 is currently declaring an interrupt. 70 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 24: Channel Interrupt Indicator -Receive PPP Processor Block (Address Location= 0x012A) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Receive PPP Processor Block Interrupt Ch 2 R/O 0 R/O 0 R/O 0 BIT 1 Receive PPP Processor Block Interrupt Ch 1 R/O 0 BIT 0 Receive PPP Processor Block Interrupt Ch 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused Receive PPP Processor Block Interrupt Channel 2 TYPE R/O R/O DESCRIPTION Receive PPP Processor Block Interrupt - Channel 2: This READ/ONLY bit-field indicates whether or not the "Receive PPP Processor Block", associated with Channel 2 is declaring an Interrupt, as described below. 0 - The Receive PPP Processor Block, associated with Channel 2 is NOT declaring an Interrupt. 1 - The Receive PPP Processor Block, associated with Channel 2 is currently declaring an interrupt. 1 Receive PPP Processor Block Interrupt Channel 1 R/O Receive PPP Processor Block Interrupt - Channel 1: This READ/ONLY bit-field indicates whether or not the "Receive PPP Processor Block", associated with Channel 1 is declaring an Interrupt, as described below. 0 - The Receive PPP Processor Block, associated with Channel 1 is NOT declaring an Interrupt. 1 - The Receive PPP Processor Block, associated with Channel 1 is currently declaring an interrupt. 0 Receive PPP Processor Block Interrupt Channel 0 R/O Receive PPP Processor Block Interrupt - Channel 0: This READ/ONLY bit-field indicates whether or not the "Receive PPP Processor Block" associated with Channel 0 is declaring an Interrupt, as described below. 0 - The Receive PPP Processor Block, associated with Channel 0 is NOT declaring an Interrupt. 1 - The Receive PPP Processor Block, associated with Channel 0 is currently declaring an interrupt. 71 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 25: Interface Control Register - Byte 1 (Address Location= 0x0132) BIT 7 Unused R/O 0 R/O 0 BIT 6 BIT 5 BIT 4 BIT 3 Unused R/O 0 R/O 0 BIT 2 BIT 1 BIT 0 20 0 Rev2...0...0 200 Receive STS-3/STM-1 Line Select[1:0] R/W 0 R/W 0 Transmit STS-3/STM-1 Line Select[1:0] R/W 0 R/W 0 BIT NUMBER 7-6 5-4 NAME Unused Receive STS3/STM-1 Line Select[1:0] TYPE R/O R/W DESCRIPTION Receive STS-3/STM-1 Line Select[1:0]: These two READ/WRITE bit-fields permit the user to configure the Receive STS-3 TOH Processor block to either accept its STS-3/STM-1 data from the Receive STS-3/STM-1 Telecom Bus Interface, or from the Receive STS-3/STM-1 PECL Interface. 0, 0 - Configures the Receive STS-3 TOH Processor block to accept the incoming STS-3/STM-1 data via the Receive STS-3/STM-1 PECL Interface block 0, 1 - Configures the Receive STS-3 TOH Processor block to accept the incoming STS-3/STM-1 data via the Receive STS-3/STM-1 Telecom Bus Interface block 1, 0 and 1, 1 - Do not use. 3-2 1-0 Unused Transmit STS3/STM-1 Line Select[1:0] R/O R/W Transmit STS-3/STM-1 Line Select[1:0]: These two READ/WRITE bit-fields permit the user to configure the Transmit STS-3 TOH Processor block to output its outbound STS-3/STM1 data to either the Transmit STS-3/STM-1 Telecom Bus Interface, or to the Transmit STS-3/STM-1 PECL Interface. 0, 0 - Configures the Transmit STS-3 TOH Processor block to output the outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 PECL Interface block 0, 1 - Configures the Transmit STS-3 TOH Processor block to output the outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 Telecom Bus Interface block 1, 0 and 1, 1 - Do not use. 72 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 26: Interface Control Register - Byte 0 (Address Location= 0x0133) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SBSYNC_Delay[7:0] BIT NUMBER 7-0 NAME SBSYNC_Delay[7:0] TYPE R/W DESCRIPTION STS-1 Telecom Bus - Sync Delay: The Transmit STS-1 Telecom Bus is aligned to the "TxSBFP_in" input pin. The user is expected to apply a pulse (with the period of a 6.48MHz clock signal) at a rate of 8kHz to the "TxSBFP_in input (pin number G4). Each Transmit STS-1 Telecom Bus will align its transmission of the very first byte of a new STS-1 frame, with a pulse at this input pin. These READ/WRITE bit-fields permit the user to specify the amount of delay (in terms of 6.48MHz clock periods) that will exist between the rising edge of "TxSBFP_in" and the transmission of the very first byte, within a given STS-1 via the Transmit STS-1 Telecom Bus. Setting this register to "0x00" configures each of the Transmit STS-1 Telecom Bus Interfaces to transmit the very first byte of a new STS-1 frame, upon detection of the rising edge of the "TxSBFP_in". Setting this register to "0x01" configures each of the Transmit STS-1 Telecom Bus Interfaces to delay its transmission of the very first byte of a new STS-1 frame, by one 6.48MHz clock period, and so on. Note: This register is only active if at least one of the three STS-1 Telecom Bus Interfaces are enabled. 73 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 27: STS-3/STM-1 Telecom Bus Control Register - Byte 3 (Address Location= 0x0134) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 HRSYNC_Delay[15:8] BIT NUMBER 7-0 NAME HRSYNC_Delay[15:8] TYPE R/W DESCRIPTION STS-3 Telecom Bus - Sync Delay - Upper Byte: The Transmit STS-3 Telecom Bus is aligned to the "TxSBFP_in" input pin. The user is expected to apply a pulse (with the period of a 6.48MHz clock signal) at a rate of 8kHz to the "TxSBFP_in input (pin number G4). The Transmit STS-3/STM-1 Telecom Bus will align its transmission of the very first byte of a new STS-3/STM-1 frame, with a pulse at this input pin. These READ/WRITE bit-fields permit the user to specify the amount of delay (in terms of 19.44MHz clock periods) that will exist between the rising edge of "TxSBFP_in" and the transmission of the very first byte, within a given STS-3 via the Transmit STS-3/STM-1 Telecom Bus. Setting these two registers to "0x0000" configures each of the Transmit STS-3/STM-1 Telecom Bus Interfaces to transmit the very first byte of a new STS-3 frame, upon detection of the rising edge of the "TxSBFP_in". Setting these register to "0x0001" configures each of the Transmit STS3 Telecom Bus Interfaces to delay its transmission of the very first byte of a new STS-3 frame, by one 19.44MHz clock period, and so on. Note: This register is only active if the STS-3/STM-1 Telecom Bus Interfaces is enabled. 74 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 28: STS-3/STM-1 Telecom Bus Control Register - Byte 2 (Address Location= 0x0135) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 HRSYNC_Delay[7:0] BIT NUMBER 7-0 NAME HRSYNC_Delay[7:0] TYPE R/W DESCRIPTION STS-3 Telecom Bus - Sync Delay - Lower Byte: The Transmit STS-3 Telecom Bus is aligned to the "TxSBFP_in" input pin. The user is expected to apply a pulse (with the period of a 6.48MHz clock signal) at a rate of 8kHz to the "TxSBFP_in input (pin number G4). The Transmit STS-3/STM-1 Telecom Bus will align its transmission of the very first byte of a new STS-3/STM-1 frame, with a pulse at this input pin. These READ/WRITE bit-fields (along with that within the "Interface Control Register - Byte 3) permit the user to specify the amount of delay (in terms of 19.44MHz clock periods) that will exist between the rising edge of "TxSBFP_in" and the transmission of the very first byte, within a given STS-3 via the Transmit STS-3/STM-1 Telecom Bus. Setting this register to "0x0000" configures each of the Transmit STS3/STM-1 Telecom Bus Interfaces to transmit the very first byte of a new STS-3 frame, upon detection of the rising edge of the "TxSBFP_in". Setting this register to "0x0001" configures each of the Transmit STS-3 Telecom Bus Interfaces to delay its transmission of the very first byte of a new STS-3 frame, by one 19.44MHz clock period, and so on. Note: This register is only active if the STS-3/STM-1 Telecom Bus Interfaces is enabled. 75 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 29: STS-3/STM-1 Telecom Bus Control Register - Byte 0 (Address Location= 0x0137) BIT 7 Telecom Bus ON R/W 0 BIT 6 Telecom Bus Disable R/W 0 BIT 5 Is STS-3 Payload R/W 0 BIT 4 Telecom Bus Parity Type R/W 0 BIT 3 Telecom Bus J1 Only R/W 0 BIT 2 Telecom Bus Parity Odd R/W 0 BIT 1 Telecom Bus Parity Disable R/W 0 BIT 0 STS-3 Rephase OFF R/W 0 20 0 Rev2...0...0 200 BIT NUMBER Bit 7 NAME Telecom Bus ON TYPE R/W Telecom Bus Enable: DESCRIPTION This READ/WRITE permits the user to either enable or disable the 155.52Mbps Telecom Bus Interface. 0 - Telecom Bus Interface is Disabled: STS-3/STM-1 data will "Clock/Data" Interface. output via "Interleave/De-Interleave" or 1 - Telecom Bus Interface is Enabled: In this selection, the STS-3/STM-1 Transmit and Receive Telecom Bus Interface will be enabled. Bit 6 Telecom Bus TriState R/W Telecom Bus Tri-state: This READ/WRITE bit-field permits the user to "tri-state" the Telecom Bus Interface. 0 - Telecom Bus Interface is NOT tri-stated. 1 - Telecom Bus Interface is tri-stated. Note: Bit 5 Is STS-3 Payload R/W This READ/WRITE bit-field is ignored if the STS-3/STM-1 Transmit and Receive Telecom Bus Interface is disabled. Is STS-3 Payload: This READ/WRITE bit-field permits the user to enable Telecom bus 0 to handle complete STS-3 payload 0 - All three buses are enabled 1 - Telecom Bus 0 is enabled to handle complete STS-3 payload, the other two buses are not used. Bit 4 Telecom Bus Parity Type R/W Telecom Bus Parity Type: This READ/WRITE bit-field permits the user to define the parameters, over which "Telecom Bus" parity will be computed. 0 - Parity is computed/verified over the STS-3/STM-1 Transmit and Receive Telecom Bus - data bus pins (e.g., TXA_D[7:0] and RXD_D[7:0]). If the user implements this selection, then the following will happen. a. The STS-3/STM-1 Transmit Telecom Bus Interface will compute and output parity (via the "TXA_DP" output pin) based upon and coincident with the data being output via the "TXA_D[7:0]" output pins. The STS-3/STM-1 Receive Telecom Bus Interface will compute and verify the parity data (which is input via the "RXD_DP" input pin) based upon the data which is being input (and latched) via b. 76 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS the "RXD_D[7:0]" input pins. 1 - Parity is computed/verified over the STS-3/STM-1 Transmit and Receive Telecom Bus - data bus pins (e.g., TXA_D[7:0] and RXD_D[7:0]); the C1J1 and PL input/output pins. If the user implements this selection, then the following will happen. a. The STS-3/STM-1 Transmit Telecom Bus Interface will compute and output parity (via the "TXA_DP" output) based upon and coincident with (1) the data being output via the "TXA_D[7:0]" output pins, (2) the state of the "TXA_PL" output pin, and (3) the state of the "TXA_C1J1" output pin. The STS-3/STM-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "RXD_DP" input pin) based upon (1) the data which is being input (and latched) via the "RXD_D[7:0]" input pins, (2) the state of the "RXD_PL" input pin, and (3) the state of the "RXD_C1J1" input pin. This bit-field is disabled if the STS-3/STM-1 Telecom Bus is disabled. The user can configure the STS-3/STM-1 Telecom Bus to compute with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity - Odd), within this register. b. Note: Bit 3 Telecom Bus J1 Only R/W Telecom Bus - J1 Indicator Only: This READ/WRITE bit-field permits the user to configure how the STS3/STM-1 Transmit and Receive Telecom Bus interface handles the "TXA_C1J1" and RXD_C1J1" signals, as described below. 0 - C1 and J1 Bytes This selection configures the following. c. The STS-3/STM-1 Transmit Telecom Bus to pulse the "TXA_C1J1" output coincident to whenever the C1 and J1 bytes are being output via the "TXA_D[7:0]" output pins. The STS-3/STM-1 Receive Telecom Bus will expect the "RXD_C1J1" input to pulse "high" coincident to whenever the C1 and J1 bytes are being sampled via the "RXD_D[7:0]" input pins. d. 1 - J1 Bytes Only This selection configures the following. e. The STS-3/STM-1 Transmit Telecom Bus Interface to only pulse the "TXA_C1J1" output pin coincident to whenever the J1 byte is being output via the "TXA_D[7:0]" output pins. The "TXA_C1J1" output pin will NOT be pulsed "high" whenever the C1 byte is being output via the "TXA_D[7:0]" output pins The STS-3/STM-1 Receive Telecom Bus Interface will expect the "RXD_C1J1" input to only pulse "high" coincident to whenever the J1 byte is being sampled via the "RXD_D[7:0]" input pins. The "RXD_C1J1" input pin will NOT be pulsed "high" whenever the C1 byte is being input via the "RXD_D[7:0]" input pins Note: f. Note: Bit 2 Telecom Bus Parity Odd R/W Telecom Bus Parity - ODD Parity Select: This READ/WRITE bit-field permits the user to configure the STS-3/STM1 Telecom Bus Interface to do the following. In the Transmit (Drop) Direction The STS-3/STM-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) TxD_D[7:0] output pins, or (2) 77 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 TxD_D[7:0] output pins, the states of the TxD_PL and TxD_C1J1 output pins (depending upon user setting for Bit 3). In the Receive (Add) Direction Receive STS-3/STM-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) RxA_D[7:0] input pins, or (2) RxA_D[7:0] input pins, the states of the RxA_PL and RxA_C1J1 input pins (depending upon user setting for Bit 3). 0 - Configures Transmit (Drop) Telecom Bus to compute EVEN parity and configures the Receive (Add) Telecom Bus to verify EVEN parity. 1 - Configures Transmit (Drop) Telecom Bus to compute ODD parity and configures the Receive (Add) Telecom Bus to verify ODD parity. Bit 1 Telecom Bus Parity Disable R/W Telecom Bus Parity Disable: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the "TxA_DP" output pin. This bit field also permits the user to enable or disable parity verification by the Receive Telecom Bus. 0 - Enables Parity Calculation (on the Transmit Telecom Bus) and Disables Parity Verification (on the Receive Telecom Bus. 1 - Disables Parity Calculation and Verification Bit 0 Rephase OFF Only R/W Telecom Bus - Rephase Disable: This READ/WRITE bit-field permits the user to configure the Receive STS-3/STM-1 Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the "RxD_D[7:0] input pins. Note: If the Receive STS-3/STM-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the "RxD_C1J1" input pin), then this feature is unnecessary. 1 - Disables Rephase 0 - Enables Rephase 78 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 30: Interface Control Register - Byte 2 - STS-1/STM-0 Telecom Bus 2 (Address Location= 0x0139) BIT 7 STS-1 Telecom Bus ON # 2 R/W 0 BIT 6 STS-1 Telecom Bus TriState # 2 R/W 0 BIT 5 Unused BIT 4 STS-1 Telecom Bus Parity Type # 2 R/W 0 BIT 3 STS-1 Telecom Bus J1 ONLY R/W 0 BIT 2 STS-1 Telecom Bus Parity Odd R/W 0 BIT 1 STS-1 Telecom Bus Parity Disable R/W 0 BIT 0 STS-1 REPHASE OFF R/W 0 R/O 0 BIT NUMBER Bit 7 NAME STS-1 Telecom Bus ON # 2 TYPE R/W DESCRIPTION STS-1 Telecom Bus ON - Channel 2: This READ/WRITE bit-field permits the user to either enable or disable the Telecom Bus associated with STS-1 Telecom Bus # 2. If the STS-1 Telecom Bus is enabled, then an STS-1 signal will be mapped into (demapped) from the STS-3 signal. If STS-1 Telecom Bus Interface - Channel 2 is disabled, then Channel 2 will support the mapping of DS3, E3 or STS-1 into the STS-3 signal. 0 - STS-1 Telecom Bus # 2 is disabled. In this mode, DS3/E3/STS-1 Channel 2 will now be enabled. Depending upon user's selection, the following functional blocks (within Channel 2) will now be enabled. If DS3/E3 Framing is support * DS3/E3 Framer Block * DS3/E3 Mapper Block * DS3/E3 Jitter Attenuator/De-Sync Block If STS-1 Framing is supported * Receive STS-1 TOH Processor Block * Receive STS-1 POH Processor Block * Transmit STS-1 POH Processor Block * Transmit STS-1 TOH Processor Block 1 - STS-1 Telecom Bus # 2 is enabled. In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with Channel 2 will be disabled. Bit 6 STS-1 Telecom Bus Tri-State # 2 R/W STS-1 Telecom Bus Tri-state - Channel 2: This READ/WRITE bit-field permits the user to "tri-state" the Telecom Bus Interface. 0 - Telecom Bus Interface is NOT tri-stated. 1 - Telecom Bus Interface is tri-stated. Note: This READ/WRITE bit-field is ignored if the STS-1 Transmit and Receive Telecom Bus Interface is disabled. Bit 5 Bit 4 Unused STS-1 Telecom Bus Parity Type # R/W R/W STS-1 Telecom Bus Parity Type - Channel 2: This READ/WRITE bit-field permits the user to define the parameters, over hi h "T l B" it ill b td 79 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 2 which "Telecom Bus" parity will be computed. 0 - Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus - data bus pins (e.g., STS1TXA_D_2[7:0] and STS1RXD_D_2[7:0]). If the user implements this selection, then the following will happen. g. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the "STS1RXD_DP_2" output pin) based upon and coincident with the data being output via the "STS1RXD_D_2[7:0]" output pins. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "STS1TXA_DP_2" input pin) based upon the data which is being input (and latched) via the "STS1TXA_D_2[7:0]" input pins. 20 0 Rev2...0...0 200 h. 1 - Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus - data bus pins (e.g., STS1TXA_D_2[7:0] and STS1RXD_D_3[7:0]); the STS1TXA_C1J1_2, STS1RXD_C1J1_2, STS1TXA_PL_2 and STS1RXD_PL_2 input/output pins. If the user implements this selection, then the following will happen. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the "RXD_DP_2" output) based upon and coincident with (1) the data being output via the "STS1RXD_D_2[7:0]" output pins, (2) the state of the "STS1RXD_PL_2" output pin, and (3) the state of the "STS1RXD_C1J1_2" output pin. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "STS1TXA_DP_2" input pin) based upon (1) the data which is being input (and latched) via the "STS1TXA_D_2[7:0]" input pins, (2) the state of the "STS1TXA_PL_2" input pin, and (3) the state of the "STS1TXA_C1J1_2" input pin. Note: This bit-field is disabled if the STS-1 Telecom Bus is disabled. The user can configure the STS-1 Telecom Bus to compute with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity - Odd), within this register. Bit 3 STS-1 Telecom Bus J1 ONLY R/W Telecom Bus - J1 Indicator Only - Channel 2: This READ/WRITE bit-field permits the user to configure how the STS-1 Transmit and Receive Telecom Bus interface handles the "STS1TXA_C1J1_2" and STS1RXD_C1J1_2" signals, as described below. 0 - C1 and J1 Bytes This selection configures the following. a. The STS-1 Receive Telecom Bus to pulse the "STS1RXD_C1J1_2" output coincident to whenever the C1 and J1 bytes are being output via the "STS1RXD_D_2[7:0]" output pins. The STS-1 Transmit Telecom Bus will expect the "STS1TXA_C1J1_2" input to pulse "high" coincident to whenever the C1 and J1 bytes are being sampled via the "STS1TXA_D_2[7:0]" input pins. b. 1 - J1 Bytes Only This selection configures the following. a. The STS-1 Receive Telecom Bus Interface to only pulse the "STS1RXD_C1J1_2" output pin coincident to whenever the J1 byte is being output via the "STSRXD_D_2[7:0]" output pins. The "STS1RXD_C1J1_2" output pin will NOT be pulsed "high" whenever the C1 byte is being output via the "STS1RXD_D_2[7:0]" Note: 80 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS output pins b. The STS-1 Transmit Telecom Bus Interface will expect the "STS1TXA_C1J1_2" input to only pulse "high" coincident to whenever the J1 byte is being sampled via the "STS1TXA_D_2[7:0]" input pins. The "STS1TXA_C1J1_2" input pin will NOT be pulsed "high" whenever the C1 byte is being input via the "STS1TXA_D_2[7:0]" input pins Note: Bit 2 STS-1 Telecom Bus Parity Odd R/W Telecom Bus Parity - ODD Parity Select - Channel 2: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus Interface, associated with Channel 2 to do the following. In the Receive (Drop) Direction Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) STS1RxD_D_2[7:0] output pins, or (2) STS1RxD_D_2[7:0] output pins, the states of the STS1RxD_PL_2 and STS1RxD_C1J1_2 output pins (depending upon user setting for Bit 3). In the Transmit (Add) Direction Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) STS1TxA_D_2[7:0] input pins, or (2) STS1TxA_D_2[7:0] input pins, the states of the STS1TxA_PL_2 and STS1TxA_C1J1_2 input pins (depending upon user setting for Bit 3). 0 - Configures Receive (Drop) Telecom Bus to compute EVEN parity and configures the Transmit (Add) Telecom Bus to verify EVEN parity. 1 - Configures Receive (Drop) Telecom Bus to compute ODD parity and configures the Transmit (Add) Telecom Bus to verify ODD parity. Bit 1 STS-1 Telecom Bus Parity Disable R/W STS-1 Telecom Bus Parity Disable - Channel 2: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the "STSRxD_DP_2" output pin. Further, this bit-field also permits the user to enable or disable parity verification via the "STS1TxA_DP_2" input pin by the Transmit Telecom Bus. 1 - Disables Parity Calculation (on the Receive Telecom Bus) and Disables Parity Verification (on the Transmit Telecom Bus. 0 - Enables Parity Calculation and Verification Bit 0 STS-1 REPHASE OFF R/W STS-1 Telecom Bus - Rephase Disable - Channel 2: This READ/WRITE bit-field permits the user to configure the Receive STS-1 Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the "RxD_D[7:0] input pins. Note: If the Receive STS-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the "RxD_C1J1" input pin), then this feature is unnecessary. 1 - Disable Rephase 0 - Enable Rephase 81 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 31: Interface Control Register - Byte 1 - STS-1/STM-0 Telecom Bus 1 (Address Location= 0x013A) BIT 7 STS-1 Telecom Bus ON #1 R/W 0 BIT 6 STS-1 Telecom Bus TriState # 1 R/W 0 BIT 5 Unused BIT 4 STS-1 Telecom Bus Parity Type # 1 R/W 0 BIT 3 STS-1 Telecom Bus J1 ONLY R/W 0 BIT 2 STS-1 Telecom Bus Parity ODD R/W 0 BIT 1 STS-1 Telecom Bus Parity Disable R/W 0 BIT 0 STS-1 REPHASE OFF R/W 0 R/W 0 BIT NUMBER Bit 7 NAME STS-1 Telecom Bus ON # 1 TYPE R/W DESCRIPTION STS-1 Telecom Bus ON - Channel 1: This READ/WRITE bit-field permits the user to either enable or disable the Telecom Bus associated with STS-1 Telecom Bus # 1. If the STS-1 Telecom Bus is enabled, then an STS-1 signal will be mapped into (demapped from) the STS-3 signal. If STS-1 Telecom Bus Interface - Channel 1 is disabled, then Channel 1 will support the mapping of DS3, E3 or STS-1 into the STS-3 signal. 0 - STS-1 Telecom Bus # 1 is disabled. In this mode, DS3/E3/STS-1 Channel 1 will now be enabled. Depending upon user's selection, the following functional blocks (within Channel 1) will now be enabled. If DS3/E3 Framing is supported * DS3/E3 Framer Block * DS3/E3 Mapper Block * DS3/E3 Jitter Attenuator/De-Sync Block If STS-1 Framing is supported * Receive STS-1 TOH Processor Block * Receive STS-1 POH Processor Block * Transmit STS-1 POH Processor Block * Transmit STS-1 TOH Processor Block 1 - STS-1 Telecom Bus # 1 is enabled. In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with Channel 1 will be disabled. Bit 6 STS-1 Telecom Bus TriState # 1 R/W STS-1 Telecom Bus Tri-state - Channel 1: This READ/WRITE bit-field permits the user to "tri-state" the Telecom Bus Interface. 0 - Telecom Bus Interface is NOT tri-stated. 1 - Telecom Bus Interface is tri-stated. Note: This READ/WRITE bit-field is ignored if the STS-1 Transmit and Receive Telecom Bus Interface is disabled. Bit 5 Bit 4 Unused STS-1 Telecom Bus Parity R/O R/W STS-1 Telecom Bus Parity Type - Channel 1: This READ/WRITE bit-field permits the user to define the parameters, over hi h "T l B" it ill b td 82 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Type # 1 which "Telecom Bus" parity will be computed. 0 - Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus - data bus pins (e.g., STS1TXA_D_1[7:0] and STS1RXD_D_1[7:0]). If the user implements this selection, then the following will happen. a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the "STS1RXD_DP_1" output pin) based upon and coincident with the data being output via the "STS1RXD_D_1[7:0]" output pins. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "STS1TXA_DP_1" input pin) based upon the data which is being input (and latched) via the "STS1TXA_D_1[7:0]" input pins. b. 1 - Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus - data bus pins (e.g., STS1TXA_D_1[7:0] and STS1RXD_D_1[7:0]); the STS1TXA_C1J1_1, STS1RXD_C1J1_1, STS1TXA_PL_1 and STS1RXD_PL_1 input/output pins. If the user implements this selection, then the following will happen. a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the "STS1RXD_DP_1" output) based upon and coincident with (1) the data being output via the "STS1RXD_D_1[7:0]" output pins, (2) the state of the "STS1RXD_PL_1" output pin, and (3) the state of the "STS1RXD_C1J1_1" output pin. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "STS1TXA_DP_1" input pin) based upon (1) the data which is being input (and latched) via the "STS1TXA_D_1[7:0]" input pins, (2) the state of the "STS1TXA_PL_1" input pin, and (3) the state of the "STS1TXA_C1J1_1" input pin. This bit-field is disabled if the STS-1 Telecom Bus is disabled. The user can configure the STS-1 Telecom Bus to compute/verify with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity - Odd), within this register. b. Note: Bit 3 STS-1 Telecom Bus J1 ONLY R/W Telecom Bus - J1 Indicator Only - Channel 1: This READ/WRITE bit-field permits the user to configure how the STS-1 Transmit and Receive Telecom Bus interface handles the "STS1TXA_C1J1_1" and STS1RXD_C1J1_1" signals, as described below. 0 - C1 and J1 Bytes This selection configures the following. a. The STS-1 Receive Telecom Bus to pulse the "STS1RXD_C1J1_1" output coincident to whenever the C1 and J1 bytes are being output via the "STS1RXD_D_1[7:0]" output pins. The STS-1 Transmit Telecom Bus will expect the "STS1TXA_C1J1_1" input to pulse "high" coincident to whenever the C1 and J1 bytes are being sampled via the "STS1TXA_D_1[7:0]" input pins. b. 1 - J1 Bytes Only This selection configures the following. i. The STS-1 Receive Telecom Bus Interface to only pulse the "STS1RXD_C1J1_1" output pin coincident to whenever the J1 byte is being output via the "STS1RXD_D_1[7:0]" output pins. The "STS1RXD_C1J1_1" output pin will NOT be pulsed "high" whenever the C1 byte is being output via the "STS1RXD_D_1[7:0]" Note: 83 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS output pins). j. The STS-1 Transmit Telecom Bus Interface will expect the "STS1TXA_C1J1_1" input to only pulse "high" coincident to whenever the J1 byte is being sampled via the "STS1TXA_D_1[7:0]" input pins. The "STS1TXA_C1J1_1" input pin will NOT be pulsed "high" whenever the C1 byte is being input via the "STS1TXA_D_1[7:0]" input pins). 20 0 Rev2...0...0 200 Note: Bit 2 STS-1 Telecom Bus Parity Odd R/W Telecom Bus Parity - ODD Parity Select - Channel 1: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus Interface, associated with Channel 1 to do the following. In the Receive (Drop) Direction Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) STS1RxD_D_1[7:0] output pins, or (2) STS1RxD_D_1[7:0] output pins, the states of the STS1RxD_PL_1 and "STS1RxD_C1J1_1 output pins (depending upon user setting for Bit 3). In the Transmit (Add) Direction Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) STS1TxA_D_1[7:0] input pins, or (2) STS1TxA_D_1[7:0] input pins, the states of the STS1TxA_PL_1 and STS1TxA_C1J1_1 input pins (depending upon user setting for Bit 3). 0 - Configures Receive (Drop) Telecom Bus to compute EVEN parity and configures the Transmit (Add) Telecom Bus to verify EVEN parity 1 - Configures Receive (Drop) Telecom Bus to compute ODD parity and configures the Transmit (Add) Telecom Bus to verify ODD parity. Bit 1 STS-1 Telecom Bus Parity Disable R/W STS-1 Telecom Bus Parity Disable - Channel 1: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the "STSRxD_DP_1" output pin. Further, this bit field also permits the user to enable or disable parity verification via the "STS1TxA_DP_1" input pin by the Transmit Telecom Bus. 1 - Disables Parity Calculation (on the Receive Telecom Bus) and Disables Parity Verification (on the Transmit Telecom Bus. 0 - Enables Parity Calculation and Verification Bit 0 STS-1 REPHASE OFF R/W STS-1 Telecom Bus - Rephase Disable - Channel 1: This READ/WRITE bit-field permits the user to configure the Receive STS-1 Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the "RxD_D[7:0] input pins. Note: If the Receive STS-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the "RxD_C1J1" input pin), then this feature is unnecessary. 1 - Disables Rephase 0 - Enables Rephase 84 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 32: Interface Control Register - Byte 0 - STS-1/STM-0 Telecom Bus 0 (Address Location= 0x013B) BIT 7 STS-1 Telecom Bus ON #0 R/W 0 BIT 6 STS-1 Telecom Bus TriState # 0 R/W 0 BIT 5 STS-3c REPHASE OFF R/W 0 BIT 4 STS-1 Telecom Bus Parity Type # 0 R/W 0 BIT 3 STS-1 Telecom Bus J1 ONLY R/W 0 BIT 2 STS-1 Telecom Bus Parity Odd R/W 0 BIT 1 STS-1 Telecom Bus Parity Disable R/W 0 BIT 0 STS-1 REPHASE OFF R/W 0 BIT NUMBER Bit 7 NAME STS-1 Telecom Bus ON # 0 TYPE R/W DESCRIPTION STS-1 Telecom Bus ON - Channel 0: This READ/WRITE bit-field permits the user to either enable or disable the Telecom Bus associated with STS-1 Telecom Bus # 0. If the STS-1 Telecom Bus is enabled, then an STS-1 signal will be mapped into (demapped from) the STS-3 signal. If STS-1 Telecom Bus Interface - Channel 3 is disabled, then Channel 0 will support the mapping of DS3, E3 or STS-1 into the STS-3 signal. 0 - STS-1 Telecom Bus # 0 is disabled. In this mode, DS3/E3/STS-1 Channel 0 will now be enabled. Depending upon user's selection, the following functional blocks (within Channel 0) will now be enabled. If DS3/E3 Framing is supported * DS3/E3 Framer Block * DS3/E3 Mapper Block * DS3/E3 Jitter Attenuator/De-Sync Block If STS-1 Framing is supported * Receive STS-1 TOH Processor Block * Receive STS-1 POH Processor Block * Transmit STS-1 POH Processor Block * Transmit STS-1 TOH Processor Block 1 - STS-1 Telecom Bus # 0 is enabled. In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with Channel 0 will be disabled. Bit 6 STS-1 Telecom Bus Tri-State # 0 R/W STS-1 Telecom Bus Tri-state - Channel 0: This READ/WRITE bit-field permits the user to "tri-state" the Telecom Bus Interface. 0 - Telecom Bus Interface is NOT tri-stated. 1 - Telecom Bus Interface is tri-stated. Note: This READ/WRITE bit-field is ignored if the STS-1 Transmit and Receive Telecom Bus Interface is disabled. Bit 5 STS-3c REPHASE OFF R/O STS-3c While Rephase Off: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus # 0 to process STS-3c data while the "Rephase" feature is disabled. 85 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - STS-1 Telecom Bus # 0 is processing STS-3 data. 1 - STS-1 Telecom Bus # 0 is processing STS-3c data. Note: Bit 4 STS-1 Telecom Bus Parity Type # 0 R/W This bit-field is ignored if STS-1 Telecom Bus Interface # 0 has been configured to operate in the "Rephase" Mode. 20 0 Rev2...0...0 200 STS-1 Telecom Bus Parity Type - Channel 0: This READ/WRITE bit-field permits the user to define the parameters, over which "Telecom Bus" parity will be computed. 0 - Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus - data bus pins (e.g., STS1TXA_D_0[7:0] and STS1RXD_D_0[7:0]). If the user implements this selection, then the following will happen. a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the "STS1RXD_DP_0" output pin) based upon and coincident with the data being output via the "STS1RXD_D_0[7:0]" output pins. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "STS1TXA_DP_0" input pin) based upon the data which is being input (and latched) via the "STS1TXA_D_0[7:0]" input pins. b. 1 - Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus - data bus pins (e.g., STS1TXA_D_0[7:0] and STS1RXD_D_0[7:0]); the STS1TXA_C1J1_0, STS1RXD_C1J1_0, STS1TXA_PL_0 and STS1RXD_PL_0 input/output pins. If the user implements this selection, then the following will happen. a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the "STS1RXD_DP_0" output) based upon and coincident with (1) the data being output via the "STS1RXD_D_0[7:0]" output pins, (2) the state of the "STS1RXD_PL_0" output pin, and (3) the state of the "STS1RXD_C1J1_0" output pin. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the "STS1TXA_DP_0" input pin) based upon (1) the data which is being input (and latched) via the "STS1TXA_D_0[7:0]" input pins, (2) the state of the "STS1TXA_PL_0" input pin, and (3) the state of the "STS1TXA_C1J1_0" input pin. This bit-field is disabled if the STS-1 Telecom Bus is disabled. The user can configure the STS-1 Telecom Bus to compute/verify with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity - Odd), within this register. b. Note: Bit 3 STS-1 Telecom Bus J1 ONLY R/W Telecom Bus - J1 Indicator Only - Channel 0: This READ/WRITE bit-field permits the user to configure how the STS-1 Transmit and Receive Telecom Bus interface handles the "STS1TXA_C1J1_0" and STS1RXD_C1J1_0" signals, as described below. 0 - C1 and J1 Bytes This selection configures the following. a. The STS-1 Receive Telecom Bus to pulse the "STS1RXD_C1J1_0" output coincident to whenever the C1 and J1 bytes are being output via the "STS1RXD_D_0[7:0]" output pins. The STS-1 Transmit Telecom Bus will expect the "STS1TXA_C1J1_0" input to pulse "high" coincident to whenever the C1 and J1 bytes are being sampled via the b. 86 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS "STS1TXA_D_0[7:0]" input pins. 1 - J1 Bytes Only This selection configures the following. a. The STS-1 Receive Telecom Bus Interface to only pulse the "STS1RXD_C1J1_0" output pin coincident to whenever the J1 byte is being output via the "STS1RXD_D_0[7:0]" output pins. The "STS1RXD_C1J1_0" output pin will NOT be pulsed "high" whenever the C1 byte is being output via the "STS1RXD_D_0[7:0]" output pins The STS-1 Transmit Telecom Bus Interface will expect the "STS1TXA_C1J1_0" input to only pulse "high" coincident to whenever the J1 byte is being sampled via the "STS1TXA_D_0[7:0]" input pins. The "STS1TXA_C1J1_0" input pin will NOT be pulsed "high" whenever the C1 byte is being input via the "STS1TXA_D_0[7:0]" input pins Note: b. Note: Bit 2 STS-1 Telecom Bus Parity Odd R/W Telecom Bus Parity - ODD Parity Select - Channel 0: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus Interface, associated with Channel 0 to do the following. In the Receive (Drop) Direction Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) STS1RxD_D_0[7:0] output pins, or (2) STS1RxD_D_0[7:0] output pins, the states of the STS1RxD_PL_0 and "STS1RxD_C1J1_0 output pins (depending upon user setting for Bit 3). In the Transmit (Add) Direction Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) STS1TxA_D_0[7:0] input pins, or (2) STS1TxA_D_0[7:0] input pins, the states of the STS1TxA_PL_0 and STS1TxA_C1J1_0 input pins (depending upon user setting for Bit 3). 0 - Configures Receive (Drop) Telecom Bus to compute EVEN parity and configures the Transmit (Add) Telecom Bus to verify EVEN parity 1 - Configures Receive (Drop) Telecom Bus to compute ODD parity and configures the Transmit (Add) Telecom Bus to verify ODD parity. Bit 1 STS-1 Telecom Bus Parity Disable R/W STS-1 Telecom Bus Parity Disable - Channel 0: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the "STSRxD_DP_0" output pin. Further, this bit field also permits the user to enable or disable parity verification via the "STS1TxA_DP_0" input pin by the Transmit Telecom Bus. 1 - Disables Parity Calculation (on the Receive Telecom Bus) and Disables Parity Verification (on the Transmit Telecom Bus. 0 - Enables Parity Calculation and Verification Bit 0 STS-1 REPHASE OFF R/W STS-1 Telecom Bus - Rephase Disable - Channel 0: This READ/WRITE bit-field permits the user to configure the Receive STS-1 Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the "RxD_D[7:0] input pins. Note: If the Receive STS-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the "RxD_C1J1" input pin), then this feature is unnecessary. 87 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Disables Rephase 0 - Enables Rephase 20 0 Rev2...0...0 200 88 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 33: Interface Control Register - STS-1/STM-0 Telecom Bus Interrupt Enable/Status Register (Address Location= 0x013C) BIT 7 Unused BIT 6 TB2 RxParity Error Interrupt Status RUR 0 BIT 5 TB1 RxParity Error Interrupt Status RUR 0 BIT 4 TB0 RxParity Error Interrupt Status RUR 0 BIT 3 Unused BIT 2 TB2 RxParity Error Interrupt Enable R/W 0 BIT 1 TB1 RxParity Error Interrupt Enable R/W 0 BIT 0 TB0 RxParity Error Interrupt Enable R/W 0 R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused Telecom Bus # 2 Receive Parity Error Interrupt Status TYPE R/O RUR DESCRIPTION STS-1 Telecom Bus # 2 - Receive Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or "STS-1 Telecom Bus - Channel 2" has declared a "Receive Parity Error" Interrupt since the last read of this register. 0 - The "Receive Parity Error" Interrupt has not occurred since the last read of this register. 1 - The "Receive Parity Error" Interrupt has occurred since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 5 Telecom Bus # 1 Receive Parity Error Interrupt Status RUR STS-1 Telecom Bus # 1 - Receive Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or "STS-1 Telecom Bus - Channel 1" has declared a "Receive Parity Error" Interrupt since the last read of this register. 0 - The "Receive Parity Error" Interrupt has not occurred since the last read of this register. 1 - The "Receive Parity Error" Interrupt has occurred since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 4 Telecom Bus # 0 Receive Parity Error Interrupt Status RUR STS-1 Telecom Bus # 0 - Receive Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or "STS-1 Telecom Bus - Channel 3" has declared a "Receive Parity Error" Interrupt since the last read of this register. 0 - The "Receive Parity Error" Interrupt has not occurred since the last read of this register. 1 - The "Receive Parity Error" Interrupt has occurred since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 3 2 Unused Telecom Bus # 2 - Receive Parity Error Interrupt R/O R/W STS-1 Telecom Bus # 2 - Receive Parity Error Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the "R i P it E "I t t f STS 1 T l B Ch l 2 If th 89 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Enable 20 0 Rev2...0...0 200 "Receive Parity Error" Interrupt for STS-1 Telecom Bus - Channel 2. If the user enables this interrupt, then STS-1 Telecom Bus - Channel 2 will generate an interrupt anytime the "Receive STS-1 Telecom Bus" detects a parity error within the incoming STS-1 data. 0 - Disables the "Receive Parity Error" Interrupt. 1 - Enables the "Receive Parity Error" Interrupt. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 1 Telecom Bus # 1 - Receive Parity Error Interrupt Enable R/W STS-1 Telecom Bus # 1 - Receive Parity Error Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the "Receive Parity Error" Interrupt for STS-1Telecom Bus - Channel 1. If the user enables this interrupt, then STS-1 Telecom Bus - Channel 1 will generate an interrupt anytime the "Receive STS-1 Telecom Bus" detects a parity error within the incoming STS-1 data. 0 - Disables the "Receive Parity Error" Interrupt. 1 - Enables the "Receive Parity Error" Interrupt. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 0 Telecom Bus # 0 - Receive Parity Error Interrupt Enable R/W STS-1 Telecom Bus # 0 - Receive Parity Error Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the "Receive Parity Error" Interrupt for STS-1 Telecom Bus - Channel 0. If the user enables this interrupt, then STS-1 Telecom Bus - Channel 0 will generate an interrupt anytime the "Receive STS-1 Telecom Bus" detects a parity error within the incoming STS-1 data. 0 - Disables the "Receive Parity Error" Interrupt. 1 - Enables the "Receive Parity Error" Interrupt. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 90 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 34: Interface Control Register - STS-1/STM-0 Telecom Bus FIFO Status Register (Address Location = 0x013D) BIT 7 Unused BIT 6 Unused BIT 5 STS-1 Telecom Bus Tx Overrun Bus 2 R/O 0 BIT 4 STS-1 Telecom Bus Tx Underrun Bus 2 R/O 0 BIT 3 STS-1 Telecom Bus Tx Overrun Bus 1 R/O 0 BIT 2 STS-1 Telecom Bus Tx Underrun Bus 1 R/O 0 BIT 1 STS-1 Telecom Bus Tx Overrun Bus 0 R/O 0 BIT 0 STS-1 Telecom Bus Tx Underrun Bus 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7 6 5 NAME Unused Unused STS-1 Telecom Bus - TxFIFO Overrun # 2 TYPE R/O R/O R/O DESCRIPTION STS-1 Telecom Bus - Transmit FIFO Overrun Indicator - Channel 2: This READ-ONLY bit-field indicates whether or not "STS-1 Telecom Bus - Channel 2" is currently declaring a "Transmit FIFO Overrun" condition. 0 - Indicates that "STS-1 Telecom Bus - Channel 2" is NOT declaring a "Transmit FIFO Overrun" condition. 1 - Indicates that "STS-1 Telecom Bus - Channel 2" is currently declaring a "Transmit FIFO Overrun" condition. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 4 STS-1 Telecom Bus - TxFIFO Underrun # 2 R/O STS-1 Telecom Bus - Transmit FIFO Underrun Indicator - Channel 2: This READ-ONLY bit-field indicates whether or not "STS-1 Telecom Bus - Channel 3" is currently declaring a "Transmit FIFO Underrun" condition. 0 - Indicates that "STS-1 Telecom Bus - Channel 2" is NOT declaring a "Transmit FIFO Underrun" condition. 1 - Indicates that "STS-1 Telecom Bus - Channel 2" is currently declaring a "Transmit FIFO Underrun" condition. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 3 STS-1 Telecom Bus - TxFIFO Overrun # 1 R/O STS-1 Telecom Bus - Transmit FIFO Overrun Indicator - Channel 1: This READ-ONLY bit-field indicates whether or not "STS-1 Telecom Bus - Channel 1" is currently declaring a "Transmit FIFO Overrun" condition. 0 - Indicates that "STS-1 Telecom Bus - Channel 1" is NOT declaring a "Transmit FIFO Overrun" condition. 1 - Indicates that "STS-1 Telecom Bus - Channel 1" is currently declaring a "Transmit FIFO Overrun" condition. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 2 STS-1 Telecom Bus - TxFIFO Underrun # 1 R/O STS-1 Telecom Bus - Transmit FIFO Underrun Indicator - Channel 1: This READ-ONLY bit-field indicates whether or not "STS-1 Telecom Bus - Channel 1" is currently declaring a "Transmit FIFO Underrun" condition. 0 - Indicates that "STS-1 Telecom Bus - Channel 1" is NOT declaring a 91 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS "Transmit FIFO Underrun" condition. 1 - Indicates that "STS-1 Telecom Bus - Channel 1" is currently declaring a "Transmit FIFO Underrun" condition. Note: 1 STS-1 Telecom Bus - TxFIFO Overrun # 0 R/O This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 20 0 Rev2...0...0 200 STS-1 Telecom Bus - Transmit FIFO Overrun Indicator - Channel 0: This READ-ONLY bit-field indicates whether or not "STS-1 Telecom Bus - Channel 0" is currently declaring a "Transmit FIFO Overrun" condition. 0 - Indicates that "STS-1 Telecom Bus - Channel 0" is NOT declaring a "Transmit FIFO Overrun" condition. 1 - Indicates that "STS-1 Telecom Bus - Channel 0" is currently declaring a "Transmit FIFO Overrun" condition. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 0 STS-1 Telecom Bus - TxFIFO Underrun # 0 R/O STS-1 Telecom Bus - Transmit FIFO Underrun Indicator - Channel 0: This READ-ONLY bit-field indicates whether or not "STS-1 Telecom Bus - Channel 0" is currently declaring a "Transmit FIFO Underrun" condition. 0 - Indicates that "STS-1 Telecom Bus - Channel 0" is NOT declaring a "Transmit FIFO Underrun" condition. 1 - Indicates that "STS-1 Telecom Bus - Channel 0" is currently declaring a "Transmit FIFO Underrun" condition. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 92 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 35: Interface Control Register - STS-1/STM-0 Telecom Bus FIFO Interrupt Status Register (Address Location= 0x013E) BIT 7 Unused BIT 6 Unused BIT 5 STS-1 Telecom Bus # 2 Tx Overrun Interrupt Status RUR 0 BIT 4 STS-1 Telecom Bus # 2 Tx Underrun Interrupt Status RUR 0 BIT 3 STS-1 Telecom Bus # 1 Tx Overrun Interrupt Status RUR 0 BIT 2 STS-1 Telecom Bus # 1 Tx Underrun Interrupt Status RUR 0 BIT 1 STS-1 Telecom Bus # 0 Tx Overrun Interrupt Status RUR 0 BIT 0 STS-1 Telecom Bus # 0 Tx Underrun Interrupt Status RUR 0 R/O 0 R/O 0 BIT NUMBER 7 6 5 NAME Unused Unused STS-1 Telecom Bus # 2 - TxFIFO Overrun Interrupt Status TYPE R/O R/O RUR DESCRIPTION STS-1 Telecom Bus - TxFIFO Overrun Interrupt Status - Channel 2: This RESET-upon-READ bit-field indicates whether or not "STS-1 Telecom Bus - Channel 2" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. 0 - Indicates that "STS-1 Telecom Bus - Channel 2" has NOT declared a "TxFIFO Overrun" Interrupt since the last read of this register. 1 - Indicates that "STS-1 Telecom Bus - Channel 2" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 4 STS-1 Telecom Bus # 2 - TxFIFO Underrun Interrupt Status RUR STS-1 Telecom Bus - TxFIFO Underrun Interrupt Status - Channel 2: This RESET-upon-READ bit-field indicates whether or not "STS-1 Telecom Bus - Channel 2" has declared a "TxFIFO Underrun" Interrupt since the last read of this register. 0 - Indicates that "STS-1 Telecom Bus - Channel 2" has NOT declared a "TxFIFO Underrun" Interrupt since the last read of this register. 1 - Indicates that "STS-1 Telecom Bus - Channel 2" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 3 STS-1 Telecom Bus # 1 - TxFIFO Overrun Interrupt Status RUR STS-1 Telecom Bus - TxFIFO Overrun Interrupt Status - Channel 1: This RESET-upon-READ bit-field indicates whether or not "STS-1 Telecom Bus - Channel 1" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. 0 - Indicates that "STS-1 Telecom Bus - Channel 1" has NOT declared a "TxFIFO Overrun" Interrupt since the last read of this register. 1 - Indicates that "STS-1 Telecom Bus - Channel 1" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 2 STS-1 Telecom Bus # 1 - RUR STS-1 Telecom Bus - TxFIFO Underrun Interrupt Status - Channel 1: 93 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TxFIFO Underrun Interrupt Status 20 0 Rev2...0...0 200 This RESET-upon-READ bit-field indicates whether or not "STS-1 Telecom Bus - Channel 1" has declared a "TxFIFO Underrun" Interrupt since the last read of this register. 0 - Indicates that "STS-1 Telecom Bus - Channel 1" has NOT declared a "TxFIFO Underrun" Interrupt since the last read of this register. 1 - Indicates that "STS-1 Telecom Bus - Channel 1" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 1 STS-1 Telecom Bus # 0 - TxFIFO Overrun Interrupt Status RUR STS-1 Telecom Bus - TxFIFO Overrun Interrupt Status - Channel 0: This RESET-upon-READ bit-field indicates whether or not "STS-1 Telecom Bus - Channel 0" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. 0 - Indicates that "STS-1 Telecom Bus - Channel 0" has NOT declared a "TxFIFO Overrun" Interrupt since the last read of this register. 1 - Indicates that "STS-1 Telecom Bus - Channel 0" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 0 STS-1 Telecom Bus # 0 - TxFIFO Underrun Interrupt Status RUR STS-1 Telecom Bus - TxFIFO Underrun Interrupt Status - Channel 0: This RESET-upon-READ bit-field indicates whether or not "STS-1 Telecom Bus - Channel 0" has declared a "TxFIFO Underrun" Interrupt since the last read of this register. 0 - Indicates that "STS-1 Telecom Bus - Channel 0" has NOT declared a "TxFIFO Underrun" Interrupt since the last read of this register. 1 - Indicates that "STS-1 Telecom Bus - Channel 0" has declared a "TxFIFO Overrun" Interrupt since the last read of this register. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 94 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 36: Interface Control Register - STS-1/STM-0 Telecom Bus FIFO Interrupt Enable Register (Address Location= 0x013F) BIT 7 Unused BIT 6 Unused BIT 5 STS-1 Telecom Bus # 2 Tx Overrun Interrupt Enable R/W 0 BIT 4 STS-1 Telecom Bus # 2 Tx Underrun Interrupt Enable R/W 0 BIT 3 STS-1 Telecom Bus # 1 Tx Overrun Interrupt Enable R/W 0 BIT 2 STS-1 Telecom Bus # 1 Tx Underrun Interrupt Enable R/W 0 BIT 1 STS-1 Telecom Bus # 0 Tx Overrun Interrupt Enable R/W 0 BIT 0 STS-1 Telecom Bus # 0 Tx Underrun Interrupt Enable R/W 0 R/O 0 R/O 0 BIT NUMBER 7 6 5 NAME Unused Unused STS-1 Telecom Bus # 2 TxFIFO Overrun Interrupt Enable TYPE R/O R/O DESCRIPTION STS-1 Telecom Bus - TxFIFO Overrun Interrupt Enable - Channel 2: This READ/WRITE bit-field permits the user to either enable or disable the "TxFIFO Overrun" Interrupt, associated with STS-1 Telecom Bus - Channel 2. If the user enables this interrupt, then the "STS-1 Telecom Bus - Channel 2" will generate an interrupt anytime it declares the "TxFIFO Overrun" condition. 0 - Disables the "TxFIFO Overrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 2. 1 - Enables the "TxFIFO Overrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 2. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 4 STS-1 Telecom Bus # 2 TxFIFO Underrun Interrupt Enable R/W STS-1 Telecom Bus - TxFIFO Underrun Interrupt Enable - Channel 2: This READ/WRITE bit-field permits the user to either enable or disable the "TxFIFO Underrun" Interrupt, associated with STS-1 Telecom Bus - Channel 2. If the user enables this interrupt, then the "STS-1 Telecom Bus - Channel 2" will generate an interrupt anytime it declares the "TxFIFO Underrun" condition. 0 - Disables the "TxFIFO Underrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 2. 1 - Enables the "TxFIFO Underrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 2. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 2" has been enabled. 3 STS-1 Telecom Bus # 1 TxFIFO Overrun Interrupt Enable R/W STS-1 Telecom Bus - TxFIFO Overrun Interrupt Enable - Channel 1: This READ/WRITE bit-field permits the user to either enable or disable the "TxFIFO Overrun" Interrupt, associated with STS-1 Telecom Bus - Channel 1. If the user enables this interrupt, then the "STS-1 Telecom Bus - Channel 1" will generate an interrupt anytime it declares the "TxFIFO Overrun" condition. 0 - Disables the "TxFIFO Overrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 1. 1 - Enables the "TxFIFO Overrun" Interrupt, associated with "STS-1 95 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Telecom Bus - Channel 1. Note: 2 STS-1 Telecom Bus # 1 TxFIFO Underrun Interrupt Enable R/W This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 20 0 Rev2...0...0 200 STS-1 Telecom Bus - TxFIFO Underrun Interrupt Enable - Channel 1: This READ/WRITE bit-field permits the user to either enable or disable the "TxFIFO Underrun" Interrupt, associated with STS-1 Telecom Bus - Channel 1. If the user enables this interrupt, then the "STS-1 Telecom Bus - Channel 1" will generate an interrupt anytime it declares the "TxFIFO Underrun" condition. 0 - Disables the "TxFIFO Underrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 1. 1 - Enables the "TxFIFO Underrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 1. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 1" has been enabled. 1 STS-1 Telecom Bus # 0 TxFIFO Overrun Interrupt Enable R/W STS-1 Telecom Bus - TxFIFO Overrun Interrupt Enable - Channel 0: This READ/WRITE bit-field permits the user to either enable or disable the "TxFIFO Overrun" Interrupt, associated with STS-1 Telecom Bus - Channel 0. If the user enables this interrupt, then the "STS-1 Telecom Bus - Channel 0" will generate an interrupt anytime it declares the "TxFIFO Overrun" condition. 0 - Disables the "TxFIFO Overrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 0. 1 - Enables the "TxFIFO Overrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 0. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 0 STS-1 Telecom Bus # 0 TxFIFO Underrun Interrupt Enable R/W STS-1 Telecom Bus - TxFIFO Underrun Interrupt Enable - Channel 0: This READ/WRITE bit-field permits the user to either enable or disable the "TxFIFO Underrun" Interrupt, associated with STS-1 Telecom Bus - Channel 3. If the user enables this interrupt, then the "STS-1 Telecom Bus - Channel 0" will generate an interrupt anytime it declares the "TxFIFO Underrun" condition. 0 - Disables the "TxFIFO Underrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 0. 1 - Enables the "TxFIFO Underrun" Interrupt, associated with "STS-1 Telecom Bus - Channel 0. Note: This bit-field is only active if "STS-1 Telecom Bus - Channel 0" has been enabled. 96 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 37: Operation General Purpose Input/Output Register - Byte 0 (Address Location= 0x0147) BIT 7 GPIO_7 R/W 0 BIT 6 GPIO_6 R/W 0 BIT 5 GPIO_5 R/W 0 BIT 4 GPIO_4 R/W 0 BIT 3 GPIO_3 R/W 0 BIT 2 GPIO_2 R/W 0 BIT 1 GPIO_1 R/W 0 BIT 0 GPIO_0 R/W 0 BIT NUMBER 7 NAME GPIO_7 TYPE R/W DESCRIPTION General Purpose Input/Output Pin # 7: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_7" pin is configured to be an input or an output pin. If GPIO_7 is configured to be an input pin: If GPIO_7 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_7" (pin number AA25) input pin. If the "GPIO_7" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_7" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_7 is configured to be an output pin: If GPIO_7 is configured to be an output pin, then the user can control the logic level of "GPIO_7" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_7 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_7 output pin to be driven "HIGH". Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 2 is enabled. 6 GPIO_6 R/W General Purpose Input/Output Pin # 6: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_6" pin is configured to be an input or an output pin. If GPIO_6 is configured to be an input pin: If GPIO_6 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_6" (pin number W24) input pin. If the "GPIO_6" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_6" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_6 is configured to be an output pin: If GPIO_6 is configured to be an output pin, then the user can control the logic level of "GPIO_6" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_6 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_6 output pin to be driven "HIGH". Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 2 is enabled. 5 GPIO_5 R/W General Purpose Input/Output Pin # 5: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_5" pin is configured to be an input or an output pin. 97 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS If GPIO_5 is configured to be an input pin: If GPIO_5 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_5" (pin number AC26) input pin. If the "GPIO_5" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_5" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_5 is configured to be an output pin: If GPIO_5 is configured to be an output pin, then the user can control the logic level of "GPIO_5" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_5 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_5 output pin to be driven "HIGH". Note: 4 GPIO_4 R/W This register bit-field is only active if STS-1 Telecom Bus - Channel 1 is enabled. 20 0 Rev2...0...0 200 General Purpose Input/Output Pin # 4: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_4" pin is configured to be an input or an output pin. If GPIO_4 is configured to be an input pin: If GPIO_4 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_4" (pin number Y25) input pin. If the "GPIO_4" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_4" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_4 is configured to be an output pin: If GPIO_4 is configured to be an output pin, then the user can control the logic level of "GPIO_4" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_4 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_4 output pin to be driven "HIGH". Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 1 is enabled. 3 GPIO_3 R/W General Purpose Input/Output Pin # 3: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_3" pin is configured to be an input or an output pin. If GPIO_3 is configured to be an input pin: If GPIO_3 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_3" (pin number AB26) input pin. If the "GPIO_3" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_3" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_3 is configured to be an output pin: If GPIO_3 is configured to be an output pin, then the user can control the logic level of "GPIO_3" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_3 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_3 output pin to be driven "HIGH". 98 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 1 is enabled. 2 GPIO_2 R/W General Purpose Input/Output Pin # 2: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_2" pin is configured to be an input or an output pin. If GPIO_2 is configured to be an input pin: If GPIO_2 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_2" (pin number V23) input pin. If the "GPIO_2" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_2" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_2 is configured to be an output pin: If GPIO_2 is configured to be an output pin, then the user can control the logic level of "GPIO_2" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_2 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_2 output pin to be driven "HIGH". Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 0 is enabled. 1 GPIO_1 R/W General Purpose Input/Output Pin # 1: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_1" pin is configured to be an input or an output pin. If GPIO_1 is configured to be an input pin: If GPIO_1 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_1" (pin number AC27) input pin. If the "GPIO_1" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_1" input pin is pulled to a logic "LOW", then this register bit will be set to "0". If GPIO_1 is configured to be an output pin: If GPIO_1 is configured to be an output pin, then the user can control the logic level of "GPIO_1" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_1 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_1 output pin to be driven "HIGH". Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 0 is enabled. 0 GPIO_0 R/W General Purpose Input/Output Pin # 0: The exact function of this READ/WRITE bit-field depends upon whether the "GPIO_0" pin is configured to be an input or an output pin. If GPIO_0 is configured to be an input pin: If GPIO_0 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the "GPIO_0" (pin number W25) input pin. If the "GPIO_0" input pin is pulled to a logic "HIGH", then this register bit will be set to "1". Conversely, if the "GPIO_0" input pin is pulled to a logic "LOW", then this register bit will be set to "0". 99 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS If GPIO_0 is configured to be an output pin: If GPIO_0 is configured to be an output pin, then the user can control the logic level of "GPIO_0" by writing the appropriate value into this bit-field. Setting this bit-field to "0" causes the GPIO_0 output pin to be driven "LOW". Conversely, setting this bit-field to "1" causes the GPIO_0 output pin to be driven "HIGH". Note: This register bit-field is only active if STS-1 Telecom Bus - Channel 0 is enabled. 20 0 Rev2...0...0 200 100 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 38: Operation General Purpose Input/Output Direction Register 0 (Address Location= 0x014B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 GPIO_DIR[7:0] BIT NUMBER 7 NAME GPIO_DIR[7] TYPE R/W GPIO_7 Direction Select: DESCRIPTION This READ/WRITE bit-field permits the user to configure the "GPIO_7" pin (pin number AA25) to function as either an input or an output pin. 0 - Configures GPIO_7 to function as an input pin. 1 - Configures GPIO_7 to function as an output pin. Note: 6 GPIO_DIR[6] R/W This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 2 is enabled. GPIO_6 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_6" pin (pin number W24) to function as either an input or an output pin. 0 - Configures GPIO_6 to function as an input pin. 1 - Configures GPIO_6 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 2 is enabled. 5 GPIO_DIR[5] R/W GPIO_5 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_5" pin (pin number AC26) to function as either an input or an output pin. 0 - Configures GPIO_5 to function as an input pin. 1 - Configures GPIO_5 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 1 is enabled. 4 GPIO_DIR[4] R/W GPIO_4 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_4" pin (pin number Y25) to function as either an input or an output pin. 0 - Configures GPIO_4 to function as an input pin. 1 - Configures GPIO_4 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 1 is enabled. 3 GPIO_DIR[3] R/W GPIO_3 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_3" pin (pin number AB26) to function as either an input or an output pin. 0 - Configures GPIO_3 to function as an input pin. 1 - Configures GPIO_3 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 1 is enabled. 101 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 2 GPIO_DIR[2] R/W GPIO_2 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_2" pin (pin number V23) to function as either an input or an output pin. 0 - Configures GPIO_2 to function as an input pin. 1 - Configures GPIO_2 to function as an output pin. Note: 1 GPIO_DIR[1] R/W This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 0 is enabled. 20 0 Rev2...0...0 200 GPIO_1 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_1" pin (pin number AC27) to function as either an input or an output pin. 0 - Configures GPIO_1 to function as an input pin. 1 - Configures GPIO_1 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 0 is enabled. 0 GPIO_DIR[0] R/W GPIO_0 Direction Select: This READ/WRITE bit-field permits the user to configure the "GPIO_0" pin (pin number W25) to function as either an input or an output pin. 0 - Configures GPIO_0 to function as an input pin. 1 - Configures GPIO_0 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface - Channel 0 is enabled. 102 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 39: Operation Output Control Register - Byte 1 (Address Location= 0x0150) BIT 7 8kHz or STUFF Out Enable BIT 6 8kHz OUT Select BIT 5 Egress Direction Monitored - STUFF Output R/W 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 R/W 0 R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7 NAME 8kHz or STUFF Out Enable TYPE R/W DESCRIPTION 8kHz or STUFF Output Enable - LOF Output Pin: This READ/WRITE bit-field, along with Bit 6 (8kHz OUT Select) permits the user to define the role of the LOF output pin (pin AD11). The relationship between the states of these bit-fields and the corresponding role of the LOF output pin is presented below. Bit 7 (8kHz or STUFF Out Enable) 0 0 1 1 Note: 1. If Bit 7 is set to "0", then Bit 1 (AIS-L Output Enable) within the "Receive STS-3 Transport - Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0x116B) will indictate whether or not pin AD11 is the "LOF" or the "AIS-L" output indicator. 2. If Bit 1 (AIS-L Output Enable) is set to "0", then pin AD11 will function as the LOF output indicator. 3. If Bit 1 (AIS-L Output Enable) is set to "1", then pin AD11 will function as the AIS-L output indicator. 0 1 0 1 Bit 6 (8kHz OUT Select) Role of LOF output pin LOF or AIS-L Indicator LOF or AIS-L Indicator Bit Stuff Indicator Output 8kHz Output 6 8kHz OUT Select R/W 8kHz OUT - LOF Output Pin: This READ/WRITE bit-field, along with Bit 6 (8kHz OUT Select) permits the user to define the role of the LOF output pin (pin AD11). The relationship between the states of these bit-fields and the corresponding role of the LOF output pin is presented below. Bit 7 (8kHz or STUFF Out Enable) 0 0 1 1 Bit 6 (8kHz OUT Select) 0 1 0 1 Role of LOF output pin LOF or AIS-L Indicator LOF or AIS-L Indicator Bit Stuff Indicator Output 8kHz Output 103 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 5 Egress Direct Monitored -STUFF Output R/W Egress Direction Monitored - STUFF Output: If the LOF output pin has been configured to function as a "STUFF Indicator" output, then it can be configured to reflect the current stuff opportunities of the channel designated by Bits 7 through 4 (Stuff Indicator Channel Select[3:0]) within the Operation Output Control Register - Byte 0. This READ/WRITE bit-field permits the user to configure the LOF output pin to either reflect the "current stuff opportunities" for the Ingress or Egress Path of the selected channel. 0 - Configures the LOF output pin to reflect the "current stuff opportunity" of the Ingress Path of the "selected" channel. 1 - Configures the LOF output pin to reflect the "current stuff opportunity" of the Egress Path of the "selected" channel. Note: 4-0 Unused R/O This bit-field will be ignored if the "selected" channel has been configured to operate in the STS-1 Mode. 20 0 Rev2...0...0 200 104 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 40: Operation Output Control Register - Byte 0 (Address Location= 0x0153) BIT 7 Unused R/O 0 R/O 0 BIT 6 BIT 5 BIT 4 BIT 3 Unused R/O 0 R/O 0 BIT 2 BIT 1 BIT 0 Stuff Indicator Channel Select[1:0] R/W 0 R/W 0 8kHz Source Channel Select[1:0] R/W 0 R/W 0 BIT NUMBER 7-6 5-4 NAME Unused Stuff Indicator Channel Select[1:0] TYPE R/O R/W DESCRIPTION Stuff Indicator - Channel Select[1:0]: These two (2) READ/WRITE bit-fields permit the user to identify which of the 3 channels should have their "bit-stuff opportunity" status reflected on the LOF output pin. Setting these bit-fields to [0, 0] configures the LOF output pin to reflect the bit-stuff opportunity status of Channel 0. Likewise, setting these bitfields to [1, 0] configures the LOF output pin to reflect the bit-stuff opportunity status of Channel 2. Note: These bit-fields are ignored if any of the following are true. 1. If the corresponding channel has been configured to operate in the STS-1 Mode. 2. If the LOF output pin has been configured to function as the LOF or AIS-L indicator output. 3. If the LOF output pin has been configured to function as an 8kHz output pin. 3-2 1-0 Unused 8kHz Source Channel Select[1:0] R/O R/W 8kHz Source Channel Select[1:0]: If the LOF output pin has been configured to output an 8kHz clock output signal, then the XRT94L33 will derive this 8kHz clock signal, from the Ingress DS3/E3 or Receive STS-1 signal of the "Selected" channel. These two(2) READ/WRITE bit-fields permit the user to specify the "Selected" channel. Setting these bit-fields to [0, 0] configures the LOF output pin to output an 8kHz clock signal, that is derived from the Ingress DS3/E3 or Receive STS-1 input signal of Channel 0. Likewise, setting these bitfields to [1, 0] configures the LOF output pin to reflect the bit-stuff opportunity status of Channel 2. Note: These bit-fields are ignored if any of the following are true. 1. If the LOF output pin has been configured to function as the LOF or AIS-L indicator output. 2. If the LOF output pin has been configured to function as the "Stuff Indicator" output pin. 105 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 41: Operation Slow Speed Port Control Register - Byte 1 (Address Location= 0x0154) BIT 7 SSI Enable R/W 0 BIT 6 SSI Insert R/W 0 BIT 5 SSI Force Zero R/W 0 BIT 4 Unused R/O 0 BIT 3 SSE Enable R/W 0 BIT 2 SSE Insert R/W 0 BIT 1 SSE Force Zero R/W 0 BIT 0 Unused R/O 0 20 0 Rev2...0...0 200 BIT NUMBER 7 NAME SSI Enable TYPE R/W DESCRIPTION Slow-Speed Ingress - Interface Port Enable: This READ/WRITE bit-field permits the user to enable or disable the SSI (Slow-Speed Ingress) Interface Port. If the SSI Interface port is enabled, then it can be used to either monitor (e.g., extract) or to replace (e.g., insert) a DS3, E3 or STS-1 signal, into the Ingress DS3/E3 or Receive STS-1 path of the "Selected" channel. 0 - Disables the SSI Interface Port. 1 - Enables the SSI Interface Port. 6 SSI Insert R/W Slow-Speed Ingress - Interface Port - Insert: This READ/WRITE bit-field permits the user to configure the SSI Interface port to either monitor (e.g., extract) an "Ingress DS3/E3" or "Receive STS-1" signal, or to replace (e.g., insert) a DS3, E3 or STS-1 signal into the Ingress DS3/E3 or Receive STS-1 path of the "Selected" channel. If the user configures the SSI Interface port to monitor a given DS3, E3 or STS-1 signal, then the SSI Interface will then be configured to be an "output" interface. In this case, the SSI Interface port will consist of an "SSI_POS", "SSI_NEG" and "SSI_CLK" output signals. Additionally, a copy of the Ingress DS3/E3 or Receive STS-1 signal will be output via this output port. If the user configures the SSI Interface port to replace (e.g., insert) an "Ingress DS3/E3" or Receive STS-1 signal, then the SSI Interface will then be configured to be an "input" interface. In this case, the SSI Interface port will consist of an "SSI_POS", "SSI_NEG" and "SSI_CLK" input signals. Additionally, the DS3, E3 or STS-1 signal, that is applied at this input port will overwrite that of the "Ingress DS3/E3" or the Receive STS-1 signal. 0 - Configures the SSI Interface as an output port that will permit the user to monitor the "selected" Ingress DS3/E3 or Receive STS-1 signal. 1 - Configures the SSI Interface as an input port. In this configuration, the DS3, E3 or STS-1 signal that is input via this port will replace/overwrite the "Ingress" DS3/E3 or Receive STS-1 signal, within the "selected" channel, prior to being mapped into STS-3. Note: This bit-field will be ignored if the SSI Interface port is disabled. 5 SSI Force Zero R/W Slow Speed Ingress - Interface Port - Force to All Zeros: This READ/WRITE bit-field permits the user to force the Ingress DS3/E3 or Receive STS-1 signal, within the "selected" channel to an "All Zeros" pattern. 0 - Configures the Ingress DS3/E3 or Receive STS-1 signal (within the "selected" channel) to flow to the DS3/E3 Mapper Block or to the Transmit SONET POH Processor block, in a normal manner. 1 - Forces the data, within the Ingress DS3/E3 or Receive STS-1 signal (within the "selected" channel) to an "All Zeros" pattern. 106 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Note: This bit-field will be ignored if the SSI Interface port is disabled. 4 3 Unused SSE Enable R/O R/W Slow-Speed Egress - Interface Port Enable: This READ/WRITE bit-field permits the user to enable or disable the SSE (Slow Speed Egress) Interface Port. If the SSE Interface port is enabled, then it can be used to either monitor (e.g., extract) or to replace (e.g., insert) a DS3, E3 or STS-1 signal, into the Egress DS3/E3 or Transmit STS-1 path of the "Selected" channel. 0 - Disables the SSE Interface Port 1 - Enables the SSE Interface Port. 2 SSE Insert R/W Slow Speed Egress - Interface Port - Insert: This READ/WRITE bit-field permits the user to configure the SSE Interface port to either monitor (e.g., extract) an "Egress DS3/E3" or "Receive STS-1" signal, or to replace (e.g., insert) a DS3, E3 or STS-1 signal into the Egress DS3/E3 or Transmit STS-1 path of the "Selected" channel. If the user configures the SSE Interface port to monitor a given DS3, E3 or STS-1 signal, then the SSE Interface wil then be configured to be an "output" interface. In this case, the SSE Interface port will consist of an "SSE_POS", "SSE_NEG" and "SSE_CLK" output signals. Additionally, a copy of the Egress DS3/E3 or Transmit STS-1 signal will be output via this output port. If the user configures the SSE Interface port to replace (e.g., insert) an "Egress DS3/E3" or Transmit STS-1 signal, then the SSE Interface will then be configured to be an "input" interface. In this case, the SSE Interface port will consist of an "SSE_POS", "SSE_NEG" and "SSE_CLK" input signals. Additionally, the DS3, E3 or STS-1 signal, that is applied at this input port will overwrite that of the "Egress DS3/E3" or the Transmit STS-1 signal. 0 - Configures the SSE Interface as an output port that will permit the user to monitor the "selected" Egress DS3/E3 or Transmit STS-1 signal.. 1 - Configures the SSE Interface as an input port. In this configuration, the DS3, E3 or STS-1 signal, that is input via this port will replace/overwrite the "Egress" DS3/E3 or Transmit STS-1 signal, within the "selected" channel, prior to being mapped into STS-3. Note: This bit-field will be ignored if the SSE Interface port is disabled. 1 SSE Force Zero R/W Slow Speed Egress - Interface Port - Force to All Zeros: This READ/WRITE bit-field permits the user to force the Egress DS3/E3 or Transmit STS-1 signal, within the "selected" channel to an "All Zeros" pattern. 0 - Configures the Egress DS3/E3 or Transmit STS-1 signal (within the "selected" channel) to flow to the DS3/E3/STS-1 LIU IC in a normal manner. 1 - Forces the data, within the Egress DS3/E3 or Transmit STS-1 signal (within the "selected" channel) to an "All Zeros" pattern. Note: This bit-field will be ignored if the SSE Interface port is disabled. 0 Unused R/O 107 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 42: Operation Slow Speed Port Control Register - Byte 0 (Address Location= 0x0157) BIT 7 Unused R/O 0 R/O 0 BIT 6 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 Unused R/O 0 R/O 0 BIT 2 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 SSI_Channel_Select[1:0] SSE_Channel_Select[1:0] BIT NUMBER 7-6 5-4 NAME Unused SSI_Channel_Select[ 1:0]: TYPE R/O R/W DESCRIPTION Slow-Speed Ingress - Interface Port - Channel Select[1:0]: These READ/WRITE bit-fields permit the user to select which of the 3 Ingress DS3/E3 or Receive STS-1 signals will be processed via the SSI Interface port. Setting SSI_Channel_Select[1:0] to [0, 0] configures the SSI Interface port to process the Ingress DS3/E3 or Receive STS-1 signal associated with Channel 0. Likewise, setting SSI_Channel_Select[1:0] to [1, 0] configures the SSI Interface port to process the Ingress DS3/E3 or Receive STS-1 signal associated with Channel 2. Note: These bit-fields are ignored if the SSI Interface port is disabled. 3 -2 1-0 Unused SSE_Channel_Select [1:0] R/O R/W Slow Speed Egress - Interface Port - Channel Select[1:0]: These READ/WRITE bit-fields permit the user to select which of the 3 Egress DS3/E3 or Receive STS-1 signals will be processed via the SSE Interface port. Setting SSE_Channel_Select[1:0] to [0, 0] configures the SSE Interface port to process the Egress DS3/E3 or Transmit STS-1 signal associated with Channel 0. Likewise, setting SSE_Channel_Select[1:0] to [1, 0] configures the SSE Interface port to process the Egress DS3/E3 or Transmit STS-1 signal associated with Channel 2. Note: These bit-fields are ignored if the SSE Interface port is disab led. 108 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 43: Operation - DS3/E3/STS-1 Clock Frequency Out of Range Detection - Direction Register (Address Location= 0x0158) BIT 7 BIT 6 BIT 5 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 ON_EGRESS DIRECTION R/W 0 BIT NUMBER 7-1 0 NAME Unused ON_EGRESS_DIRECTION TYPE R/O R/W DESCRIPTION Frequency Out of Range Detection on Egress Direction: This READ/WRITE bit-field permits the user to configure the "DS3/E3/STS-1 Clock Frequency - Out of Range Detector" to operate in either the Ingress or Egress direction. 0 - Configures the DS3/E3/STS-1 Clock Frequency - Out of Range Detector" to operate on the DS3, E3 or STS-1 clock signals in the Ingress Direction. 1 - Configures the DS3/E3/STS-1 Clock Frequency - Out of Range Detector" to operate on the DS3, E3 or STS-1 clock signals in the Egress Direction. Table 44: Operation - DS3/E3/STS-1Clock Frequency - DS3 Out of Range Detection Threshold Register (Address Location= 0x015A) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 DS3_OUT_OF_RANGE_DETECTION_THRESHOLD[7:0] BIT NUMBER 7-0 NAME DS3_OUT_OF_RANGE_ DETECTION_THR TYPE R/W DESCRIPTION DS3 Out of Range - Detection Threshold[7:0]: These eight READ/WRITE bit-fields permit the user to define (in terms of ppm) the frequency difference that must exist between a given DS3 signal (in either the Ingress or Egress direction) and that of the REFCLK45 input clock signal; before the XRT94L33 will declare a "DS3 Clock Frequency - Out of Range" condition. 109 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 45: Operation - DS3/E3/STS-1Clock Frequency - STS-1/E3 Out of Range Detection Threshold Registers (Address Location= 0x015B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 STS-1/E3_OUT_OF_RANGE_DETECTION_THRESHOLD[7:0] BIT NUMBER 7-0 NAME STS1/E3_OUT_OF_RAN GE_DETECTION_THR TYPE R/W DESCRIPTION STS-1/E3 Out of Range - Detection Threshold[7:0]: These eight READ/WRITE bit-fields permit the user to define (in terms of ppm) the frequency difference that must exist between a given STS-1 or E3 signal (in either the Ingress or Egress direction) and that of the REFCLK51/REFCLK34 input clock signal; before the XRT94L33 will declare a "STS-1/E3 Clock Frequency - Out of Range" condition. Table 46: Operation - DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register - Byte 0 (Address Location=0x015D) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Out of Range - Channel 2 Interrupt enable R/O 0 TYPE R/O R/W DS3/E3/STS-1 Frequency - Out of Range - Channel 2 - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 2. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the DS3, E3 or STS-1 signal (in the selected direction - Ingress or Egress) within Channel 2, differs from its corresponding Reference Clock signal (e.g., REFCLK45, REFCLK34 or REFCLK51) by its "Out of Range Detection Threshold" (in terms of ppm) or more. 0 - Disables the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 2. 1 - Enables the "DS3/E3/STS-1 Frequency Interrupt for Channel 2. 1 Out of Range - Channel 1 Interrupt Enable R/W - Out of Range" R/O 0 R/W 0 BIT 1 Out of Range - Channel 1 Interrupt Enable R/W 0 DESCRIPTION BIT 0 Out of Range - Channel 0 Interrupt Enable R/W 0 R/O 0 BIT NUMBER 7-3 2 R/O 0 NAME R/O 0 Unused Out of Range - Channel 2 Interrupt Enable DS3/E3/STS-1 Frequency - Out of Range - Channel 1 - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt 110 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS for Channel 1. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the DS3, E3 or STS-1 signal (in the selected direction - Ingress or Egress) within Channel 1, differs from its corresponding Reference Clock signal (e.g., REFCLK45, REFCLK34 or REFCLK51) by its "Out of Range Detection Threshold" (in terms of ppm) or more. 0 - Disables the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 1. 1 - Enables the "DS3/E3/STS-1 Frequency Interrupt for Channel 1. - Out of Range" 0 Out of Range - Channel 0 Interrupt Enable R/W DS3/E3/STS-1 Frequency - Out of Range - Channel 0 - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 0. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the DS3, E3 or STS-1 signal (in the selected direction - Ingress or Egress) within Channel 0, differs from its corresponding Reference Clock signal (e.g., REFCLK45, REFCLK34 or REFCLK51) by its "Out of Range Detection Threshold" (in terms of ppm) or more. 0 - Disables the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 0. 1 - Enables the "DS3/E3/STS-1 Frequency Interrupt for Channel 0. - Out of Range" 111 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 47: Operation - DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register - Byte 0 (Address Location=0x015F) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Out of Range - Channel 2 Interrupt Status R/O 0 TYPE R/O RUR DS3/E3/STS-1 Frequency - Out of Range - Channel 2 - Interrupt Status: This RESET-Upon-READ bit-field indicates whether or not the XRT94L33 has declares the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 2, since the last read of this register. 0 - Indicates that the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 2 has NOT occurred since the last read of this register. 1 - Indicates that the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 2 has occurred since the last read of this register. 1 Out of Range - Channel 1 Interrupt Status RUR DS3/E3/STS-1 Frequency - Out of Range - Channel 1 - Interrupt Status: This RESET-Upon-READ bit-field indicates whether or not the XRT94L33 has declares the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 1, since the last read of this register. 0 - Indicates that the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 1 has NOT occurred since the last read of this register. 1 - Indicates that the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 1 has occurred since the last read of this register. 0 Out of Range - Channel 0 Interrupt Status RUR DS3/E3/STS-1 Frequency - Out of Range - Channel 0 - Interrupt Status: This RESET-Upon-READ bit-field indicates whether or not the XRT94L33 has declares the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 0, since the last read of this register. 0 - Indicates that the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 0 has NOT occurred since the last read of this register. 1 - Indicates that the "DS3/E3/STS-1 Frequency - Out of Range" Interrupt for Channel 0 has occurred since the last read of this register. R/O 0 RUR 0 DESCRIPTION BIT 1 Out of Range - Channel 1 Interrupt Status RUR 0 BIT 0 Out of Range - Channel 0 Interrupt Status RUR 0 R/O 0 BIT NUMBER 7-3 2 R/O 0 NAME Unused R/O 0 Out of Range - Channel 2 Interrupt Status 112 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 48: APS Mapping Register (Address Location= 0x0180) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Protection Channel Protected Channel BIT NUMBER 7-4 3-0 NAME Protection Channel Protected Channel TYPE R/W R/W Protection Channel: Protected Channel: DESCRIPTION Table 49: APS Control Register - 1:1 & 1:N Protection Map (Address Location= 0x0181) BIT 7 Group Enable R/W 0 BIT 6 APS Type BIT 5 Timing BIT 4 Receive Payload Bypass R/W 0 BIT 3 Group Reset R/W 0 BIT 2 Line Port In Use R/O 0 BIT 1 APS Auto Switch Enable R/W 0 BIT 0 APS Auto Switch R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME Group Enable TYPE R/W Group Enable: DESCRIPTION This READ/WRITE bit-field permits the user to enable the APS for this group. 1 - Enables the APS for this group 2 - Disables the APS for this group 6 APS Type R/W APS Type: This READ/WRITE bit-field permits the user to determine the type of APS for this group. 0 - Configures the type of APS to be 1+1 1 - Configures the type of APS to be 1:N 5 Timing R/W Timing: This READ/WRITE bit-field permits the user to specify whether the protection or the protected channel should dominate the timing of transmit APS. 0 - Protected channel dominates the timing 1 - Protection Channel dominates the timing 4 Receive Payload Bypass R/W Receive Payload Bypass: This READ/WRITE bit-field permits the user to bypass the receive payload of protection channel. 0 - Receive payload is not bypassed. 1 - Receive payload is bypassed. 113 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 3 Group Reset R/W Group Reset: This READ/WRITE bit-field permits the user to reset the APS control and FIFO. A "0" to "1" transition will cause the APS control and FIFO to be reset. 2 Line Port In Use R/O Line Port In Use: This READ-ONLY bit-field permits the user to check the current line port being in used for receiving OC3 data. 0 - Port 0 (main port) is the current line port in used 1 - Port 1 (backup port) is the current line port in used 1 APS Auto Switch Enable R/W APS Auto Switch Enable: This READ/WRITE bit-field permits the user to configure the XRT94L33 to automatically switch from the "Primary" to the "Redundant" port, whenever the Receive STS-3 TOH Processor block declares an LOS (Loss of Signal) condition. 0 - Disables the APS Auto Switch feature. In this mode, the XRT94L33 will not automatically switch from the "Primary" port to the "Redundant" port, whenever the Receive STS-3 TOH Processor block declares an LOS condition. 1 - Enables the APS Auto Switch feature 0 APS Switch R/W APS Switch: This READ/WRITE bit-field permits the user to command an APS switch (from one port to the other) via software control. 0 - Configures the Receive STS-3 TOH Processor block to use the "Primary Receive" Port. 1 - Configures the Receive STS-3 TOH Processor block to use the "Redundant Receive" Port. 20 0 Rev2...0...0 200 114 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 50: APS Status Register (Address Location= 0x0194) BIT 7 BIT 6 BIT 5 Receive APS Parity Enable R/W 0 BIT 4 Receive APS Parity Type R/W 0 BIT 3 Transmit APS Parity Enable R/W 0 BIT 2 Transmit APS Parity Type R/W 0 BIT 1 Transmit APS Parity Error R/O 0 BIT 0 Receive APS Parity Error R/O 0 Unused R/O 0 R/O 0 BIT NUMBER 7-6 5 NAME Unused Receive APS Parity Enable TYPE R/O R/W Receive APS Parity Enable: DESCRIPTION This READ/WRITE bit-field permits the user to enable receive APS parity check. 0 - Disables receive APS parity check 1 - Enables receive APS parity check 4 Receive APS Parity Type R/W Receive APS Parity Type: This READ/WRITE bit-field permits the user to specify the type of parity used for receive APS. 0 - Even parity is used 1 - Odd parity is used 3 Transmit APS Parity Enable R/W Transmit APS Parity Enable: This READ/WRITE bit-field permits the user to enable transmit APS parity check 0 - Disables transmit APS parity check 1 - Enables transmit APS parity check 2 Transmit APS Parity Type R/W Transmit APS Parity Type: This READ/WRITE bit-field permits the user to specify the type of parity used for transmit APS. 0 - Even parity is used 1 - Odd parity is used 1 Transmit APS Parity Error R/O Transmit APS Parity Error: This READ-ONLY bit-field permits the user to check the parity error status in transmit APS module 0 - Indicates "NO" parity error occurs 1 - Indicates parity error occurs 0 Receive APS Parity Error R/O Receive APS Parity Error: This READ-ONLY bit-field permits the user to check the parity error status in receive APS module 0 - Indicates "NO" parity error occurs 1 - Indicates parity error occurs Table 51: APS Status Register (Address Location= 0x0196) 115 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 20 0 Rev2...0...0 200 BIT 0 R/O 0 Group Overflow Status [7:0] BIT NUMBER 7-0 NAME Group Overflow Status TYPE R/O Group Overflow Status: DESCRIPTION This READ/WRITE bit-field indicates whether or not a FIFO overflow has occurred in group n 1+1 APS protection channel. 0 - Indicates "NO" FIFO overflow 1 - Indicates a FIFO overflow Table 52: APS Status Register (Address Location= 0x0197) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Group Underflow Status [7:0] BIT NUMBER 7-0 NAME Group Underflow Status TYPE R/O Group Underflow Status: DESCRIPTION This READ/WRITE bit-field indicates whether or not a FIFO underflow has occurred in group n 1+1 APS protection channel. 0 - Indicates "NO" FIFO underflow 1 - Indicates a FIFO underflow 116 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 53: APS Interrupt Register (Address Location= 0x0198) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Transmit APS Parity Error Interrupt Status R/O 0 R/O 0 R/O 0 RUR 0 BIT 0 Receive APS Parity Error Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Transmit APS Parity Error Interrupt Status TYPE R/O RUR DESCRIPTION Transmit APS Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the transmit APS module has declared a "Transmit APS Parity Error" Interrupt since the last read of this register. 0 - The "Transmit APS Parity Error" Interrupt has not occurred since the last read of this register. 1 - The "Transmit APS Parity Error" Interrupt has occurred since the last read of this register. 7-0 Receive APS Parity Error Interrupt Status RUR Receive APS Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the receive APS module has declared a "Receive APS Parity Error" Interrupt since the last read of this register. 0 - The "Receive APS Parity Error" Interrupt has not occurred since the last read of this register. 1 - The "Receive APS Parity Error" Interrupt has occurred since the last read of this register 117 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 54: APS Interrupt Register (Address Location= 0x019A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 20 0 Rev2...0...0 200 Group Overflow Interrupt Status BIT NUMBER 7-0 NAME Group Overflow Interrupt Status TYPE RUR DESCRIPTION Group Overflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not group n (0-7) APS protection channel has declared a "FIFO overflow" Interrupt since the last read of this register. 0 - The "FIFO overflow" Interrupt has not occurred since the last read of this register. 1 - The "FIFO overflow" Interrupt has occurred since the last read of this register. Table 55: APS Interrupt Register (Address Location= 0x019B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 Group Underflow Interrupt Status BIT NUMBER 7-0 NAME Group Underflow Interrupt Status TYPE RUR DESCRIPTION Group Underflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not group n (07) APS protection channel has declared a "FIFO underflow" Interrupt since the last read of this register. 0 - The "FIFO underflow" Interrupt has not occurred since the last read of this register. 1 - The "FIFO underflow" Interrupt has occurred since the last read of this register. 118 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 56: APS Interrupt Enable Register (Address Location= 0x019C) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Transmit APS Parity Error Interrupt Enable R/O 0 R/O 0 R/O 0 R/W 0 BIT 0 Receive APS Parity Error Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Transmit APS Parity Error Interrupt Enable TYPE R/O R/W DESCRIPTION Transmit APS Parity Error Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "Transmit APS Parity Error" Interrupt in Transmit APS module 0 - Disables the "Transmit APS Parity Error" Interrupt 1 - Enables the "Transmit APS Parity Error" Interrupt 7-0 Receive APS Parity Error Interrupt Enable R/W Receive APS Parity Error Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "Receive APS Parity Error" Interrupt in Receive APS module 0 - Disables the "Receive APS Parity Error" Interrupt 1 - Enables the "Receive APS Parity Error" Interrupt Table 57: APS Interrupt Enable Register (Address Location= 0x019E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Group Overflow Interrupt Enable BIT NUMBER 7-0 NAME Group Overflow Interrupt Enable TYPE R/W DESCRIPTION Group Overflow Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "FIFO overflow" interrupt in group n APS protection channel. 0 - Disables "FIFO overflow" interrupt . 1 - Enables "FIFO overflow" Interrupt 119 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 58: APS Interrupt Enable Register (Address Location= 0x019F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 Group Underflow Interrupt Enable BIT NUMBER 7-0 NAME Group Underflow Interrupt Enable TYPE R/W DESCRIPTION Group Underflow Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "FIFO underflow" interrupt in group n APS protection channel. 0 - Disables "FIFO underflow" interrupt . 1 - Enables "FIFO underflow" Interrupt 120 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS LINE INTERFACE CONTROL BLOCK LINE INTERFACE CONTROL REGISTER 1.3 1.3.1 Table 59: Line Interface Control Register - Address Map INDIVIDUAL REGISTER ADDRESS 0x02 0x03 0x04 - 0x06 0x07 0x08 -0x0A 0x0B 0x0C - 0x0E 0x0F 0x10 - 0x82 0x83 ADDRESS LOCATION 0x0302 0x0303 0x0304 - 0x0306 0x0307 0x0308 -0x030A 0x030B 0x030C - 0x030E 0x030F 0x0310 - 0x0382 0x0383 REGISTER NAME Receive Line Interface Control Register - Byte 1 Receive Line Interface Control Register - Byte 0 Reserved Receive Line Status Register Reserved Receive Line Interrupt Register Reserved Receive Line Interrupt Enable Register Reserved Transmit Line Interface Control Register DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 121 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.3.2 LINE INTERFACE CONTROL REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 60: Receive Line Interface Control Register - Byte 1 (Address Location= 0x0302) BIT 7 Unused BIT 6 Loop-timing Mode R/W 0 BIT 5 Split Loop Back R/W 0 BIT 4 Unused BIT 3 Remote Serial Loop Back R/W 0 BIT 2 Unused BIT 1 Analog Local Loop Back Enable R/W 0 BIT 0 Digital Local Loop Back Enable R/W 0 R/W 0 R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused Loop Timing Mode TYPE R/O R/W Loop-Timing Mode: DESCRIPTION This READ/WRITE bit-field permits the user to configure the 94L33 to operate in the Loop-timing Mode. If the user implements this configuration, then the Transmit Line Interface Block will use the Recovered Clock as its timing source. 0 - Configures the Transmit Line Interface Block to use "Local-Timing" Mode (e.g., the timing source is from the Clock Synthesizer block). 1 - Configures the Transmit Line Interface Block to operate in the "LoopTiming" Mode. 5 Split Loop Back R/W Split Loop-back Enable: This READ/WRITE bit-field permits the user to configure the 94L33 to operate in the "Split Loop-back" Mode. If the user implements this configuration, then two types of loop-backs will exist within the chip simultaneously. a. A Local Loop-back This loop-back path will originate from the Transmit STS-3 TOH Processor block. It will be routed through a portion of the "Transceiver circuitry" (through the "Transmit Parallel-to-Serial Converter" block) and then back to the "Receive Serial-to-Parallel Converter" block, before being routed to the Receive STS-3 TOH Processor block. b. A Remote Loop-back This loop-back path will originate from the Receive STS-3/STM-1 PECL Interface input. It will be routed through the CDR (Clock & Data Recovery) block; before being routed to the Transmit STS-3/STM-1 PECL Interface output. 0 - Configures the 94L33 to disable split loop back 1 - Configures the 94L33 to enable split loop back 4 3 Unused Remote Serial Loop Back R/W Remote Serial Loop-back Enable: This READ/WRITE bit-field permits the user to configure the 94L33 to operate in the "Remote Serial Loop-back" Mode. In this mode, the incoming (Received Data) will enter the device via the Receive STS3/STM-1 PECL Interface Input. This signal will then be processed via the CDR (Clock and Data Recovery) Block. At this point, this input signal will proceed via two paths in parallel. In one path, the signal will proceed onto the "Receive Serial-to-Parallel" Converter and then the Receive STS-3 122 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TOH Processor block (and so on). The other path will not proceed through the "Receive Serial-to Parallel" Converter block. Instead this signal will proceed on towards the "Transmit STS-3/STM-1 PECL Interface Output, thereby completing the loop-back path. 0 - Configures the 94L33 to NOT operate in the Remote Serial Loop-back Mode. 1 - Configures the 94L33 to operate in the Remote Serial Loop-back Mode. 2 1 Unused Analog Local Loop Back Enable R/O R/W Analog Local Loop Back: This READ/WRITE bit field permits the user to configure the 94L33 to operate in the "Analog Local Loop Back" Mode. If the user implements this configuration, analog local loop back including data and clock recovery will be enabled. 0 - Analog local loop back is disabled 1 - Analog local loop back is enabled 0 Digital Local Loop Back Enable R/W Digital Local Loop Back: This READ/WRITE bit field permits the user to configure the 94L33 to operate in the "Digital Local Loop Back" Mode. If the user implements this configuration, digital local loop back NOT including data and clock recovery will be enabled. 0 - Digital local loop back is disabled 1 - Digital local loop back is enabled 123 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 61: Receive Line Interface Control Register - Byte 0 Address Location= 0x0303) BIT 7 Receive Line Interface Module Power Down R/W 0 BIT 6 Redundant Receive Line Interface Module Power Down R/W 0 BIT 5 Force Training Mode Upon LOS BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 20 0 Rev2...0...0 200 R/W 0 R/O 0 R/O 0 R/O 0 R/O 0 R/W 0 BIT NUMBER 7 NAME Receive Line Interface Module Power Down TYPE R/W DESCRIPTION Receive Line Interface Module Power Down: This READ/WRITE bit field permits the user to power down receive line interface module 0 - Turn on receive line interface module 1 - Power down receive line interface module 6 Redundant Receive Line Interface Module Power Down R/W Redudant Receive Line Interface Module Power Down: This READ/WRITE bit field permits the user to power down redundant receive line interface module 0 - Turn on redundant receive line interface module 1 - Power down redundant receive line interface module 5 Force Training Mode Upon LOS R/W Force Training Mode Upon LOS: This READ/WRITE bit field permits the receive line interface phase lock loop to stay in training mode as long as the external LOS is asserted. 0 - Receive Line Interface PLL will NOT stay in training mode 1 - Receive Line Interface PLL will stay in training mode 4-0 Unused R/O 124 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 62: Receive Line Interface Status Register (Address Location= 0x0307) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Clock Lock Status R/O 0 R/O 0 RUR 0 BIT 2 Loss of Signal Status RUR 0 BIT 1 Redundant Receiver Clock Lock Status RUR 0 BIT 0 Redundant Receiver Loss of Signal Status RUR 0 Unused R/W 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused Clock Lock Status TYPE R/O RUR Clock Lock Status: DESCRIPTION This RESET-upon-READ bit field indicates whether or not the clock lock status is detected by transceiver 0 - Indicates clock lock is NOT detected by transceiver 1 - Indicates clock lock is detected by transceiver 2 Loss of Signal Status RUR Loss of Signal Status: This RESET-upon-READ bit field indicates whether or not the loss of signal status is detected by transceiver 0 - Indicates loss of signal is NOT detected by transceiver 1 - Indicates loss of signal is detected by transceiver 1 Redundant Receiver Clock Lock Status RUR Redundant Receiver Clock Lock Status: This RESET-upon-READ bit field indicates whether or not the clock lock status is detected by redundant receiver 0 - Indicates clock lock is NOT detected by redundant receiver 1 - Indicates clock lock is detected by redundant receiver 0 Redundant Receiver Loss of Signal Status RUR Redundant Receiver Loss of Signal Status: This RESET-upon-READ bit field indicates whether or not the loss of signal status is detected by redundant receiver 0 - Indicates loss of signal is NOT detected by redundant receiver 1 - Indicates loss of signal is detected by redundant receiver 125 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 63: Receive Line Interface Interrupt Register (Address Location= 0x030B) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Clock Lock Interrupt BIT 2 Loss of Signal Interrupt BIT 1 Redundant Receiver Clock Lock Interrupt RUR 0 BIT 0 Redundant Receiver Loss of Signal Interrupt RUR 0 20 0 Rev2...0...0 200 R/W 0 R/O 0 R/O 0 R/O 0 RUR 0 RUR 0 BIT NUMBER 7-4 3 NAME Unused Clock Lock Interrupt TYPE R/O RUR Clock Lock Interrupt: DESCRIPTION This RESET-upon-READ bit field indicates whether or not a clock lock interrupt has occurred. A clock lock interrupt occurs when the signal "Clock Lock Status" (address location: 0x0307) makes a "0" to "1" or "1" to "0" transition. 0 - Indicates clock lock interrupt is NOT declared. 1 - Indicates clock lock is declared 2 Loss of Signal Interrupt RUR Loss of Signal Interrupt: This RESET-upon-READ bit field indicates whether or not a loss of signal interrupt has occurred. A clock lock interrupt occurs when the signal "Loss of Signal Status" (Address Location: 0x0307) makes a "0" to "1" or "1" to "0" transition. 0 - Indicates a loss of signal interrupt is NOT declared. 1 - Indicates a loss of signal is declared 1 Redundant Receiver Clock Lock Interrupt RUR Redundant Receiver Clock Lock Interrupt: This RESET-upon-READ bit field indicates whether or not a clock lock interrupt has occurred in the redundant receiver block. A clock lock interrupt occurs when the signal "Clock Lock Status" (address location: 0x0307) makes a "0" to "1" or "1" to "0" transition. 0 - Indicates clock lock interrupt is NOT declared. 1 - Indicates clock lock is declared 0 Redundant Receiver Loss of Signal Interrupt RUR Redundant Receiver Loss of Signal Interrupt: This RESET-upon-READ bit field indicates whether or not a loss of signal interrupt has occurred in the redundant receiver block. A clock lock interrupt occurs when the signal "Loss of Signal Status" (Address Location: 0x0307) makes a "0" to "1" or "1" to "0" transition. 0 - Indicates a loss of signal interrupt is NOT declared. 1 - Indicates a loss of signal is declared 126 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 64: Receive Line Interface Interrupt Register (Address Location= 0x030F) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Clock Lock Interrupt Enable BIT 2 Loss of Signal Interrupt Enable BIT 1 Redundant Receiver Clock Lock Interrupt Enable R/W 0 BIT 0 Redundant Receiver Loss of Signal Interrupt Enable R/W 0 R/W 0 R/O 0 R/O 0 R/O 0 R/W 0 R/W 0 BIT NUMBER NAME TYPE DESCRIPTION 7-4 3 Unused Clock Lock Interrupt Enable R/O R/W Clock Lock Interrupt Enable: This READ/WRITE bit field disables or enables the clock lock interrupt. 0 - Disables clock lock interrupt 1 - Enables clock lock interrupt 2 Loss of Signal Interrupt R/W Loss of Signal Interrupt Enable: This READ/WRITE bit field disables or enables the loss of signal interrupt. 0 - Disables loss of signal interrupt 1 - Enables loss of signal interrupt 1 Redundant Receiver Clock Lock Interrupt Enable R/W Redundant Receiver Clock Lock Interrupt Enable: This READ/WRITE bit field disables or enables the clock lock interrupt for the redundant receiver block. 0 - Disables clock lock interrupt 1 - Enables clock lock interrupt 0 Redundant Receiver Loss of Signal Interrupt R/W Redundant Receiver Loss of Signal Interrupt Enable: This READ/WRITE bit field disables or enables the loss of signal interrupt for the redundant receiver block. 0 - Disables loss of signal interrupt 1 - Enables loss of signal interrupt 127 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 65: Transmit Line Interface Control Register (Address Location= 0x0383) BIT 7 Transmit Line Interface Module Power Down R/W 0 BIT 6 Transmit Clock Enable BIT 5 Clock Synthesizer BIT 4 Redundant Enable BIT 3 Unused BIT 2 Unused BIT 1 BIT 0 20 0 Rev2...0...0 200 Reference Clock Divide R/W 0 R/W 0 R/W 0 R/O 0 R/O 0 R/W 0 R/W 0 BIT NUMBER 7 NAME Transmit Line Interface Module Power Down TYPE R/W DESCRIPTION Transmit Line Interface Module Power Down: This READ/WRITE bit field permits the user to enable or disable both transmitter data and clock outputs in the transmit line interface module. 0 - Disables both transmitter data and clock outputs in transmit line interface 1 - Enables both transmitter data and clock outputs in transmit line interface 6 Transmit Clock Enable R/W Transmit Clock Enable: This READ/WRITE bit field permits the user to enable or disable the transmitter clock output. 0 - Disables transmitter clock output 1 - Enables transmitter clock output 5 Clock Synthesizer R/W Clock Synthesizer: This READ/WRITE bit field permits the user to determine the source of transmit SONET clock. 0 - Uses reference clock as SONET transmit clock 1 - Uses 19MHz generated by clock synthesizer as SONET transmit clock 4 Redundant Enable R/W Redundant Enable: This READ/WRITE bit field permits the user to enable or disable the redundant transmit output pads 0 - Disables redundant transmit output 1 - Enables redundant transmit output 3 Unused R/W Serial Loopback: This READ/WRITE bit field permits the user to enable or disable serial loopback. 0 - Disables Serial loopback 1 - Enables Serial loopback 2 1-0 Unused Reference Clock Divide R/O R/W Reference Clock Divide: This READ/WRITE bit field permits the user to select the desired reference clock speed as follows: 00 = 19.44 MHz 128 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 01 = 38.88 MHz 10 = 51.85 MHz 11 = 77.76 MHz 129 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.4 RECEIVE/TRANSMIT UTOPIA INTERFACE BLOCK 20 0 Rev2...0...0 200 The register map for the Receive/Transmit Utopia Interface Block is presented in the Table below. Additionally, a detailed description of each of the "Receive/Transmit UTOPIA Interface" Block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "Receive and Transmit UTOPIA Interface Blocks "highlighted" is presented below in Figure 6 Figure 5: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive/Transmit UTOPIA Interface Blocks "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 130 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RECEIVE/TRANSMIT UTOPIA INTERFACE BLOCK REGISTER 1.4.1 Table 66: Receive/Transmit UTOPIA Interface Block Register - Address Map RECEIVE/TRANSMIT UTOPIA INTERFACE REGISTERS 0x0384 - 0x0502 0x0503 0x0504 - 0x0512 0x0513 0x0514 - 0x0516 0x0517 0x0518 - 0x0582 0x0583 0x0584 - 0x0592 0x0593 0x0594 - 0x0596 0x0597 0x0598 - 0x1102 Reserved Receive UTOPIA Control Register - Byte 0 Reserved Receive UTOPIA Port Address Reserved Receive UTOPIA Port Number Reserved Transmit UTOPIA Control Register - Byte 0 Reserved Transmit UTOPIA Port Address Reserved Transmit UTOPIA Port Number Reserved 0x00 0x8F 0x00 0x00 0x00 0x00 0x00 0x8F 0x00 0x00 0x00 0x00 0x00 131 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.4.2 RECEIVE UTOPIA INTERFACE BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 67: Receive UTOPIA/POS-PHY Control Register - Byte 0 (Address = 0x0503) BIT 7 UTOPIA Level Select BIT 6 Multi-PHY Polling Enable R/W 0 BIT 5 Back to Back Polling Enable R/W 0 BIT 4 Direct Status Indication Enable R/W 0 BIT 3 BIT 2 BIT 1 BIT 0 UTOPIA/POS-PHY Data Bus Width Cell Size[1:0] R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 BIT NUMBER 7 NAME UTOPIA Level Select TYPE R/W UTOPIA Level Select: DESCRIPTION This READ/WRITE bit-field permits the user to select either UTOPIA level 3, UTOPIA level 2, or UTOPIA level 1 standard to be used. If the user selects UTOPIA level 3 to be used, the UTOPIA interface will support cell-level handshakes compliant to the UTOPIA level 3 standard. If the user selects UTOPIA level 2 or 1, then the UTOPIA interface will support cell-level handshakes compliant to both UTOPIA level 2 and 1 standards. 0 - Configures the Receive UTOPIA interface block to use UTOPIA Level 1 or 2 standards 1 - Configures the Receive UTOPIA interface block to use UTOPIA Level 3 standard. 6 Multi-PHY Polling Enable R/W Multi-PHY Polling Enable: This READ/WRITE bit-field permits the user to either enable or disable Multi-PHY Polling for the Receive UTOPIA Interface block. If the user implements this feature (and configures the XRT94L33 to operate in the Multi-PHY Mode) then the RxUClav output pin will be driven (either "high" or "low") based upon the fill-status of the Receive FIFO within the Channel that corresponds to the "Receive UTOPIA Address" that is currently being applied to the "RxUAddr[4:0]" input pins. If the user does not implement this feature (and then configures the XRT94L33 to operate in the Single-PHY Mode), then the "RxUClav" output pin will unconditionally reflect the "Receive FIFO fill-status" for Channel 0. No attention will be paid to the address values placed upon the "RxUAddr[4:0]" input pins. 0 - Configures the Receive UTOPIA Interface block to operate in the Single-PHY Mode. 1 - Configures the Receive UTOPIA Interface block to operate in the Multi-PHY Mode. 5 Back-to-Back Polling Enable R/W Back-to-Back Polling Enable: This READ/WRITE bit-field permits the user to configure the Receive UTOPIA Interface block to support "Back-to-Back Polling". Ordinarily, for Multi-PHY polling, the user is required to interleave all UTOPIA Address values (that are to be placed 132 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS on the "RxUAddr[4:0]" input pins) with the NULL Address (e.g., 0x1F). However, if the user configures the Receive UTOPIA Interface block to operate in the "UTOPIA Level 3" Mode, and if the user also enables "Back-to-Back Polling", then he/she does not need to interleave the UTOPIA Addresses with the NULL Address. In this case, the user can simply apply a "back-to-back" stream of "relevant" UTOPIA Addresses to the "RxUAddr[4:0]" input pins, and the XRT94L33 will respond by driving the RxUClav output pins to the appropriate states (depending upon the Receive FIFO fill-status). 0 - Disables "Back-to-Back" Polling. In this mode, the user must interleave all UTOPIA Addresses (that are to be applied to the "RxUAddr[4:0]" input pins) with the NULL Address. 1 - Enables "Back-to-Back" Polling. In this mode, the user does not need to interleave all UTOPIA Addresses (that are to be applied to the "RxUAddr[4:0]" input pins) with the NULL Address. Note: In order to configure the Receive UTOPIA Interface block to operate in the "Back-to-Back Polling" Mode, the user must also do the following. 1.Configure the Receive UTOPIA Interface to operate in the "UTOPIA Level 3" Mode. This is accomplished by setting Bit 7 (UTOPIA Level 3 Disable) within this Register to "0". 2.Configure the Receive UTOPIA Interface to support "MultiPHY" Polling. This is accomplished by setting Bit 6 (Multi-PHY Polling Enable) within this register to "1". 4 3-2 Direct Status Indication Enable UTOPIA/POS-PHY Data Bus Width[1:0] R/W R/W UTOPIA/POS-PHY Data Bus Width[1:0]: These READ/WRITE bit-fields permit the user to select the width of the Receive UTOPIA and POS-PHY Data Buses. The relationship between the contents of these bit-fields and the corresponding widths of the Receive UTOPIA and POS-PHY Data Bus is tabulated below. UTOPIA/POS-PHY Data Bus Width[1:0] 00 01 10 11 1-0 Cell Size[1:0] Cell Size[1:0]: These two READ/WRITE bit-fields permit the user to specify the size of the ATM cell that will be handled by the Receive UTOPIA Interface blocks. The relationship between the contents of these bit-fields and the corresponding Cell Sizes are tabulated below. Corresponding UTOPIA/POSPHY Data Bus Width Not Valid 8 bits 16 bits Not Valid Cell Size[1:0] Resulting Cell Size (Bytes) 133 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 01 53 bytes (Only valid for UTOPIA Level 1, and if the UTOPIA Data Bus Width is set to 8 bits) 54 bytes (Only valid for UTOPIA Levels 1 and 2) 56 bytes The user must bear in mind the UTOPIA Level and the UTOPIA Data Bus width selected, when selecting the Cell Size. 20 0 Rev2...0...0 200 10 11 Note: 134 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 68: Receive UTOPIA Port Address Register (Address = 0x0513) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Receive UTOPIA Port Address [4:0] BIT NUMBER 7-5 4-0 NAME Unused Receive UTOPIA Port Address [4:0] TYPE R/O R/W DESCRIPTION Receive UTOPIA Port Address[4:0]: These READ/WRITE register bits, along with the "Receive UTOPIA Port Number [4:0]" bits (within the "Receive UTOPIA Port Number" Register (Address = 0x0517) permit the user to assign a unique Receive UTOPIA address to each of the three STS-1 channels within the XRT94L33. For UTOPIA Level 2/3 applications, the user can write in any value, ranging from 0x00 through 0x1E into this register. The Receive UTOPIA Address Assignment Procedure: In order to assign a UTOPIA Address to a given Channel (or Port) within the XRT94L33, the user must do the following. a. Write the value corresponding to a given XRT94L33 Channel into the "Receive UTOPIA Port Number" Register (Address = 0x0517). Write the corresponding UTOPIA Address value into this register. b. Once this "two-step" procedure has been executed, then the XRT94L33 Channel (as specified during step "a") will be assigned the "Receive UTOPIA Address" value (as specified during step "b"). 135 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 69: Receive UTOPIA Port Number Register (Address = 0x0517) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 Receive UTOPIA Port Number[4:0] BIT NUMBER 7-5 4-0 NAME Unused Receive UTOPIA Port Number[4:0] TYPE R/O R/W DESCRIPTION Receive UTOPIA Port Number[4:0]: These READ/WRITE register bits, along with the "Receive UTOPIA Port Address[4:0]" bits (within the "Receive UTOPIA Port Address" Register (Address = 0x0513) permit the user to assign a unique Receive UTOPIA address to each of the three STS-1 channels within the XRT94L33. In the XRT94L33, the following are the only valid values that can be written into these register bits, during the "Receive UTOPIA Address Assignment" process. 0x00 - XRT94L33 Channel 0 0x01 - XRT94L33 Channel 1 0x02 - XRT94L33 Channel 2 The Receive UTOPIA Address Assignment Procedure: In order to assign a UTOPIA Address to a given Channel (or Port) within the XRT94L33, the user must do the following. a. b. Write the value corresponding to a given XRT94L33 Channel into this register. Write the corresponding UTOPIA Address value into the "Receive UTOPIA Port Address" Register (Address = 0x0513). Once this "two-step" procedure has been executed, then the XRT94L33 Channel (as specified during step "a") will be assigned the "Receive UTOPIA Address" value (as specified during step "b"). 136 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TRANSMIT UTOPIA INTERFACE BLOCK REGISTER DESCIPTION 1.4.3 Table 70: Transmit UTOPIA/POS-PHY Control Register - Byte 0 (Address = 0x0583) BIT 7 UTOPIA Level 3 Disable R/W 1 BIT 6 Multi-PHY Polling Enable R/W 0 BIT 5 Back to Back Polling Enable R/W 0 BIT 4 Direct Status Indication Enable R/W 0 BIT 3 BIT 2 BIT 1 BIT 0 UTOPIA/POS-PHY Data Bus Width Cell Size[1:0] R/W 1 R/W 1 R/W 1 R/W 1 BIT NUMBER 7 6 NAME UTOPIA Level 3 Disable Multi-PHY Polling Enable TYPE R/W R/W DESCRIPTION Multi-PHY Polling Enable: This READ/WRITE bit-field permits the user to either enable or disable Multi-PHY Polling for the Transmit UTOPIA Interface block. If the user implements this feature (and configures the XRT94L33 to operate in the Multi-PHY Mode) then the TxUClav output pin will be driven (either "high" or "low") based upon the fill-status of the Transmit FIFO within the Channel that corresponds to the "Transmit UTOPIA Address" that is currently being applied to the "TxUAddr[4:0]" input pins. If the user does not implement this feature (and then configures the XRT94L33 to operate in the Single-PHY Mode), then the "TxUClav" output pin will unconditionally reflect the "Transmit FIFO fill-status" for Channel 0. No attention will be paid to the address values placed upon the "TxUAddr[4:0]" input pins. 0 - Configures the Transmit UTOPIA Interface block to operate in the Single-PHY Mode. 1 - Configures the Transmit UTOPIA Interface block to operate in the Multi-PHY Mode. 5 Back-to-Back Polling Enable R/W Back-to-Back Polling Enable: This READ/WRITE bit-field permits the user to configure the Transmit UTOPIA Interface block to support "Back-to-Back Polling". Ordinarily, for Multi-PHY polling, the user is required to interleave all UTOPIA Address values (that are to be placed on the "TxUAddr[4:0]" input pins) with the NULL Address (e.g., 0x1F). However, if the user configures the Transmit UTOPIA Interface block to operate in the "UTOPIA Level 3" Mode, and if the user also enables "Back-to-Back Polling", then he/she does not need interleave the UTOPIA Addresses with the NULL Address. In this case, the user can simply apply a "back-to-back" stream of "relevant" UTOPIA Addresses to the "TxUAddr[4:0]" input pins, and the XRT94L33 will respond by driving the TxUClav output pins to the appropriate states (depending upon the Transmit FIFO fill-status). 0 - Disables "Back-to-Back" Polling. In this mode, the user must interleave all UTOPIA Addresses (that are to be applied to the "TxUAddr[4:0]" input pins) with the NULL Address. 1 - Enables "Back-to-Back" Polling. In this mode, the user does 137 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 not need to interleave all UTOPIA Addresses (that are to be applied to the "TxUAddr[4:0]" input pins) with the NULL Address. Note: In order to configure the Transmit UTOPIA Interface block to operate in the "Back-to-Back Polling" Mode, the user must also do the following. 1. Configure the Transmit UTOPIA Interface to operate in the "UTOPIA Level 3" Mode. This is accomplished by setting Bit 7 (UTOPIA Level 3 Disable) within this Register to "0". 2. Configure the Transmit UTOPIA Interface to support "MultiPHY" Polling. This is accomplished by setting Bit 6 (Multi-PHY Polling Enable) within this register to "1". 4 3-2 Direct Status Indication Enable UTOPIA/POS-PHY Data Bus Width[1:0] R/W R/W UTOPIA/POS-PHY Data Bus Width[1:0]: These READ/WRITE bit-fields permit the user to select the width of the Transmit UTOPIA and POS-PHY Data Buses. The relationship between the contents of these bit-fields and the corresponding widths of the Transmit UTOPIA and POS-PHY Data Bus is tabulated below. UTOPIA/POS-PHY Data Bus Width[1:0] 00 01 10 11 1-0 Cell Size[1:0] Cell Size[1:0]: These two READ/WRITE bit-fields permit the user to specify the size of the ATM cell that will be handled by the Transmit UTOPIA Interface blocks. The relationship between the contents of these bit-fields and the corresponding Cell Sizes are tabulated below. Cell Size[1:0] 00 01 Resulting Cell Size (Bytes) 52 bytes 53 bytes (Only valid for UTOPIA Level 1, and if the UTOPIA Data Bus Width is set to 8 bits) 54 bytes (Only valid for UTOPIA Levels 1 and 2) 56 bytes The user must bear in mind the UTOPIA Level and the UTOPIA Data Bus width selected, when selecting the Cell Size. Corresponding UTOPIA/POSPHY Data Bus Width Not Valid 8 bits 16 bits Not Valid 10 11 Note: 138 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 71: Transmit UTOPIA Port Address Register (Address = 0x0593) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit UTOPIA Port Address[4:0] BIT NUMBER 7-5 4-0 NAME Unused Transmit UTOPIA Port Address[4:0] TYPE R/O R/W DESCRIPTION Transmit UTOPIA Port Address[4:0]: These READ/WRITE register bits, along with the "Transmit UTOPIA Port Number[4:0]" bits (within the "Trasnmit UTOPIA Port Number" Register (Address = 0x0597) permit the user to assign a unique Transmit UTOPIA address to each of the three STS-1 channels within the XRT94L33. For UTOPIA Level 2/3 applications, the user can write in any value, ranging from 0x00 through 0x1E into this register. The Transmit UTOPIA Address Assignment Procedure: In order to assign a UTOPIA Address to a given Channel (or Port) within the XRT94L33, the user must do the following. a. Write the value corresponding to a given XRT94L33 Channel into the "Transmit UTOPIA Port Number" Register (Address = 0x0597). Write the corresponding UTOPIA Address value into this register. b. Once this "two-step" procedure has been executed, then the XRT94L33 Channel (as specified during step "a") will be assigned the "Transmit UTOPIA Address" value (as specified during step "b"). 139 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 72: Transmit UTOPIA Port Number Register (Address = 0x0597) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 Transmit UTOPIA Port Number[4:0] BIT NUMBER 7-5 4-0 NAME Unused Transmit UTOPIA Port Number[4:0] TYPE R/O R/W DESCRIPTION Transmit UTOPIA Port Number[4:0]: These READ/WRITE register bits, along with the "Transmit UTOPIA Port Address[4:0]" bits (within the "Transmit UTOPIA Port Address" Register (Address = 0x0593) permit the user to assign a unique Transmit UTOPIA address to each of the three STS-1 channels within the XRT94L33. In the XRT94L33, the following are the only valid values that can be written into these register bits, during the "Transmit UTOPIA Address Assignment" process. 0x00 - XRT94L33 Channel 0 0x01 - XRT94L33 Channel 1 0x02 - XRT94L33 Channel 2 The Transmit UTOPIA Address Assignment Procedure: In order to assign a UTOPIA Address to a given Channel (or Port) within the XRT94L33, the user must do the following. a. b. Write the value corresponding to a given XRT94L33 Channel into this register. Write the corresponding UTOPIA Address value into the "Transmit UTOPIA Port Address" Register (Address = 0x0593). Once this "two-step" procedure has been executed, then the XRT94L33 Channel (as specified during step "a") will be assigned the "Transmit UTOPIA Address" value (as specified during step "b"). 140 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RECEIVE STS-3 TOH PROCESSOR BLOCK 1.5 The register map for the Receive STS-3 TOH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Receive STS-3 TOH Processor" Block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "Receive STS-3 TOH Processor Block "highlighted" is presented below in Figure 6 Figure 6: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive STS-3 TOH Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 141 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.5.1 RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 73: Receive STS-3 TOH Processor Block Control Register - Address Map INDIVIDUAL REGISTER ADDRESS 0x00 - 0x02 0x03 0x04 - 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D - 0x1E 0x1F ADDRESS LOCATION 0x1000 - 0x1102 0x1103 0x1104 - 0x1105 0x1106 0x1107 0x1108 0x1109 0x110A 0x110B 0x110C 0x110D 0x110E 0x110F 0x1110 0x1111 0x1112 0x1113 0x1114 0x1115 0x1116 0x1117 0x1118 0x1119 0x111A 0x111B 0x111C 0x111D - 0x111E 0x111F Reserved Receive STS-3 Transport Control Register - Byte 0 Reserved Receive STS-3 Transport Status Register - Byte 1 Receive STS-3 Transport Status Register - Byte 0 Reserved Receive STS-3 Transport Interrupt Status Register - Byte 2 Receive STS-3 Transport Interrupt Status Register - Byte 1 Receive STS-3 Transport Interrupt Status Register - Byte 0 Reserved Receive STS-3 Transport Interrupt Enable Register - Byte 2 Receive STS-3 Transport Interrupt Enable Register - Byte 1 Receive STS-3 Transport Interrupt Enable Register - Byte 0 Receive STS-3 Transport B1 Error Count - Byte 3 Receive STS-3 Transport B1 Error Count - Byte 2 Receive STS-3 Transport B1 Error Count - Byte 1 Receive STS-3 Transport B1 Error Count - Byte 0 Receive STS-3 Transport B2 Error Count - Byte 3 Receive STS-3 Transport B2 Error Count - Byte 2 Receive STS-3 Transport B2 Error Count - Byte 1 Receive STS-3 Transport B2 Error Count - Byte 0 Receive STS-3 Transport REI-L Error Count - Byte 3 Receive STS-3 Transport REI-L Error Count - Byte 2 Receive STS-3 Transport REI-L Error Count - Byte 1 Receive STS-3 Transport REI-L Error Count - Byte 0 Reserved Reserved Receive STS-3 Transport K1 Byte Value 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME DEFAULT VALUES 142 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0x1120 - 0x1122 0x1123 0x1124 - 0x1126 0x1127 0x1128 - 0x112A 0x112B 0x112C, 0x112D 0x112E 0x112F 0x1130 0x1131 0x1132 0x1133 0x1134 - 0x1135 0x1136 0x1137 0x1138, 0x1139 0x113A 0x113B 0x113C 0x113D 0x113E 0x113F 0x1140, 0x1141 0x1142 0x1143 0x1144, 0x1145 0x1146 0x1147 0x1148 - 0x114A 0x114B Reserved Receive STS-3 Transport K2 Byte Value Reserved Receive STS-3 Transport S1 Byte Value Reserved Receive STS-3 Transport - In-Sync Threshold Value Reserved Receive STS-3 Transport - LOS Threshold Value - MSB Receive STS-3 Transport - LOS Threshold Value - LSB Reserved Receive STS-3 Transport - SF Set Monitor Interval - Byte 2 Receive STS-3 Transport - SF Set Monitor Interval - Byte 1 Receive STS-3 Transport - SF Set Monitor Interval - Byte 0 Reserved Receive STS-3 Transport - SF Set Threshold - Byte 1 Receive STS-3 Transport - SF Set Threshold - Byte 0 Reserved Receive STS-3 Transport - SF Clear Threshold - Byte 1 Receive STS-3 Transport - SF Clear Threshold - Byte 0 Reserved Receive STS-3 Transport - SD Set Monitor Interval - Byte 2 Receive STS-3 Transport - SD Set Monitor Interval - Byte 1 Receive STS-3 Transport - SD Set Monitor Interval - Byte 0 Reserved Receive STS-3 Transport - SD Set Threshold - Byte 1 Receive STS-3 Transport - SD Set Threshold - Byte 0 Reserved Receive STS-3 Transport - SD Clear Threshold - Byte 1 Receive STS-3 Transport - SD Clear Threshold - Byte 0 Reserved Receive STS-3 Transport - Force SEF Condition REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS 0x20 - 0x22 0x23 0x24 - 0x26 0x27 0x28 - 0x2A 0x2B 0x2C, 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34, 0x35 0x36 0x37 0x38, 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40, 0x41 0x42 0x43 0x44, 0x45 0x46 0x47 0x48 - 0x4A 0x4B 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 143 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x4C, 0x4E 0x4F 0x50, 0x51 0x52 0x53 0x54, 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 - 0x62 0x63 0x64 - 0x66 0x67 0x68 - 0x6A 0x6B 0x6C - 0x79 0x7A 0x7B 0x7C ADDRESS LOCATION 0x114C, 0x114E 0x114F 0x1150, 0x1151 0x1152 0x1153 0x1154, 0x1155 0x1156 0x1157 0x1158 0x1159 0x115A 0x115B 0x115C 0x115D 0x115E 0x115F 0x1160 - 0x1162 0x1163 0x1164 - 0x1166 0x1167 0x1168 - 0x116A 0x116B 0x116C - 0x1179 0x117A 0x117B 0x117C Reserved Receive STS-3 Transport - Receive J0 Trace Buffer Control Reserved Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 1 Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 0 Reserved Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 1 Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 0 Reserved Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 2 Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 1 Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 2 Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 1 Receive STS-3 Transport - Receive SF Clear Monitor - Byte 0 Reserved Receive STS-3 Transport - Auto AIS Control Register Reserved Receive STS-3 Transport - Serial Port Control Register Reserved Receive STS-3 Transport - Auto AIS (in Downstream STS1s) Control Register Reserved Receive STS-3 Transport - TOH Capture Indirect Address Receive STS-3 Transport - TOH Capture Indirect Address Receive STS-3 Transport - TOH Capture Indirect Data 0x00 0x00 0x00 REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x00 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x000 144 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0x117D 0x117E 0x117F 0x1180 - 0x11FF REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS 0x7D 0x7E 0x7F 0x80 - 0xFF Receive STS-3 Transport - TOH Capture Indirect Data Receive STS-3 Transport - TOH Capture Indirect Data Receive STS-3 Transport - TOH Capture Indirect Data Reserved 0x00 0x00 0x00 0x00 145 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.5.2 RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 74: Receive STS-3 Transport Control Register - Byte 0 (Address Location= 0x1103) BIT 7 STS-N OH Extract R/W 0 BIT 6 SF Detect Enable R/W 0 BIT 5 SD Detect Enable R/W 0 BIT 4 Descramble Disable R/W 0 BIT 3 SDH/ SONET* R/W 0 BIT 2 REI-L Error Type R/W 0 BIT 1 B2 Error Type R/W 0 BIT 0 B1 Error Type R/W 0 BIT NUMBER 7 NAME STS-N OH Extract TYPE R/W DESCRIPTION STS-N Overhead Extract (Revision C Silicon Only): This READ/WRITE bit-field permits the user to configure the RxTOH output port to output the TOH for all lower-tributary STS-1s within the incoming STS-3 signal. 0 - Disables this feature. In this mode, the RxTOH output port will only output the TOH for the first STS-1 within the incoming STS-3 signal. 1 - Enables this feature. 6 SF Detect Enable R/W Signal Failure (SF) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SF Detection by the Receive STS-3 TOH Processor Block. 0 - SF Detection is disabled. 1 - SF Detection is enabled: 5 SD Detect Enable R/W Signal Degrade (SD) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SD Detection by the Receive STS-3 TOH Processor Block. 0 - SD Detection is disabled. 1 - SD Detection is enabled. 4 Descramble Disable R/W De-Scramble Disable: This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Receive STS-3 TOH Processor block. 0 - De-Scrambling is enabled. 1 - De-Scrambling is disabled. 3 SDH/SONET* R/W SDH/SONET Select: This READ/WRITE bit-field permits the user to configure the Receiver to operate in either the SONET or SDH Mode. 0 - Configures the Receiver to operate in the SONET Mode. 1 - Configures the Receiver to operate in the SDH Mode. 2 REI-L Error Type R/W REI-L (Line - Remote Error Indicator) Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport REI-L Error Count" register is incremented. 0 - Configures the Receive STS-3 TOH Processor block to count REI-L Bit Errors. In this case the "Receive Transport REI-L Error Count" register will be 146 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS incremented by the value of the lower nibble within the M0/M1 byte. 1 - Configures the Receive STS-3 TOH Processor block to count REI-L Frame Errors. In this case the "Receive Transport REI-L Error Count" register will be incremented each time the STS-3 Receiver receives a "non-zero" M0/M1 byte. 1 B2 Error Type R/W B2 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport B2 Error Count" register is incremented. 0 - Configures the Receive STS-3 TOH Processor block to count B2 bit errors. In this case, the "Receive Transport B2 Error Count" register will be incremented by the number of bits, within the B2 value, that is in error. 1 - Configures the Receive STS-3 TOH Processor block to count B2 frame errors. In this case, the "Receive Transport B2 Error Count" register will be incremented by the number of erred STS-3 frames. 0 B1 Error Type R/W B1 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport B1 Error Count" register is incremented. 0 - Configures the Receive STS-3 TOH Processor block to count B1 bit errors. In this case, the "Receive Transport B1 Error Count" register will be incremented by the number of bits, within the B1 value, that is in error. 1 - Configures the Receive STS-3 TOH Processor block to count B2 bit errors. In this case, the "Receive Transport B1 Error Count" register will be incremented by the number of erred STS-3 frames. 147 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 75: Receive STS-3 Transport Status Register - Byte 1 (Address Location= 0x1106) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 J0 Message Mismatch Defect Declared R/O 0 R/O 0 R/O 0 BIT 1 J0 Message Unstable Defect Declared R/O 0 BIT 0 AIS_L Defect Declared 20 0 Rev2...0...0 200 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused J0 Message Mismatch Defect Declared TYPE R/O R/O DESCRIPTION J0 - Section Trace Mismatch Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the Section Trace Mismatch condition. The Receive STS-3 TOH Processor block will declare a J0 (Section Trace) Mismatch condition, whenever it accepts a J0 Message that differs from the "Expected J0 Message". 0 - Section Trace Mismatch Condition is NOT declared. 1 - Section Trace Mismatch Condition is currently declared. 1 J0 Message Unstable Defect Declared R/O J0 - Section Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the Section Trace Instability condition. The Receive STS-3 TOH Processor block will declare a J0 (Section Trace) Unstable condition, whenever the "J0 Unstable" counter reaches the value 8. The "J0 Unstable" counter will be incremented for each time that it receives a J0 message that differs from the "Expected J0 Message". The "J0 Unstable" counter is cleared to "0" whenever the Receive STS-3 TOH Processor block has received a given J0 Message 3 (or 5) consecutive times. Note: Receiving a given J0 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Section Trace Instability condition is NOT declared. 1 - Section Trace Instability condition is currently declared. 0 AIS_L Defect Declared R/O AIS-L (Line AIS) State: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently detecting an AIS-L (Line AIS) pattern in the incoming STS-3 data stream. AIS-L is declared if bits 6, 7 and 8 (e.g., the Least Significant Bits, within the K2 byte) value the value "1, 1, 1" for five consecutive STS-1 frames. 0 - AIS-L is NOT currently declared. 1 - AIS-L is currently being declared. 148 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 76: Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1107) BIT 7 RDI-L Defect Declared R/O 0 BIT NUMBER 7 BIT 6 S1 Byte Unstable Defect Declared R/O 0 NAME RDI-L Defect Declared TYPE R/O BIT 5 (K1, K2) APS Byte Unstable R/O 0 BIT 4 SF Defect Declared BIT 3 SD Defect Declared BIT 2 LOF Defect Declared R/O 0 DESCRIPTION RDI-L (Line Remote Defect Indicator) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring a Line-Remote Defect Indicator (RDI-L), in the incoming STS-3 signal. RDI-L is declared when bits 6, 7 and 8 (e.g., the three least significant bits) of the K2 byte contains the "1, 1, 0" pattern in 5 consecutive STS-3 frames. 0 - RDI-L is NOT being declared. 1 - RDI-L is currently being declared. 6 S1 Byte Unstable Defect Declared R/O S1 Byte Unstable Defect Declared Condition: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the "S1 Byte Instability" condition. The Receive STS-3 TOH Processor block will declare an "S1 Byte Instability" condition whenever the "S1 Byte Unstable Counter" reaches the value 32. The "S1 Byte Unstable Counter" is incremented for each time that the Receive STS-3 TOH Processor block receives an S1 byte that differs from the previously received S1 byte. The "S1 Byte Unstable Counter" is cleared to "0" when the same S1 byte is received for 8 consecutive STS-3 frames. Note: Receiving a given S1 byte, in 8 consecutive STS-3 frames also sets this bit-field to "0". BIT 1 SEF Defect Declared R/O 0 BIT 0 LOS Defect Declared R/O 0 R/O 0 R/O 0 0 - S1 Instability Condition is NOT declared. 1 - S1 Instability Condition is currently declared. 5 (K1, K2) APS Byte Unstable R/O APS (K1, K2 Byte) Unstable Condition: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the "K1, K2 Byte Unstable" condition. The Receive STS-3 TOH Processor block will declare a "K1, K2 Byte Unstable" condition whenever the Receive STS-3 TOH Processor block fails to receive the same set of K1, K2 bytes, in 12 consecutive STS-3 frames. The "K1, K2 Byte Unstable" condition is cleared whenever the Receive STS-3 TOH Processor block receives a given set of K1, K2 byte values in three consecutive STS-3 frames. 0 - K1, K2 Unstable Condition is NOT currently declared. 1 - K1, K2 Unstable Condition is currently declared. 4 SF Defect Declared R/O SF (Signal Failure) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the SF defect. The SF defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SF Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given 149 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS interval of time) does not exceed the "SF Declaration" threshold. 1 - SF Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SF Declaration" threshold. 3 SD Defect Declared R/O SD (Signal Degrade) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the SD defect. The SD defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SD Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given interval of time) does not exceed the "SD Declaration" threshold. 1 - SD Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SD Declaration" threshold. 2 LOF Defect Declared R/O LOF (Loss of Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring an LOF defect condition. The Receive STS-3 TOH Processor block will declare an LOF defect condition, if continues to declare the SEF (Severely Errored Frame) condition for 3ms (or 24 SONET frame periods). 0 - LOF is NOT being declared. 1 - LOF is currently being declared. 1 SEF Defect Declared R/O SEF (Severely Errored Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring an SEF condition. The SEF condition is declared, if the "SEF Declaration Criteria"; per the settings of the FRPATOUT[1:0] bits, within the Receive STS-3 Transport - In-Sync Threshold Value Register (Address Location= 0x112B). 0 - SEF condition is NOT being declared. 1 - SEF condition is currently being declared. 0 LOS Defect Declared R/O LOS (Loss of Signal) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring an LOS (Loss of Signal) defect condition. The Receive STS-3 TOH Processor block will declare an LOS defect condition if it detects "LOS_THRESHOLD[15:0]" consecutive "All Zero" bytes in the incoming STS-3 data stream. Note: The user can set the "LOS_THRESHOLD[15:0]" value by writing the appropriate data into the "Receive STS-3 Transport - LOS Threshold Value" Register (Address Location= 0x112E and 0x112F). 20 0 Rev2...0...0 200 0 - Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring an LOS defect condition. 1 - Indicates that the Receive STS-3 TOH Processor block is currently declaring an LOS defect condition. 150 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 77: Receive STS-3 Transport Interrupt Status Register - Byte 2 (Address Location= 0x1109) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Condition Interrupt Status R/O 0 R/O 0 R/O 0 RUR 0 BIT 0 Change of RDI-L Condition Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Condition Interrupt Status TYPE R/O RUR DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of AIS-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of AIS-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of AIS-L by reading the contents of Bit 0 (AIS-L Defect Declared) within the "Receive STS3 Transport Status Register - Byte 1" (Address Location= 0x1106). 0 Change of RDI-L Condition Interrupt Status RUR Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of RDI-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of RDI-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of RDI-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of RDI-L by reading out the state of Bit 7 (RDI-L Declared) within the "Receive STS-3 Transport Status Register - Byte 0" (Address Location = 0x1107). I 151 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 78: Receive STS-3 Transport Interrupt Status Register - Byte 1 (Address Location= 0x110A) BIT 7 New S1 Byte Interrupt Status BIT 6 Change in S1 Unstable State Interrupt Status BIT 5 Change in J0 Message Unstable State Interrupt Status RUR 0 BIT 4 New J0 Message Interrupt Status BIT 3 Change in J0 Mismatch Condition Interrupt Status BIT 2 Receive TOH CAP DONE Interrupt Status BIT 1 Change in (K1, K2) APS Bytes Unstable State Interrupt Status RUR 0 BIT 0 NEW K1K2 Byte Interrupt Status 20 0 Rev2...0...0 200 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Status TYPE RUR DESCRIPTION New S1 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New S1 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New S1 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New S1 Byte Value" interrupt has occurred since the last read of this register. Note: The user can obtain the value for this most recently accepted value of the S1 byte by reading the "Receive STS-3 Transport S1 Value" register (Address Location= 0x1127). 6 Change in S1 Byte Unstable State Interrupt Status RUR Change in S1 Byte Unstable State - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 1 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has not occurred since the last read of this register. Note: The user can obtain the current "S1 Unstable" state by reading the contents of Bit 6 (S1 Unstable) within the "Receive STS-3 Transport Status Register - Byte 0" (Address Location= 0x1107). 5 Change in J0 Message Unstable State Interrupt Status RUR Change of J0 (Section Trace) Message Unstable condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 4 New J0 Message Interrupt Status RUR New J0 Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New J0 Trace Message" interrupt has occurred since the last read of this register. 0 - Indicates that the "New J0 Trace Message Interrupt" has not occurred since the last read of this register. 152 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Indicates that the "New J0 Trace Message Interrupt" has occurred since the last read of this register. Note: The user can read out the contents of the "Receive J0 Trace Buffer", which is located at Address location 0x1300 through 0x133F. 3 Change in J0 Mismatch Condition Interrupt Status RUR Change in J0 - Section Trace Mismatch Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared" or "declared" by reading the state of Bit 2 (J0_MIS) within the "Receive STS-3 Transport Status Register - Byte 1 (Address Location= 0x1106). 2 Receive TOH CAP DONE Interrupt Status RUR Receive TOH Capture DONE - Interrupt Status: This RESET-upon-READ bit-field indicates whether the "Receive TOH Data Capture" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the "Receive TOH Capture" buffer, it will remain there for one SONET frame period. 0 - Indicates that the "Receive TOH Data Capture" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Receive TOH Data Capture" Interrupt has occurred since the last read of this register. 1 Change in APS (K1, K2 Byte) Unstable Status Interrupt Status RUR Change of APS (K1, K2 Byte) Unstable Condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "K1, K2 Unstable Condition" is being declared or cleared by reading out the contents of Bit 5 (APS Unstable), within the "Receive STS-3 Transport Status Register - Byte 0" (Address Location = 0x1107). 0 NEW K1K2 Byte Interrupt Status RUR New K1, K2 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New K1, K2 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the new K1 byte by reading out 153 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 the contents of the "Receive STS-3 Transport K1 Value" Register (Address Location= 0x111F). Further, the user can also obtain the contents of the new K2 byte by reading out the contents of the "Receive STS-3 Transport K2 Value" Register (Address Location= 0x1123). 154 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 79: Receive STS-3 Transport Interrupt Status Register - Byte 0 (Address Location= 0x110B) BIT 7 Change in SF Condition Interrupt Status RUR 0 BIT 6 Change in SD Condition Interrupt Status RUR 0 BIT 5 Detection of REI-L Error Interrupt Status RUR 0 BIT 4 Detection of B2 Error Interrupt Status RUR 0 BIT 3 Detection of B1 Error Interrupt Status RUR 0 BIT 2 Change of LOF Condition Interrupt Status RUR 0 BIT 1 Change of SEF Condition Interrupt Status RUR 0 BIT 0 Change of LOS Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Change in SF Condition Interrupt Status TYPE RUR DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SF Condition Interrupt" has occurred since the last read of this register. 0 - The "Change of SF Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SF Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SF" condition by reading out the state of Bit 4 (SF Declared) within the "Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1107). 6 Change of SD Condition Interrupt Status RUR Change of Signal Degrade (SD) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SD Condition Interrupt" has occurred since the last read of this register. 0 - The "Change of SD Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SD Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SD" condition by reading out the state of Bit 3 (SD Declared) within the "Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1107). 5 Detection of REIL Interrupt Status RUR Detection of Line - Remote Error Indicator Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Declaration of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 0 - The "Declaration of Line - Remote Error Indicator" Interrupt has NOT occurred since the last read of this register. 1 - The "Declaration of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 4 Detection of B2 Error Interrupt Status RUR Detection of B2 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B2 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B2 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B2 Error Interrupt" has occurred since the last read of this register. 155 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 3 Detection of B1 Error Interrupt Status RUR Detection of B1 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B1 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B1 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B1 Error Interrupt" has occurred since the last read of this register 2 Change of LOF Interrupt Status RUR Change of Loss of Frame (LOF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOF Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOF Condition" interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOF Condition" interrupt has occurred since the last read of this register. Note: The user can determine the current "LOF" condition by reading out the state of Bit 2 (LOF Defect Declared) within the "Receive STS3 Transport Status Register - Byte 0 (Address Location= 0x1107). 20 0 Rev2...0...0 200 1 Change of SEF Condition Interrupt Status RUR Change of SEF Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SEF" Condition Interrupt has occurred since the last read of this register. 0 - The "Change of SEF Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of SEF Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "SEF" condition by reading out the state of Bit 1 (SEF Defect Declared) within the "Receive STS3 Transport Status Register - Byte 0 (Address Location= 0x1107). 0 Change of LOS Condition Interrupt Status RUR Change of Loss of Signal (LOS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOS Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOS Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOS Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "LOS" status by reading out the contents of Bit 0 (LOS Defect Declared) within the Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1107). 156 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 80: Receive STS-3 Transport Interrupt Enable Register - Byte 2 (Address Location= 0x110D) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Condition Interrupt Enable R/O 0 R/O 0 R/O 0 R/W 0 BIT 0 Change of RDI-L Condition Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Condition Interrupt Enable TYPE R/O R/W DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Receive STS-3 TOH Processor block declares the "AIS-L" condition. * When the Receive STS-3 TOH Processor block clears the "AIS-L" condition. 0 - Disables the "Change of AIS-L Condition" Interrupt. 1 - Enables the "Change of AIS-L Condition" Interrupt. Note: The user can determine the current "AIS-L" condition by reading out the state of Bit 0 (AIS-L) within the "Receive STS-3 Transport Status Register - Byte 1" (Address Location= 0x1106). 0 Change of RDI-L Condition Interrupt Enable R/W Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of RDI-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Receive STS-3 TOH Processor block declares the "RDI-L" condition. * When the Receive STS-3 TOH Processor block clears the "RDI-L" condition. 0 - Disables the "Change of RDI-L Condition" Interrupt. 1 - Enables the "Change of RDI-L Condition" Interrupt. 157 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 81: Receive STS-3 Transport Interrupt Enable Register - Byte 1 (Address Location= 0x110E) BIT 7 New S1 Byte Interrupt Enable BIT 6 Change in S1 Byte Unstable State Interrupt Enable R/W 0 BIT 5 Change in J0 Message Unstable State Interrupt Enable R/W 0 BIT 4 New J0 Message Interrupt Enable BIT 3 J0 Mismatch Interrupt Enable BIT 2 Receive TOH CAP DONE Interrupt Enable R/W 0 BIT 1 Change in APS Unstable State Interrupt Enable R/W 0 BIT 0 NEW K1K2 Byte Interrupt Enable R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Enable TYPE R/W DESCRIPTION New S1 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New S1 Byte Value" Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new S1 byte value. The Receive STS-3 TOH Processor block will accept a new S1 byte after it has received it for 8 consecutive STS-3 frames. 0 - Disables the "New S1 Byte Value" Interrupt. 1 - Enables the "New S1 Byte Value" Interrupt. 6 Change in S1 Unstable State Interrupt Enable R/W Change in S1 Byte Unstable State Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in S1 Byte Unstable State" Interrupt. If the user enables this bit-field, then the Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. * * When the Receive STS-3 TOH Processor block declares the "S1 Byte Instability" condition. When the Receive STS-3 TOH Processor block clears the "S1 Byte Instability" condition. 0 - Disables the "Change in S1 Byte Unstable State" Interrupt. 1 - Enables the "Change in S1 Byte Unstable State" Interrupt. 5 Change in J0 Message Unstable State Interrupt Enable R/W Change of J0 (Section Trace) Message Instability condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of J0 Message Instability Condition" Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. * * Whenever the Receive STS-3 TOH Processor block declares the "J0 Message Instability" condition. Whenever the Receive STS-3 TOH Processor block clears the "J0 Message Instability" condition. 0 - Disable the "Change of J0 Message Instability" Interrupt. 1 - Enables the "Change of J0 Message Instability" Interrupt. 4 New J0 Message Interrupt Enable R/W New J0 Trace Message Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New J0 Trace Message" interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new J0 Trace Message. The Receive STS-3 TOH Processor block will accept a new J0 158 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Trace Message after it has received it 3 (or 5) consecutive times. 0 - Disables the "New J0 Trace Message" Interrupt. 1 - Enables the "New J0 Trace Message" Interrupt. 3 J0 Mismatch Interrupt Enable R/W Change in "J0 - Section Trace Mismatch Condition" interrupt enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in J0 - Section Trace Mismatch condition" interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following events. * * The Receive STS-3 TOH Processor block declares a "J0 - Section Trace Mismatch" condition. The Receive STS-3 TOH Processor block clears the "J0 - Section Trace Mismatch" condition. The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared or "declared" by reading the state of Bit 2 (J0 Message Mismatch Defect Declared) within the "Receive STS-3 Transport Status Register - Byte 1 (Address Location= 0x1106). Note: 2 Receive TOH CAP DONE Interrupt Enable R/W Receive TOH Capture DONE - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive TOH Data Capture" interrupt, within the Receive STS-3 TOH Processor Block. If this interrupt is enabled, then the Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the "Receive TOH Capture" buffer, it will remain there for one SONET frame period. 0 - Disables the "Receive TOH Capture" Interrupt. 1 - Enables the "Receive TOH Capture" Interrupt. 1 Change in APS Unstable State Interrupt Enable R/W Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of APS (K1, K2 Byte) Instability condition" interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate an Interrupt in response to either of the following events. * * If the Receive STS-3 TOH Processor block declares a "K1, K2 Instability" condition. If the Receive STS-3 TOH Processor block clears the "K1, K2 Instability" condition. 0 New K1K2 Byte Interrupt Enable R/W New K1, K2 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New K1, K2 Byte Value" Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new K1, K2 byte value. The Receive STS-3 TOH Processor block will accept a new K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-3 frames. 0 - Disables the "New K1, K2 Byte Value" Interrupt. 1 - Enables the "New K1, K2 Byte Value" Interrupt. 159 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 82: Receive STS-3 Transport Interrupt Status Register - Byte 0 (Address Location= 0x110F) BIT 7 Change of SF Condition Interrupt Enable R/W 0 BIT 6 Change of SD Condition Interrupt Enable R/W 0 BIT 5 Detection of REI-L Error Interrupt Enable R/W 0 BIT 4 Detection of B2 Error Interrupt Enable R/W 0 BIT 3 Detection of B1 Error Interrupt Enable R/W 0 BIT 2 Change of LOF Condition Interrupt Enable R/W 0 BIT 1 Change of SEF Condition Interrupt Enable R/W 0 BIT 0 Change of LOS Condition Interrupt Enable R/W 0 BIT NUMBER 7 NAME Change of SF Condition Interrupt Enable TYPE R/W DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Failure (SF) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block either declares or clears the SF defect. 0 - Disables the "Change of SF Condition Interrupt". 1 - Enables the "Change of SF Condition Interrupt". 6 Change of SD Condition Interrupt Enable R/W Change of Signal Degrade (SD) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Degrade (SD) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block either declares or clears the SD defect. 0 - Disables the "Change of SD Condition Interrupt". 1 - Enables the "Change of SD Condition Interrupt". 5 Detection of REI-L Interrupt Enable R/W Detection of Line - Remote Error Indicator Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Declaration of Line - Remote Error Indicator" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block declares the "REI-L" defect. 0 - Disables the "Line - Remote Error Indicator" Interrupt. 1 - Enables the "Line - Remote Error Indicator" Interrupt. 4 Detection of B2 Error Interrupt Enable R/W Detection of B2 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B2 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block detects a B2 error. 0 - Disables the "Detection of B2 Error Interrupt". 1 - Enables the "Detection of B2 Error Interrupt". 3 Detection of B1 Error Interrupt Enable R/W Detection of B1 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B1 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block detects a B1 error. 0 - Disables the "Detection of B1 Error Interrupt". 1 - Enables the "Detection of B1 Error Interrupt". 160 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Change of LOF Condition Interrupt Enable R/W Change of Loss of Frame (LOF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Receive STS-3 TOH Processor block declares the "LOF" condition. * When the Receive STS-3 TOH Processor clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 2 1 Change of SEF Condition Interrupt Enable R/W Change of SEF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of SEF Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Receive STS-3 TOH Processor block declares the "SEF" condition. * When the "SEF" condition. Receive STS-3 TOH Processor block clears the 0 - Disables the "Change of SEF Condition Interrupt". 1 - Enables the "Change of SEF Condition Interrupt". 0 Change of LOS Condition Interrupt Enable R/W Change of Loss of Signal (LOS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Receive STS-3 TOH Processor block declares the "LOF" condition. * When the Receive STS-3 TOH Processor block clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 161 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 83: Receive STS-3 Transport - B1 Error Count Register - Byte 3 (Address Location= 0x1110) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[31:24] BIT NUMBER 7-0 NAME B1_Error_Count [31:24] TYPE RUR B1 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the B1 Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2.If the B1 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 84: Receive STS-3 Transport - B1 Error Count Register - Byte 2 (Address Location= 0x1111) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[23:16] BIT NUMBER 7-0 NAME B1_Error_Count [23:16] TYPE RUR DESCRIPTION B1 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the B1 Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2.If the B1 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. 162 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 85: Receive STS-3 Transport - B1 Error Count Register - Byte 1 (Address Location= 0x1112) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[15:8] BIT NUMBER 7-0 NAME B1_Error_Count [15:8] TYPE RUR DESCRIPTION B1 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the B1 Error Type is configured to be "bit errors", then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2.If the B1 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 86: Receive STS-3 Transport - B1 Error Count Register - Byte 0 (Address Location= 0x1113) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[7:0] BIT NUMBER 7-0 NAME B1_Error_Count [7:0] TYPE RUR B1 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the B1 Error Type is configured to be "bit errors", then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2.If the B1 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. 163 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 87: Receive STS-3 Transport - B2 Error Count Register - Byte 3 (Address Location= 0x1114) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[31:24] BIT NUMBER 7-0 NAME B2_Error_Count [31:24] TYPE RUR B2 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-3 Transport - B2 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1.If the B2 Error Type is configured to be "bit errors", then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2.If the B2 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 88: Receive STS-3 Transport - B2 Error Count Register - Byte 2 Address Location= 0x1115) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[23:16] BIT NUMBER 7-0 NAME B2_Error_Count [23:16] TYPE RUR DESCRIPTION B2 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-3 Transport - B2 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1.If the B2 Error Type is configured to be "bit errors", then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2.If the B2 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. 164 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 89: Receive STS-3 Transport - B2 Error Count Register - Byte 1 (Address Location= 0x1116) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[15:8] BIT NUMBER 7-0 NAME B2_Error_Count [15:8] TYPE RUR DESCRIPTION B2 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive STS-3 Transport - B2 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 90: Receive STS-3 Transport - B2 Error Count Register - Byte 0 (Address Location= 0x1117) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[7:0] BIT NUMBER 7-0 NAME B2_Error_Count[7:0] TYPE RUR B2 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. 165 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 91: Receive STS-3 Transport - REI-L Error Count Register - Byte 3 (Address Location= 0x1118) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[31:24] BIT NUMBER 7-0 NAME REI_L_Error_Count [31:24] TYPE RUR REI-L Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 92: Receive STS-3 Transport - REI_L Error Count Register - Byte 2 (Address Location= 0x1119) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[23:16] BIT NUMBER 7-0 NAME REI_L_Error_Count [23:16] TYPE RUR DESCRIPTION REI-L Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 166 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 93: Receive STS-3 Transport - REI_L Error Count Register - Byte 1 (Address Location= 0x111A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[15:8] BIT NUMBER 7-0 NAME REI_L_Error_Count[15:8] TYPE RUR DESCRIPTION REI-L Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line -Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 94: Receive STS-3 Transport - REI_L Error Count Register - Byte 0 (Address Location= 0x111B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_L_Error_Count[7:0] TYPE RUR REI-L Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 167 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 95: Receive STS-3 Transport K1 Value (Address Location= 0x111F) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 Filtered_K1_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K1_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K1 value, that the Receive STS-3 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. Table 96: Receive STS-3 Transport K2 Value (Address Location= 0x1123) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Filtered_K2_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K2_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K2 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K2 value, that the Receive STS-3 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. 168 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 97: Receive STS-3 Transport S1 Value (Address Location= 0x1127) BIT 7 R/O 0 BIT NUMBER 7-0 BIT 6 R/O 0 NAME Filtered_S1_Value[7:0] BIT 5 R/O 0 TYPE R/O BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 DESCRIPTION Filtered/Accepted S1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" S1 value that the Receive STS-3 TOH Processor block has received. These bit-fields are valid if it has been received for 8 consecutive STS-3 frames. BIT 1 R/O 0 BIT 0 R/O 0 Filtered_S1_Value[7:0] Table 98: Receive STS-3 Transport - In-Sync Threshold Value (Address Location=0x112B) BIT 7 R/O 0 BIT NUMBER 7-5 4-3 BIT 6 Unused R/O 0 NAME Unused FRPATOUT [1:0] R/O 0 TYPE R/O R/W Framing Pattern - SEF Declaration Criteria: These two READ/WRITE bit-fields permit the user to define the SEF Declaration criteria for the Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Declaration Criteria are presented below. FRPATOUT[1:0] 00 01 SEF Declaration Criteria The Receive STS-3 TOH Processor block will declare an SEF condition if either of the following conditions are true for four consecutive SONET frame periods. * * BIT 5 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION BIT 1 R/W 0 BIT 0 Unused R/O 0 FRPATOUT[1:0] FRPATIN[1:0] If the last (of the 3) A1 bytes, in the STS-3 data stream is erred, or If the first (of the 3) A2 bytes, in the STS-3 data stream, is erred. Hence, for this selection, a total of 16 bits are evaluated for SEF declaration. 10 The Receive STS-3 TOH Processor block will declare an SEF condition if either of the following conditions are true for four consecutive SONET frame periods. * * If the last two (of the 3) A1 bytes, in the STS-3 data stream, are erred, or If the first two (of the 3) A2 bytes, in the STS-3 data stream, are erred. Hence, for this selection, a total of 32 bits are evaluated for SEF declaration. 169 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 11 20 0 Rev2...0...0 200 The Receive STS-3 TOH Processor block will declare an SEF condition if either of the following conditions are true for four consecutive SONET frame periods. * * If the last three (of the 3) A1 bytes, in the STS-3 data stream, are erred, or If the first three (of the 3) A2 bytes, in the STS-3 data stream, are erred. Hence, for this selection, a total of 48 bits are evaluated for SEF declaration. 2-1 FRPATIN [1:0] R/W Framing Pattern - SEF Clearance Criteria: These two READ/WRITE bit-fields permit the user to define the "SEF Clearance" criteria for the Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Clearance Criteria are presented below. FRPATIN[1:0] 00 01 SEF Clearance Criteria The Receive STS-3 TOH Processor block will clear the SEF condition if both of the following conditions are true for two consecutive SONET frame periods. * * If the last (of the 3) A1 bytes, in the STS-3 data stream is un-erred, and If the first (of the 3) A2 bytes, in the STS-3 data stream, is un-erred. Hence, for this selection, a total of 16 bits/frame are evaluated for SEF clearance. 10 The Receive STS-3 TOH Processor block will clear the SEF condition if both of the following conditions are true for two consecutive SONET frame periods. * * If the last two (of the 3) A1 bytes, in the STS-3 data stream, are un-erred, and If the first two (of the 3) A2 bytes, in the STS-3 data stream, are un-erred. Hence, for this selection, a total of 32 bits/frame are evaluated for SEF clearance. 11 The Receive STS-3 TOH Processor block will clear the SEF condition if both of the following conditions are true for two consecutive SONET frame periods. * * If the last three (of the 3) A1 bytes, in the STS-3 datastream, are un-erred, and If the first three (of the 3) A2 bytes, in the STS-3 data stream, are un-erred. Hence, for this selection, a total of 48 bits/frame are evaluated for SEF declaration. 0 Unused R/O 170 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 99: Receive STS-3 Transport - LOS Threshold Value - MSB (Address Location= 0x112E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 LOS_THRESHOLD[15:8] BIT NUMBER 7-0 NAME LOS_THRESHOLD[15:8] TYPE R/W DESCRIPTION LOS Threshold Value - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - LOS Threshold Value - LSB" register specify the number of consecutive (All Zero) bytes that the Receive STS-3 TOH Processor block must detect before it can declare an LOS condition. Table 100: Receive STS-3 Transport - LOS Threshold Value - LSB (Address Location= 0x112F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 LOS_THRESHOLD[7:0] BIT NUMBER 7-0 NAME LOS_THRESHOLD[7:0] TYPE R/W DESCRIPTION LOS Threshold Value - LSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - LOS Threshold Value - MSB" register specify the number of consecutive (All Zero) bytes that the Receive STS-3 TOH Processor block must detect before it can declare an LOS condition. 171 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 101: Receive STS-3 Transport - Receive SF SET Monitor Interval - Byte 2 (Address Location= 0x1131) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_SET_MONITOR_ WINDOW [23:16] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into the "Receive STS-3 Transport SF SET Threshold" register, then an SF condition will be declared. Table 102: Receive STS-3 Transport - Receive SF SET Monitor Interval - Byte 1 (Address Location= 0x1132) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL (Bits 15 through 8): These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SF SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-3 Transport SF SET Threshold" register, then an SF condition will be declared. 172 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 103: Receive STS-3 Transport - Receive SF SET Monitor Interval - Byte 0 (Address Location= 0x1133) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[7:0] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SF SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-3 Transport SF SET Threshold" register, then an SF condition will be declared. Table 104: Receive STS-3 Transport - Receive SF SET Threshold - Byte 1 (Address Location= 0x1136) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SF SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to declare an SF (Signal Failure) condition. When the Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-3 Transport SF SET Threshold - Byte 0" register, then an SF condition will be declared. 173 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 105: Receive STS-3 Transport - Receive SF SET Threshold - Byte 0 Address Location= 0x1137) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[7: 0] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS3 Transport - SF SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to declare an SF (Signal Failure) condition. When the Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-3 Transport SF SET Threshold - Byte 1" register, then an SF condition will be declared. Table 106: Receive STS-3 Transport - Receive SF CLEAR Threshold - Byte 1 (Address Location= 0x113A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [15:8] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SF CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to clear the SF (Signal Failure) condition. When the Receive STS-3 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-3 Transport SF CLEAR Threshold - Byte 0" register, then an SF condition will be cleared. 174 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 107: Receive STS-3 Transport - Receive SF CLEAR Threshold - Byte 0 (Address Location= 0x113B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [7:0] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SF CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to clear the SF (Signal Failure) condition. When the Receive STS-3 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-3 Transport SF CLEAR Threshold - Byte 1" register, then an SF condition will be cleared. Table 108: Receive STS-3 Transport - Receive SD Set Monitor Interval - Byte 2 (Address Location= 0x113D) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-3 Transport SD SET Threshold" register, then an SD condition will be declared. 175 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 109: Receive STS-3 Transport - Receive SD Set Monitor Interval - Byte 1 (Address Location= 0x113E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW[15:8] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-3 Transport SD SET Threshold" register, then an SD condition will be declared. Table 110: Receive STS-3 Transport - Receive SD Set Monitor Interval - Byte 0 (Address Location= 0x113F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW[ 7:0] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-3 Transport SD SET Threshold" register, then an SD condition will be declared. 176 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 111: Receive STS-3 Transport - Receive SD SET Threshold - Byte 1 (Address Location= 0x1142) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to declare an SD (Signal Degrade) condition. When the Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-3 Transport SD SET Threshold - Byte 0" register, then an SD condition will be declared. Table 112: Receive STS-3 Transport - Receive SD SET Threshold - Byte 0 (Address Location= 0x1143) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to declare an SD (Signal Degrade) condition. When the Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-3 Transport SD SET Threshold - Byte 1" register, then an SD condition will be declared. 177 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 113: Receive STS-3 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0x1146) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD[15:8] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) condition. When the Receive STS-3 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-3 Transport SD CLEAR Threshold - Byte 0" register, then an SD condition will be cleared. Table 114: Receive STS-3 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0x1147) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-3 Transport - SD CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) condition. When the Receive STS-3 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-3 Transport SD CLEAR Threshold - Byte 1" register, then an SD condition will be cleared. 178 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 115: Receive STS-3 Transport - Force SEF Condition Register (Address Location= 0x114B) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 SEF FORCE R/W 0 BIT NUMBER 7-1 0 NAME Unused SEF FORCE TYPE R/O R/W SEF Force: DESCRIPTION This READ/WRITE bit-field permits the user to force the Receive STS-3 TOH Processor block to declare an SEF defect. The Receive STS-3 TOH Processor block will then attempt to reacquire framing. Writing a "1" into this bit-field configures the Receive STS-3 TOH Processor block to declare the SEF defect. The Receive STS-3 TOH Processor block will automatically set this bit-field to "0" once it has reacquired framing (e.g., has detected two consecutive STS-3 frames with the correct A1 and A2 bytes). Table 116: Receive STS-3 Transport - Receive J0 Trace Buffer Control Register (Address Location= 0x114F) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 READ SEL R/W 0 BIT 3 ACCEPT THRD R/W 0 BIT 2 MSG TYPE R/W 0 BIT 1 BIT 0 MSG LENGTH R/W 0 R/W 0 BIT NUMBER 7-5 4 NAME Unused READ SEL TYPE R/O R/W DESCRIPTION Receive Section Trace (J0) Message Buffer Read Selection: This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. a. b. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive Section Trace (J0) Message Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive Section Trace (J0) Message Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Receive STS-3 TOH Processor block, the "Receive J0 Trace Buffer" is located at Address location 0x1300 through 0x133F. 3 ACCEPT THRD R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-3 TOH Processor block must receive a given 179 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Section Trace Message, before it is accepted, as described below. 0 - The Receive STS-3 TOH Processor block accepts the Section Message after it has received it the third time in succession. 1 - The Receive STS-3 TOH Processor block accepts the Section Message after it has received in the fifth time in succession. 2 MSG TYPE R/W Message Alignment Type: This READ/WRITE bit-field permits a user to specify how the Receive STS-3 TOH Processor block will locate the boundary of the incoming Section Trace Message, as indicated below. 0 - The Section Trace Message boundary is indicated by "Line Feed". 1 - The Section Trace Message boundary is indicated by the presence of a "1" in the MSB of a the first byte (within the J0 Trace Message). 1-0 MSG LENGTH R/W J0 Message Length: These READ/WRITE bit-fields permit the user to specify the length of the J0 Trace Message, that the Receive STS-3 TOH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J0 Trace Message Length is presented below. MSG LENGTH 00 01 10/11 Resulting J0 Trace Message Length 1 Byte 16 Bytes 64 Bytes 20 0 Rev2...0...0 200 180 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 117: Receive STS-3 Transport - Receive SD Burst Error Tolerance - Byte 1 (Address Location= 0x1152) BIT 7 R/W 1 BIT NUMBER 7-0 BIT 6 R/W 1 NAME SD_BURST_TOLERANCE [15:8] BIT 5 R/W 1 BIT 4 R/W 1 TYPE R/W BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 DESCRIPTION SD_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SD BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. BIT 0 R/W 1 SD_BURST_TOLERANCE[15:8] Table 118: Receive STS-3 Transport - Receive SD Burst Error Tolerance - Byte 0 (Address Location= 0x1153) BIT 7 R/W 1 BIT NUMBER 7-0 BIT 6 R/W 1 NAME SD_BURST_TOLERANCE [7:0] BIT 5 R/W 1 BIT 4 R/W 1 TYPE R/W BIT 3 R/W 1 BIT 2 R/W 1 DESCRIPTION SD_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SD BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. BIT 1 R/W 1 BIT 0 R/W 1 SD_BURST_TOLERANCE[7:0] Table 119: Receive STS-3 Transport - Receive SF Burst Error Tolerance - Byte 1 (Address Location= 0x1156) 181 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 20 0 Rev2...0...0 200 BIT 0 R/W 1 SF_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SF_BURST_TOLERANCE[15:8] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SF BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SF (Signal Failure) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SF defect condition. 182 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 120: Receive STS-3 Transport - Receive SF Burst Error Tolerance - Byte 0 (Address Location= 0x1157) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_BURST_TOLERANCE[7:0] BIT NUMBER 7-0 NAME SF_BURST_TOLERANCE[7:0] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SF BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SF (Signal Failure) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SF defect condition. Table 121: Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 2 (Address Location= 0x1159) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_ WINDOW[23:16] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SD Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR SubInterval for SD (Signal Degrade). When the Receive STS-3 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-3 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 122: Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 1 (Address Location= 0x115A) 183 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 20 0 Rev2...0...0 200 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW[15:8] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL through 8: - Bits 15 These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SD Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-3 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-3 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 123: Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 0 (Address Location= 0x115B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW[ 7:0] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SD Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-3 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-3 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 124: Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 2 (Address Location= 0x115D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SF_CLEAR_MONITOR_WINDOW[23:16] 184 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDO W [23:16] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SF Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-3 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-3 Transport SF Clear Threshold" register, then the SF defect will be cleared. Table 125: Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 1 (Address Location= 0x115E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SF Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-3 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-3 Transport SF Clear Threshold" register, then the SF defect will be cleared. Table 126: Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 0 (Address Location= 0x115F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[7:0] 185 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-3 Transport - SF Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-3 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-3 Transport SF Clear Threshold" register, then the SF defect will be cleared. 186 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 127: Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1163) BIT 7 Transmit AIS-P (Downstream) Upon J0 Message Unstable R/W 0 BIT 6 Transmit AIS-P (Downstream) Upon J0 Message Mismatch R/W 0 BIT 5 Transmit AIS-P (Downstream) Upon SF BIT 4 Transmit AIS-P (Downstream) Upon SD BIT 3 Transmit AIS-P (Downstream) upon Loss of Optical Carrier AIS R/W 0 BIT 2 Transmit AIS-P (Downstream) upon LOF BIT 1 Transmit AIS-P (Downstream) upon LOS BIT 0 Transmit AIS-P (Downstream) Enable R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER NAME TYPE DESCRIPTION Transmit Path AIS upon Detection of Unstable Section Trace (J0): This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AISP) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it detects an Unstable Section Trace (J0) condition in the "incoming" STS-3 data-stream. 0 - Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. 1 - Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 7 Transmit AIS-P (Down-stream) upon J0 Message Unstable R/W 6 Transmit AIS-P (Down-stream) Upon J0 Message Mismatch R/W Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0) Message Mismatch: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it detects a Section Trace (J0) Message Mismatch condition in the "incoming" STS-3 data stream. 0 - Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Message Mismatch" condition. 1 - Configures the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Message Mismatch" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Down-stream) upon SF R/W Transmit Path AIS upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it declares an SF condition. 187 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 0 - Does not configure the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF defect. 1 - Configures the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Down-stream) upon SD R/W Transmit Path AIS upon Signal Degrade (SD): This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it declares an SD condition. 0 - Does not configure the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. 1 - Configures the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 Transmit AIS-P (Down-stream) upon Loss of Optical Carrier R/W Transmit Path AIS upon Loss of Optical Carrier condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it detects a "Loss of Optical Carrier" condition. 0 - Does not configure the Receive STS-3 TOH Processor block to transmit the AIS-P indicator upon detection of a "Loss of Optical Carrier" condition. 1 - Configures the Receive STS-3 TOH Processor block to transmit the AIS-P indicator upon detection of a "Loss of Optical Carrier" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 2 Transmit AIS-P (Down-stream) upon LOF R/W Transmit Path AIS upon Loss of Frame (LOF): This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor block), anytime it declares an LOF condition. 0 - Does not configure the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. 1 - Configures the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to 188 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Down-stream) upon LOS R/W Transmit Path AIS upon Loss of Signal (LOS): This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor block), anytime it declares an LOS condition. 0 - Does not configure the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. 1 - Configures the Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 Transmit AIS-P (Down-stream) Enable R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AIS-P) indicator, via the downstream traffic (e.g., towards the Receive SONET POH Processor blocks), upon detection of an SF, SD, Section Trace Mismatch, Section Trace Unstable, LOF, LOS or Loss of Optical Carrier conditions. It also permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks) anytime it detects an AIS-L condition in the "incoming " STS-3 data-stream. 0 - Configures the Receive STS-3 TOH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of the AIS-L or any of the "above-mentioned" conditions. 1 - Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this register) to "1" in order to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 189 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 128: Receive STS-3 Transport - Serial Port Control Register (Address Location= 0x1167) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 RxTOH_CLOCK_SPEED[7:0] BIT NUMBER 7-4 3-0 NAME Unused RxTOH_CLOCK_SPEED[7:0] TYPE R/O R/W DESCRIPTION RxTOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the "RxTOHClk output clock signal. The formula that relates the contents of these register bits to the "RxTOHClk" frequency is presented below. FREQ = 19.44 /[2 * (RxTOH_CLOCK_SPEED + 1) Note: For STS-3/STM-1 applications, the frequency of the RxTOHClk output signal must be in the range of 0.6075MHz to 9.72MHz Table 129: Receive STS-3 Transport - Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0x116B) BIT 7 Unused BIT 6 Unused BIT 5 Transmit AIS-P (via Downstream STS-1s) upon LOS R/W 0 BIT 4 Transmit AIS-P (via Downstream STS-1s) upon LOF R/W 0 BIT 3 Transmit AIS-P (via Downstream STS-1s) upon SD R/W 0 BIT 2 Transmit AIS-P (via Downstream STS-1s) upon SF R/W 0 BIT 1 AIS-L Output Enable BIT 0 Transmit AIS-P (via Downstream STS-1s) Enable R/W 0 R/O 0 R/O 0 R/W 0 BIT NUMBER 7-6 5 NAME Unused Transmit AIS-P (via Downstream STS-1s) upon LOS TYPE R/O R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of Signal): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOS defect. 0 - Does not configure all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOS defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to 190 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOS defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 1 (Transmit AIS-P Down-stream - Upon LOS), within the Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the LOS defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. 2. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOS), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the LOS defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 4 Transmit AIS-P (via Downstream STS-1s) upon LOF R/W Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of Frame): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOF defect. 0 - Does not configures all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOF defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOF defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 2 (Transmit AIS-P Down-stream - Upon LOF), within the Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the LOF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOF defect. 2. In the case of Bit 2 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the LOS defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 191 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 3 Transmit AIS-P (via Downstream STS-1s) upon SD R/W 20 0 Rev2...0...0 200 Transmit AIS-P (via Downstream STS-1s) upon SD (Signal Degrade): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SD defect. 0 - Does not configures all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SD defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SD defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 4 (Transmit AIS-P Down-stream - Upon SD), within the Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the SD defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. 2. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the SD defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 2 Transmit AIS-P (via Downstream STS-1s) upon SF R/W Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares an SF condition. 0 - Does not configures all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SF defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SF defect. 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 5 (Transmit AIS-P Down-stream - Upon SF), within the Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the SF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the 192 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS NE declaring the SF defect. 2. In the case of Bit 5 (Transmit AIS-P Downstream - Upon SF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the SF defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 1 AIS-L Output Enable R/W AIS-L Output Enable: This READ/WRITE bit-field, along with Bits 7 (8kHz or STUFF Out Enable) within the "Operation Output Control Register - Byte 1" (Address Location= 0x0150) permit the user to configure the "AIS-L" indicator to be output via the "LOF" output pin (pin AD11). If Bit 7 (within the "Operation Output Control Register - Byte 1") is set to "0", then setting this bit-field to "1" configures pin AD11 to function as the AIS-L output indicator. If Bit 7 (within the "Operation Output Control Register - Byte 1") is set to "0", then setting this bit-field to "0" configures pin AD11 to function as the LOF output indicator. If Bit 7 (within the "Operation Output Control Register - Byte 1) is set to "1", then this register bit is ignored. 0 Transmit AIS-P (via Downstream STS-1s) Enable R/W Automatic Transmission of AIS-P (via the downstream STS-1s) Enable: This READ/WRITE bit-field permits the user to configure all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AISP indicator, via its "outbound" STS-1 signals, upon detection of an SF, SD, LOS and LOF condition. 0 - Does not configure the "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P indicator, whenever the Receive STS-3 TOH Processor block declares either the LOS, LOF, SD or SF defects. 1 - Configures the "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P indicator, whenever the Receive STS-3 TOH Processor block declares either the LOS, LOF, SD or SF defects. 193 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.6 TRANSMIT STS-3 TOH PROCESSOR BLOCK 20 0 Rev2...0...0 200 The register map for the Transmit STS-3 TOH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Transmit STS-3 TOH Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "Transmit STS-3 TOH Processor Block "highlighted" is presented below in Figure 7 Figure 7: Illustration of the Functional Block Diagram of the XRT94L33, with the Transmit STS-3 TOH Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 194 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TRANSMIT STS-3 TOH PROCESSOR BLOCK REGISTER 1.6.1 Table 130: Transmit STS-3 TOH Processor Block Registers - Address Map INDIVIDUAL REGISTER ADDRESS 0x00, 0x01 0x02 0x03 0x04 - 0x15 0x16 0x17 0x18 - 0x1D 0x1E 0x1F 0x20 - 0x22 0x23 0x24, 0x25 0x26 0x27 0x28 - 0x2A 0x2B 0x2C, 0x2D 0x2E 0x2F 0x30 - 0x32 0x33 0x34 - 0x36 ADDRESS LOCATION 0x1800 - 0x1901 0x1902 0x1903 0x1904 - 0x1915 0x1916 0x1917 0x1918 - 0x191D 0x191E 0x191F 0x1920 - 0x1921 0x1923 0x1924 - 0x1925 0x1926 0x1927 0x1928 - 0x192A 0x192B 0x192C - 0x192D 0x192E 0x192F 0x1930 - 0x1931 0x1933 0x1934 - 0x1936 Reserved Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 Reserved Reserved Transmit STS-3 Transport - Transmit A1 Byte Error Mask - Low Register - Byte 0 Reserved Reserved Transmit STS-3 Transport - Transmit A2 Byte Error Mask - Low Register - Byte 0 Reserved Transmit STS-3 Transport - B1 Byte Error Mask Register Reserved Reserved Transmit STS-3 Transport - Transmit B2 Byte Error Mask Register - Byte 0 Reserved Transmit STS-3 Transport - Transmit B2 Byte - Bit Error Mask Register - Byte 0 Reserved Transmit STS-3 Transport - K1K2 Byte (APS) Value Register - Byte 1 Transmit STS-3 Transport - K1K2 Byte (APS) Value Register - Byte 0 Reserved Transmit STS-3 Transport - RDI-L Control Register Reserved REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 195 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x37 0x38 - 0x3A 0x3B 0x3C - 0x3E 0x3F 0x40 - 0x42 0x43 0x44 0x45 0x46 0x47 0x48 - 0x4A 0x4B 0x4C - 0x4E 0x4F 0x50 - 0x52 0x53 0x54 - 0xFF ADDRESS LOCATION 0x1937 0x1938 - 0x193A 0x193B 0x193C - 0x193E 0x193F 0x1940 - 0x1942 0x1943 0x1944 0x1945 0x1946 0x1947 0x1948 - 0x194A 0x194B 0x194C - 0x194E 0x194F 0x1950 - 0x1952 0x1953 0x1954 - 0x19FF REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES Transmit STS-3 Transport - M1 Byte Value Register Reserved Transmit STS-3 Transport - S1 Byte Value Register Reserved Transmit STS-3 Transport - F1 Byte Value Register Reserved Transmit STS-3 Transport - E1 Byte Value Register Transmit STS-3 Transport - E2 Byte Control Register Reserved Transmit STS-3 Transport - E2 Byte Pointer Register Transmit STS-3 Transport - E2 Byte Value Register Reserved Transmit STS-3 Transport - Transmit J0 Byte Value Register Reserved Transmit STS-3 Transport - Transmit J0 Byte Control Register Reserved Transmit STS-3 Transport - Serial Port Control Register Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 196 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TRANSMIT STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION 1.6.2 Table 131: Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) BIT 7 Reserved BIT 6 STS-N Overhead Insert R/W 0 BIT 5 E2 Insert Method R/W 0 BIT 4 E1 Insert Method R/W 0 BIT 3 F1 Insert Method R/W 0 BIT 2 S1 Insert Method R/W 0 BIT 1 K1K2 Insert Method R/W 0 BIT 0 M0M1 Insert Method[1] R/W 0 R/O 0 BIT NUMBER 7 6 NAME Unused STS-N Overhead Insert TYPE R/O R/W DESCRIPTION STS-N Overhead Insert (Revision C Silicon Only): This READ/WRITE bit-field permits the user to configure the TxTOH input port to insert the TOH for all lower-tributary STS-1s within the outbound STS-3 signal. 0 - Disables this feature. In this mode, the TxTOH input port will only accept the TOH for the first STS-1 within the outbound STS-3 signal. 1 - Enables this feature. 5 E2 Insert Method R/W E2 Byte Insert Method: This READ/WRITE bit-field permits the user to specify the source of the contents of the E2 byte, within the "transmit" output STS-3 data stream. 0 - E2 Byte is obtained from "TxTOH" Serial Input Port. 1 - E2 Byte is obtained from the contents within the "Transmit STS-3 Transport - E2 Byte Value" register (Address Location= 0xN947). This selection provides the user with software control over the value of the "outbound" E2 byte. 4 E1 Insert Method R/W E1 Byte Insert Method: This READ/WRITE bit-field permits the user to specify the source of the contents of the E1 byte, within the "transmit" output STS-3 data stream. 0 - E1 Byte is obtained from "TxTOH" Serial Input Port. 1 - E1 Byte is obtained from the contents within the "Transmit STS-3 Transport - E1 Byte Value" register (Address Location= 0xN943). This selection provides the user with software control over the value of the "outbound" E1 byte. 3 F1 Insert Method R/W F1 Byte Insert Method: This READ/WRITE bit-field permits the user to specify the source of the contents of the F1 byte, within the "transmit" output STS-3 data stream. 0 - F1 Byte is obtained from "TxTOH" Serial Input Port. 1 - F1 Byte is obtained from the contents within the "Transmit STS-3 Transport - F1 Byte Value" register (Address Location= 0xN93F). This selection provides the user with software control over the value of the "outbound" F1 byte. 2 S1 Insert Method R/W S1 Byte Insert Method: 197 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 This READ/WRITE bit-field permits the user to specify the source of the contents of the S1 byte, within the "transmit" output STS-3 data stream. 0 - S1 Byte is obtained from "TxTOH" Serial Input Port. 1 - S1 Byte is obtained from the contents within the "Transmit STS-3 Transport - S1 Byte Value" register (Address Location= 0xN93B). This selection provides the user with software control over the value of the "outbound" S1 byte. 1 K1K2 Insert Method R/W K1K2 Byte Insert Method: This READ/WRITE bit-field permits the user to specify the source of the contents of the K1 and K2 bytes, within the "transmit" output STS-3 data stream. 0 - K1 and K2 Bytes are obtained from "TxTOH" Serial Input Port. 1 - K1 and K2 Bytes are obtained from the contents within the "Transmit STS-3 Transport - K1K2 Byte Value" register - Byte 1 (Address Location = 0x192E) and the "Transmit STS-3 Transport - K1K2 Byte Value" register - Byte 2 (Address Location= 0x192F). This selection provides the user with software control over the value of the "outbound" K1 and K2 bytes. 0 M0M1 Insert Method[1] R/W M0M1 Insert Method - Bit 1: This READ/WRITE bit-field, along with "M0M1 Insert Method[0]" (located in the "Transmit STS-3 Transport - SONET Control Register - Byte 0") permit the user to specify the source of the contents of the M0/M1 byte, within the "transmit" output STS-3 data stream. The relationship between these two bit-fields and the corresponding source of the M0/M1 byte is presented below. M0M1 Insert Method[1:0] 0 0 0 1 Source of M0/M1 Byte From corresponding STS-1 Receiver (B2 Error Count) Obtained from the contents of the "Transmit STS-3 Transport - M0/M1 Byte Value" register (Address Location= 0xN937). M0/M1 byte is obtained from the "TxTOH" Serial Input Port. From corresponding STS-3 Receiver (B2 Error Count). 1 1 0 1 198 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 132: Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) BIT 7 M0M1 Insert Method[0] R/W 0 BIT 6 Unused R/O 0 BIT 5 RDI-L Force R/W 0 BIT 4 AIS-L Force R/W 0 BIT 3 LOS Force R/W 0 BIT 2 Scramble Enable R/W 0 BIT 1 B2 Error Insert R/W 0 BIT 0 A1A2 Error Insert R/W 0 BIT NUMBER 7 NAME M0M1 Insert Method[0] TYPE R/W DESCRIPTION M0M1 Insert Method - Bit 0: This READ/WRITE bit-field, along with "M0M1 Insert Method[1]" (located in the "Transmit STS-3 Transport - SONET Control Register - Byte 1") permit the user to specify the source of the contents of the M0/M1 byte, within the "transmit" output STS-3 data stream. The relationship between these two bit-fields and the corresponding source of the M0/M1 byte is presented below. M0M1 Insert Method[1:0] 0 0 0 1 Source of M0/M1 Byte From corresponding STS-3 Receiver (B2 Error Count) Obtained from the contents of the "Transmit STS-3 Transport - M0/M1 Byte Value" register (Address Location= 0xN937). M0/M1 byte is obtained from the "TxTOH" Serial Input Port. From corresponding STS-3 Receiver (B2 Error Count). 1 1 6 5 Unused RDI-L Force R/O R/W 0 1 Transmit Line - Remote Defect Indicator: This READ/WRITE bit-field permits the user to (by software control) force the Transmit STS-3 TOH Processor block to generate and transmit the RDI-L indicator to the remote terminal equipment. 0 - Does not configure the Transmit STS-3 TOH Processor block to generate and transmit the RDI-L indicator. 1 - Configures the Transmit STS-3 TOH Processor block to generate and transmit the RDI-L indicator. In this case, the STS-3 Transmitter will force bits 6, 7 and 8 (of the K2 byte) to the value "1, 1, 0". Note: This bit-field is ignored if the Transmit STS-3 TOH Processor block is transmitting the Line AIS (AIS-L) indicator or the LOS pattern. 4 AIS-L Force R/W Transmit Line - AIS Indicator: This READ/WRITE bit-field permits the user to (by software control) force the Transmit STS-3 TOH Processor block to generate and transmit the AIS-L indicator to the remote terminal equipment. 0 - Does not configure the Transmit STS-3 TOH Processor block to 199 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS generate and transmit the AIS-L indicator. 1 - Configures the Transmit STS-3 TOH Processor block to generate and transmit the AIS-L indicator. In this case, the Transmit STS-3 TOH Processor block will force all bits (within the "outbound" STS-3 frame) with the exception of the Section Overhead Bytes to an "All Ones" pattern. Note: 3 LOS Force R/W This bit-field is ignored if the Transmit STS-3 TOH Processor block is transmitting the LOS pattern. 20 0 Rev2...0...0 200 Transmit LOS Pattern: This READ/WRITE bit-field permits the user to (by software control) force the Transmit STS-3 TOH Processor block to transmit the LOS (Loss of Signal) pattern to the remote terminal equipment. 0 - Does not configure the Transmit STS-3 TOH Processor block to generate and transmit the LOS pattern. 1 - Configures the Transmit STS-3 TOH Processor block to transmit the LOS pattern. In this case, the Transmit STS-3 TOH Processor block will force all bytes (within the "outbound" SONET frame) to an "All Zeros" pattern. 2 Scramble Enable R/W Scramble Enable: This READ/WRITE bit-field permits the user to either enable or disable the Scrambler, within the Transmit STS-3 TOH Processor block circuitry 0 - Disables the Scrambler. 1 - Enables the Scrambler. 1 B2 Error Insert R/W Transmit B2 Byte Error Insert Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to insert errors into the "outbound" B2 bytes, per the contents within the "Transmit STS-3 Transport - Transmit B2 Byte Error Mask Registers" 0 - Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the B2 bytes, within the outbound STS-3 signal. 1 - Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 bytes (per the contents within the "Transmit B2 Byte Error Mask Registers"). 0 A1A2 Error Insert R/W Transmit A1A2 Byte Error Insert Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to insert errors into the "outbound" A1 and A2 bytes, per the contents within the "Transmit STS-3 Transport - Transmit A1 Byte Error Mask" and Transmit A2 Byte Error Mask" Registers. 0 - Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the A1 and A2 bytes, within the outbound STS-3 datastream. 1 - Configures the Transmit STS-3 TOH Processor block to insert errors into the A1 and A2 bytes (per the contents within the "Transmit A1 Byte Error Mask" and "Transmit A2 Byte Error Mask" Registers. Table 133: Transmit STS-3 Transport - Transmit A1 Error Mask - Low Register - Byte 0 (Address Location= 0x1917) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 200 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Unused A1 Error in STS-1 Channel 2 R/O 0 R/O 0 R/W 0 A1 Error in STS-1 Channel 1 R/W 0 A1 Error in STS-1 Channel 0 R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused A1 Error in STS-1 Channel # 2 TYPE R/O R/W DESCRIPTION A1 Error in STS-1 Channel # 2: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 2. 0 - Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A1 byte, within STS-1 Channel 2. 1 - Configures the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 2. Note: This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 1 A1 Error in STS-1 Channel # 1 R/W A1 Error in STS-1 Channel # 1: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 1. 0 - Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A1 byte, within STS-1 Channel 1. 1 - Configures the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 1. Note: This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 0 A1 Error in STS-1 Channel # 0 R/W A1 Error in STS-1 Channel # 0: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 0. 0 - Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A1 byte, within STS-1 Channel 0. 1 - Configures the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 0. Note: This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". Table 134: Transmit STS-3 Transport - Transmit A2 Error Mask - Low Register - Byte 0 (Address Location= 0x191F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 201 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Unused A2 Error in STS-1 Channel 2 R/O 0 R/O 0 R/W 0 A2 Error in STS-1 Channel 1 R/W 0 20 0 Rev2...0...0 200 A2 Error in STS-1 Channel 0 R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused TYPE R/O DESCRIPTION A2 Error in STS-1 Channel # 2 R/W A2 Error in STS-1 Channel # 2: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 2. 0 - Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A2 byte, within STS-1 Channel 2. 1 - Configures the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 2. Note: This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 1 A2 Error in STS-1 Channel # 1 R/W A2 Error in STS-1 Channel # 1: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 1. 0 - Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A2 byte, within STS-1 Channel 1. 1 - Configures the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 1. Note: This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 0 A2 Error in STS-1 Channel # 0 R/W A2 Error in STS-1 Channel # 0: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 0. 0 - Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A2 byte, within STS-1 Channel 0. 1 - Configures the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 0. Note: This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 202 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 135: Transmit STS-3 Transport - B1 Byte Error Mask Register (Address Location= 0x1923) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 B1_Byte_Error_Mask[7:0] BIT NUMBER 7-0 NAME B1_Byte_Error_Mask [7:0] TYPE R/W DESCRIPTION B1 Byte Error Mask[7:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the B1 bytes, within the outbound STS-3 data stream. The Transmit STS-3 TOH Processor block will perform an XOR operation with the contents of the B1 byte, and this register. The results of this calculation will be inserted into the B1 byte position within the "outbound" STS-3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the B1 byte will be in error. Note: For normal operation, the user should set this register to 0x00. Table 136: Transmit STS-3 Transport - Transmit B2 Byte Error Mask Register - Byte 0 (Address Location= 0x1927) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 B2 Error in STS-1 Channel 2 R/O 0 R/O 0 R/W 0 BIT 1 B2 Error in STS-1 Channel 1 R/W 0 BIT 0 B2 Error in STS-1 Channel 0 R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused B2 Error in STS-1 Channel # 2 TYPE R/O R/W DESCRIPTION B2 Byte Error in STS-1 Channel # 2: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1 Channel 2. If the user enables this feature, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within STS-1 Channel 2) and the contents of the "Transmit STS-3 Transport - Transmit B2 Bit Error Mask Register - Byte 0 (Address Location= 0x192B). The results of this calculation will be written back into the "B2 byte" position, within STS-1 Channel 2, prior to transmission to the remote terminal. 0 - Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the B2 byte, within STS-1 Channel 2. 1 - Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 byte, within STS-1 Channel 2. Note: This bit-field is only valid if Bit 1 (B2 Error Insert), within the 203 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address = 0x1903) to "1". 1 B2 Error in STS-1 Channel # 1 R/W B2 Byte Error in STS-1 Channel # 1: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1 Channel 1. If the user enables this feature, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within STS-1 Channel 1) and the contents of the "Transmit STS-3 Transport - Transmit B2 Bit Error Mask Register - Byte 0 (Address Location= 0x192B). The results of this calculation will be written back into the "B2 byte" position, within STS-1 Channel 1, prior to transmission to the remote terminal. 0 - Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the B2 byte, within STS-1 Channel 1. 1 - Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 byte, within STS-1 Channel 1. Note: This bit-field is only valid if Bit 1 (B2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 0 B2 Error in STS-1 Channel # 0 R/W B2 Byte Error in STS-1 Channel # 0: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1 Channel 0. If the user enables this feature, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within STS-1 Channel 0) and the contents of the "Transmit STS-3 Transport - Transmit B2 Bit Error Mask Register - Byte 0 (Address Location= 0x192B). The results of this calculation will be written back into the "B2 byte" position, within STS-1 Channel 0, prior to transmission to the remote terminal. 0 - Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the B2 byte, within STS-1 Channel 0. 1 - Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 byte, within STS-1 Channel 0. Note: This bit-field is only valid if Bit 1 (B2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 204 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 137: Transmit STS-3 Transport - Transmit B2 Bit Error Mask Register - Byte 0 (Address Location= 0x192B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_B2_Error_Mask[7:0] BIT NUMBER 7-0 NAME Transmit_B2_Error_Mask[7:0] TYPE R/W DESCRIPTION Transmit B2 Error Mask Byte: These READ/WRITE bit-fields permit the user to specify exact which bits, within the "selected" B2 byte (within the outbound STS-3 signal) will be erred. If the user configures the Transmit STS-3 TOH Processor block to transmit one or more erred B2 bytes, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within the "selected" STS-1 Channel) and the contents of this register. The results of this calculation will be written back into the "B2 byte" position within the "selected" STS-1 Channel, prior to transmission to the remote terminal. The user can select which STS-1 channels (within the outbound STS-3 signal) will contain the "erred" B2 byte, by writing the appropriate data into the "Transmit STS-3 Transport - Transmit B2 Byte Error Mask Register - Bytes 1 and 0 (Address Location= 0x1927). Note: This bit-field is only valid if Bit 1 (B2 Error Insert), within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location= 0x1903) to "1". 205 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 138: Transmit STS-3 Transport - K1K2 (APS) Value Register - Byte 1 (Address Location= 0x192E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_K2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_K2_Byte_Value[7:0] TYPE R/W DESCRIPTION Transmit K2 Byte Value: If the appropriate "K1K2 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the K2 byte, within the "outbound" STS-3 signal. If Bit 1 (K1K2 Insert Method) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) is set to "1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "K2" byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if Bit 1 (K1K2 Insert Method) is set to "0". Table 139: Transmit STS-3 Transport - K1K2 (APS) Value Register - Byte 0 (Address Location= 0x192F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_K1_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_K1_Byte_Value[7:0] TYPE R/W Transmit K1 Byte Value: DESCRIPTION If the appropriate "K1K2 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the K1 byte, within the "outbound" STS-3 signal. If Bit 1 (K1K2 Insert Method) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) is set to "1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "K1" byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if Bit 1 (K1K2 Insert Method) is set to "0". 206 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 140: Transmit STS-3 Transport - RDI-L Control Register (Address Location= 0x1933) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 External RDIL Enable R/O 0 R/O 0 R/W 0 BIT 2 Transmit RDI-L upon AIS-L R/W 0 BIT 1 Transmit RDIL upon LOF R/W 0 BIT 0 Transmit RDIL upon LOS R/W 0 R/O 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused External RDI-L Enable TYPE R/O R/W DESCRIPTION External RDI-L Insertion Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor to accept data via the "TxTOH" input pin, when transmitting the RDI-L indicator to the remote terminal equipment. 0 - Configures the Transmit STS-3 TOH Processor block to internally generate the RDI-L indicator, when appropriate. 1 - Configure the Transmit STS-3 TOH Processor block accept data via the "TxTOH" input pin, when transmitting the RDI-L indicator. 2 Transmit RDI-L upon AIS-L R/W Transmit Line Remote Defect Indicator (RDI-L) upon Detection of AIS-L: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to automatically transmit a RDI-L indicator to the remote terminal anytime (and for the duration) that the corresponding Receive STS-3 TOH Processor is declaring the Line AIS (AIS-L) defect condition. 0 - Configures the Transmit STS-3 TOH Processor block to NOT automatically transmit the RDI-L indicator, whenever (and for the duration that) the corresponding Receive STS-3 TOH Processor block is declaring the AIS-L defect condition. 1 - Configures the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator, whenever (and for the duration that) the corresponding Receive STS-3 TOH Processor block declares the AIS-L defect condition. 1 Transmit RDI-L upon LOF R/W Transmit Line Remote Defect Indicator (RDI-L) upon Detection of LOF: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to automatically transmit a RDI-L indicator to the remote terminal anytime (and for the duration) that the corresponding Receive STS-3 TOH Processor block is declaring the LOF defect. 0 - Configures the Transmit STS-3 TOH Processor to NOT automatically transmit the RDI-L indicator, whenever the corresponding Receive STS-3 TOH Processor block declares the LOF defect. 1 - Configures the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator, whenever (and for the duration that) the corresponding Receive STS-3 TOH Processor block declares the LOF defect. 207 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 Transmit RDI-L upon LOS R/W 20 0 Rev2...0...0 200 Transmit Line Remote Defect Indicator (RDI-L) upon Detection of LOS: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator to the remote terminal anytime (and for the duration) that the corresponding Receive STS-3 TOH Processor block is declaring the LOS defect. 0 - Configures the Transmit STS-3 TOH Processor block to NOT automatically transmit the RDI-L indicator, whenever the corresponding Receive STS-3 TOH Processor block declares the LOS defect. 1 - Configures the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator, whenever (and for the duration that) the corresponding Receive STS-3 TOH Processor block declares the LOS defect. 208 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 141: Transmit STS-3 Transport - M0M1 Byte Value Register (Address Location= 0x1937) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_M0M1_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_M0M1_Byte_Value [7:0] TYPE R/W DESCRIPTION Transmit M0M1 Byte Value: If the appropriate "M0M1 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the M0M1 byte, within the "outbound" STS-3 signal. If Bit 0 (M0M1 Insert Method - Bit 1) within the Transmit STS3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) and Bit 7 (M0M1 Insert Method - Bit 0) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 0 (Address Location=0x1903) is set to "0, 1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "M0M1" byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if the M0M1 Insert Method[1:0] bits are set to any value other than "0, 1". Table 142: Transmit STS-3 Transport - S1 Byte Value Register (Address Location= 0x193B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_S1_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_S1_Byte_Value[7:0] TYPE R/W Transmit S1 Byte Value: DESCRIPTION If the appropriate "S1 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the S1 byte, within the "outbound" STS-3 signal. If Bit 2 (S1 Insert Method) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) is set to "1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "S1" byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if Bit 2 (S1 Insert Method) is set to "0". 209 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 143: Transmit STS-3 Transport - F1 Byte Value Register (Address Location= 0x193F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 Transmit_F1_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_F1_Byte_Value[7:0] TYPE R/W DESCRIPTION Transmit F1 Byte Value: If the appropriate "F1 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the F1 byte, within the "outbound" STS-3 signal. If Bit 3 (F1 Insert Method) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) is set to "1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "F1" byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if Bit 3 (F1 Insert Method) is set to "0". Table 144: Transmit STS-3 Transport - E1 Byte Value Register (Address Location= 0x1943) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_E1_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_E1_Byte_Value[7:0] TYPE R/W DESCRIPTION Transmit E1 Byte Value: If the appropriate "E1 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the E1 byte, within the "outbound" STS-3 signal. If Bit 4 (E1 Insert Method) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) is set to "1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "E1" byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if Bit 4 (E1 Insert Method) is set to "0". 210 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 145: Transmit STS-3 Transport - E2 Byte Control Register (Address Location= 0x1944) BIT 7 Enable All STS-1s R/W 0 R/O 0 R/O 0 R/O 0 BIT 6 BIT 5 BIT 4 BIT 3 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 2 BIT 1 BIT 0 BIT NUMBER 7 NAME Enable All STS-1s TYPE R/W Enable All STS-1s: DESCRIPTION This READ/WRITE bit-field permits the user to implement either of the following configurations options for software control of the E2 byte value, within the outbound STS-3 signal. 0 - Configures the Transmit STS-3 TOH Processor block to read out the contents o the "Transmit STS-3 Transport - E2 Byte Value" register and load that value into the E2 byte (within STS-1 # 1) within the outbound STS-3 signal. 1 - Configures the Transmit STS-3 TOH Processor block to read out the contents of the 3 "shadow" registers, and to load these values into the E2 byte positions, within each corresponding STS-1 signal; within the outbound STS-3 signal. Note: This register bit is ignored if Bit 5 (E2 Insert Method) within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1" (Address Location= 0x1902) is set to "0". 6-0 Unused R/O 211 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 146: Transmit STS-3 Transport - E2 Pointer Register (Address Location= 0x1946) BIT 7 BIT 6 BIT 5 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/W 0 R/W 0 BIT 3 BIT 2 BIT 1 BIT 0 20 0 Rev2...0...0 200 E2_Pointer[1:0] R/W 0 R/W 0 BIT NUMBER 7-2 1-0 NAME Unused E2_Pointer[1:0] TYPE R/O R/W E2 Pointer[3:0]: DESCRIPTION These READ/WRITE bit-fields permit the user to uniquely identify one of the 3 STS-1 E2 byte "shadow" registers, when performing read or write operations to these registers. If the user has set Bit 7 (Enable All STS-1s), within this register to "1", then the contents of these four register bits, act as a pointer to a given "shadow" register. Once the user specifies this pointer value; then he/she completes the read or write operation (to or from the "shadow" register) by performing a read or write to the "Transmit STS-3 Transport - E2 Byte Value" register (Address Location= 0x1947). Valid "shadow" pointer values range from "0x00" to "0x02" (where the pointer value of "0x00" corresponds to the E2 "shadow" register, corresponding to STS-1 # 1; and so on). Note: This register bit is ignored if Bit 7 (Enable All STS-1s) is set to "1"; or if Bit 5 (E2 Insert Method) within the "Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1" (Address Location= 0x1902) is set to "0". 212 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 147: Transmit STS-3 Transport - E2 Byte Value Register (Address Location=0x1947) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_E2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit_E2_Byte_Value[7:0] TYPE R/W DESCRIPTION Transmit E2 Byte Value: The exact function of these register bits depends upon whether Bit 7 (Enable All STS-1s) within the "Transmit STS-3 Transport - E2 Byte Control" Register (Address Location= 0x1944) has been set to "0" or "1"; as described below. If "Enable All STS-1s" is set to "0" If the appropriate "E2 Insert Method" is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the E2 byte, within the "outbound" STS-3 signal. More specifically, this value will be loaded into the E2 byte position, within STS-1 # 1 (within the outbound STS-3 signal). If Bit 5 (E2 Insert Method) within the Transmit STS-3 Transport - SONET Transmit Control Register - Byte 1 (Address Location= 0x1902) is set to "1", then the Transmit STS-3 TOH Processor block will load the contents of this register into the "E2" byte-field, within each outbound STS-3 frame. If "Enable All STS-1s" is set to "1" In this mode, these register bit permit the user to have direct READ/WRITE access of the "STS-1 E2 Byte shadow" register; that is being pointed at by the "E2 Pointer[1:0]" value. These register bits are ignored if Bit 5 (E2 Insert Method) is set to "0". 213 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 148: Transmit STS-3 Transport - J0 Byte Value Register (Address Location= 0x194B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 Transmit_J0_Value[7:0] BIT NUMBER 7-0 NAME Transmit_J0_Value[7:0] TYPE R/W Transmit J0 Value Byte: DESCRIPTION These READ/WRITE bits permit a user to specify the value of the J0 byte, that will be transmitted via the Transport Overhead, within the very next STS-3 Frame. Note: This register is only valid if the Transmit STS-3 TOH Processor block is configured to read out the contents from this register and insert it into the J0 byte-field within each outbound STS-3 frame. The user accomplishes this by setting Bits 1 and 0 (J0_TYPE), within the Transmit STS-3 Transport - J0 Byte Control Register (Address Location= 0x194F) to "1, 0". 214 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 149: Transmit STS-3 Transport - Transmitter J0 Control Register (Address Location= 0x194F) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 1 BIT 5 BIT 4 BIT 3 R/W BIT 2 R/W 1 BIT 1 J0_TYPE R/W 0 R/W 0 BIT 0 MSG_LENGTH BIT NUMBER 7-4 3-2 NAME Unused MSG_LENGTH[1:0] TYPE R/O R/W Message Length[1:0]: DESCRIPTION These two READ/WRITE bit-fields permit the user to specify the length of the message that is to be repetitively transmitted via the J0 byte, as depicted below. MSG_LENGTH[1:0] 00 01 10 or 11 1-0 J0_TYPE[1:0] R/W Corresponding Message Length (Bytes) 1 Byte 16 Bytes 64 Bytes Transmit J0 Source[1:0]: These two READ/WRITE bit-fields permit the user to specify the source of the message that will be transported via the J0 byte/message, within the outbound STS-3 data-stream, as depicted below. J0_TYPE[1:0] 00 01 Corresponding Source of J0 Byte/Message. Automatically set the J0 Byte, in each "outbound" STS-3 frame to "0x01". The "Transmit Section Trace Message Buffer". The "Transmit STS-3 Trace Buffer" Memory is located at Address Location 0x1B00 through 0x1B3F. 10 From the "Transmit J0 Value[7:0]" Register. In this setting, the Transmit STS-3 TOH Processor block will read out the contents of the "Transmit J0 Value[7:0]" Register (Address Location= 0x194B), and will insert this value into the J0 byte of each outbound STS-3 frame. 11 From the "TxTOH" Input pin (pin F8). 215 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 150: Transmit STS-3 Transport - Serial Port Control Register (Address Location= 0x1953) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTOH_CLOCK_SPEED[7:0] BIT NUMBER 7-4 3-0 NAME Unused TxTOH_CLOCK_SPEED[7:0] TYPE R/O R/W DESCRIPTION TxTOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permits the user to specify the frequency of the "TxTOHClk output clock signal. The formula that relates the contents of these register bits to the "TxTOHClk" frequency is presented below. FREQ = 19.44 /[2 * (TxTOH_CLOCK_SPEED + 1) Note: For STS-3/STM-1 applications, the frequency of the TxTOHClk output signal must be in the range of 0.6075MHz to 9.72MHz 216 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.7 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK The register map for the Redundant Receive STS-3 TOH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Redundant Receive STS-3 TOH Processor" Block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "Redundant Receive STS-3 TOH Processor Block "highlighted" is presented below in Figure 6 Figure 8: Illustration of the Functional Block Diagram of the XRT94L33, with the Redundant Receive STS-3 TOH Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 217 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.7.1 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 151: Redundant Receive STS-3 TOH Processor Block Control Register - Address Map INDIVIDUAL REGISTER ADDRESS 0x00 - 0x02 0x03 0x04 - 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 ADDRESS LOCATION 0x1600 - 0x1702 0x1703 0x1704 - 0x1705 0x1706 0x1707 0x1708 0x1709 0x170A 0x170B 0x170C 0x170D 0x170E 0x170F 0x1710 0x1711 0x1712 0x1713 0x1714 0x1715 0x1716 Reserved Redundant Receive STS-3 Transport Control Register - Byte 0 Reserved Redundant Receive STS-3 Transport Status Register - Byte 1 Redundant Receive STS-3 Transport Status Register - Byte 0 Reserved Redundant Receive STS-3 Transport Interrupt Status Register - Byte 2 Redundant Receive STS-3 Transport Interrupt Status Register - Byte 1 Redundant Receive STS-3 Transport Interrupt Status Register - Byte 0 Reserved Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 2 Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 1 Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 0 Redundant Receive STS-3 Transport B1 Error Count - Byte 3 Redundant Receive STS-3 Transport B1 Error Count - Byte 2 Redundant Receive STS-3 Transport B1 Error Count - Byte 1 Redundant Receive STS-3 Transport B1 Error Count - Byte 0 Redundant Receive STS-3 Transport B2 Error Count - Byte 3 Redundant Receive STS-3 Transport B2 Error Count - Byte 2 Redundant Receive STS-3 Transport B2 Error Count - Byte 1 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME DEFAULT VALUES 218 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0x1717 0x1718 0x1719 0x171A 0x171B 0x171C 0x171D - 0x171E 0x171F 0x1720 - 0x1722 0x1723 0x1724 - 0x1726 0x1727 0x1728 - 0x172A 0x172B 0x172C, 0x172D 0x172E 0x172F 0x1730 0x1731 0x1732 0x1733 0x1734 - 0x1735 0x1736 0x1737 REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D - 0x1E 0x1F 0x20 - 0x22 0x23 0x24 - 0x26 0x27 0x28 - 0x2A 0x2B 0x2C, 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34, 0x35 0x36 0x37 Redundant Receive STS-3 Transport B2 Error Count - Byte 0 Redundant Receive STS-3 Transport REI-L Error Count - Byte 3 Redundant Receive STS-3 Transport REI-L Error Count - Byte 2 Redundant Receive STS-3 Transport REI-L Error Count - Byte 1 Redundant Receive STS-3 Transport REI-L Error Count - Byte 0 Reserved Reserved Redundant Receive STS-3 Transport K1 Byte Value Reserved Redundant Receive STS-3 Transport K2 Byte Value Reserved Redundant Receive STS-3 Transport S1 Byte Value Reserved Redundant Receive STS-3 Transport - In-Sync Threshold Value Reserved Redundant Receive STS-3 Transport - LOS Threshold Value - MSB Redundant Receive STS-3 Transport - LOS Threshold Value - LSB Reserved Redundant Receive STS-3 Transport - SF Set Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - SF Set Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - SF Set Monitor Interval - Byte 0 Reserved Redundant Receive STS-3 Transport - SF Set Threshold - Byte 1 Redundant Receive STS-3 Transport - SF Set Threshold - Byte 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 219 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x38, 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40, 0x41 0x42 0x43 0x44, 0x45 0x46 0x47 0x48 - 0x4A 0x4B 0x4C, 0x4E 0x4F 0x50, 0x51 0x52 0x53 0x54, 0x55 0x56 0x57 ADDRESS LOCATION 0x1738, 0x1739 0x173A 0x173B 0x173C 0x173D 0x173E 0x173F 0x1740, 0x1741 0x1742 0x1743 0x1744, 0x1745 0x1746 0x1747 0x1748 - 0x174A 0x174B 0x174C, 0x174E 0x174F 0x1750, 0x1751 0x1752 0x1753 0x1754, 0x1755 0x1756 0x1757 Reserved Redundant Receive STS-3 Transport - SF Clear Threshold - Byte 1 Redundant Receive STS-3 Transport - SF Clear Threshold - Byte 0 Reserved Redundant Receive STS-3 Transport - SD Set Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - SD Set Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - SD Set Monitor Interval - Byte 0 Reserved Redundant Receive STS-3 Transport - SD Set Threshold - Byte 1 Redundant Receive STS-3 Transport - SD Set Threshold - Byte 0 Reserved Redundant Receive STS-3 Transport - SD Clear Threshold - Byte 1 Redundant Receive STS-3 Transport - SD Clear Threshold - Byte 0 Reserved Redundant Condition Reserved Redundant Receive STS-3 Transport - Receive J0 Trace Buffer Control Reserved Redundant Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 1 Redundant Receive STS-3 Transport - SD Burst Error Count Tolerance - Byte 0 Reserved Redundant Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 1 Redundant Receive STS-3 Transport - SF Burst Error Count Tolerance - Byte 0 Receive STS-3 Transport - Force SEF REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 220 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0x1758 0x1759 0x175A 0x175B 0x175C 0x175D 0x175E 0x175F 0x1760 - 0x1762 0x1763 0x1764 - 0x1766 0x1767 0x1768 - 0x176A 0x176B 0x176C - 0x1779 0x117A 0x117B 0x117C 0x117D 0x117E 0x117F 0x1780 - 0x17FF Reserved Redundant Receive STS-3 Transport -Receive SD Clear Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 2 Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 1 Redundant Receive STS-3 Transport - Receive SF Clear Monitor - Byte 0 Reserved Redundant Receive STS-3 Transport - Auto AIS Control Register Reserved Redundant Receive STS-3 Transport - Serial Port Control Register Reserved Redundant Receive STS-3 Transport - Auto AIS (in Downstream STS-1s) Control Register Reserved Redundant Receive STS-3 Transport - TOH Capture Indirect Address Redundant Receive STS-3 Transport - TOH Capture Indirect Address Redundant Receive STS-3 Transport - TOH Capture Indirect Data Redundant Receive STS-3 Transport - TOH Capture Indirect Data Redundant Receive STS-3 Transport - TOH Capture Indirect Data Redundant Receive STS-3 Transport - TOH Capture Indirect Data Reserved REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 - 0x62 0x63 0x64 - 0x66 0x67 0x68 - 0x6A 0x6B 0x6C - 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 - 0xFF 0x00 0xFF 0xFF 0xFF 0x00 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 221 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.7.2 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 152: Redundant Receive STS-3 Transport Control Register - Byte 0 (Address Location= 0x1703) BIT 7 STS-N OH Extract R/W 0 BIT 6 SF Detect Enable R/W 0 BIT 5 SD Detect Enable R/W 0 BIT 4 Descramble Disable R/W 0 BIT 3 SDH/ SONET* R/W 0 BIT 2 REI-L Error Type R/W 0 BIT 1 B2 Error Type R/W 0 BIT 0 B1 Error Type R/W 0 BIT NUMBER 7 NAME STS-N OH Extract TYPE R/W DESCRIPTION STS-N Overhead Extract (Revision C Silicon Only): This READ/WRITE bit-field permits the user to configure the RxTOH output port to output the TOH for all lower-tributary STS-1s within the incoming STS-3 signal. 0 - Disables this feature. In this mode, the RxTOH output port will only output the TOH for the first STS-1 within the incoming STS-3 signal. 1 - Enables this feature. 6 SF Detect Enable R/W Signal Failure (SF) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SF Detection by the Redundant Receive STS-3 TOH Processor Block. 0 - SF Detection is disabled. 1 - SF Detection is enabled: 5 SD Detect Enable R/W Signal Degrade (SD) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SD Detection by the Redundant Receive STS-3 TOH Processor Block. 0 - SD Detection is disabled. 1 - SD Detection is enabled. 4 Descramble Disable R/W De-Scramble Disable: This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Redundant Receive STS-3 TOH Processor block. 0 - De-Scrambling is enabled. 1 - De-Scrambling is disabled. 3 SDH/SONET* R/W SDH/SONET Select: This READ/WRITE bit-field permits the user to configure the Redundant Receiver to operate in either the SONET or SDH Mode. 0 - Configures the Redundant Receiver to operate in the SONET Mode. 1 - Configures the Redundant Receiver to operate in the SDH Mode. 2 REI-L Error Type R/W REI-L (Line - Remote Error Indicator) Error Type: This READ/WRITE bit-field permits the user to specify how the "Redundant Receive Transport REI-L Error Count" register is incremented. 0 - Configures the Redundant Receive STS-3 TOH Processor block to count REI-L Bit Errors. 222 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS In this case the "Redundant Receive Transport REI-L Error Count" register will be incremented by the value of the lower nibble within the M0/M1 byte. 1 - Configures the Redundant Receive STS-3 TOH Processor block to count REI-L Frame Errors. In this case the "Redundant Receive Transport REI-L Error Count" register will be incremented each time the STS-3 Redundant Receiver receives a "non-zero" M0/M1 byte. 1 B2 Error Type R/W B2 Error Type: This READ/WRITE bit-field permits the user to specify how the "Redundant Receive Transport B2 Error Count" register is incremented. 0 - Configures the Redundant Receive STS-3 TOH Processor block to count B2 bit errors. In this case, the "Redundant Receive Transport B2 Error Count" register will be incremented by the number of bits, within the B2 value, that is in error. 1 - Configures the Redundant Receive STS-3 TOH Processor block to count B2 frame errors. In this case, the "Redundant Receive Transport B2 Error Count" register will be incremented by the number of erred STS-3 frames. 0 B1 Error Type R/W B1 Error Type: This READ/WRITE bit-field permits the user to specify how the "Redundant Receive Transport B1 Error Count" register is incremented. 0 - Configures the Redundant Receive STS-3 TOH Processor block to count B1 bit errors. In this case, the "Redundant Receive Transport B1 Error Count" register will be incremented by the number of bits, within the B1 value, that is in error. 1 - Configures the Redundant Receive STS-3 TOH Processor block to count B2 bit errors. In this case, the "Redundant Receive Transport B1 Error Count" register will be incremented by the number of erred STS-3 frames. 223 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 153: Redundant Receive STS-3 Transport Status Register - Byte 1 (Address Location= 0x1706) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 J0 Message Mismatch Defect Declared R/O 0 R/O 0 R/O 0 BIT 1 J0 Message Unstable Defect Declared R/O 0 BIT 0 AIS_L Defect Declared R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-3 2 NAME Unused J0 Message Mismatch Defect Declared TYPE R/O R/O DESCRIPTION J0 - Section Trace Mismatch Indicator: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS-3 TOH Processor block is currently declaring the Section Trace Mismatch condition. The Redundant Receive STS-3 TOH Processor block will declare a J0 (Section Trace) Mismatch condition, whenever it accepts a J0 Message that differs from the "Expected J0 Message". 0 - Section Trace Mismatch Condition is NOT declared. 1 - Section Trace Mismatch Condition is currently declared. 1 J0 Message Unstable Defect Declared R/O J0 - Section Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS-3 TOH Processor block is currently declaring the Section Trace Instability condition. The Redundant Receive STS-3 TOH Processor block will declare a J0 (Section Trace) Unstable condition, whenever the "J0 Unstable" counter reaches the value 8. The "J0 Unstable" counter will be incremented for each time that it receives a J0 message that differs from the "Expected J0 Message". The "J0 Unstable" counter is cleared to "0" whenever the Redundant Receive STS-3 TOH Processor block has received a given J0 Message 3 (or 5) consecutive times. Note: Receiving a given J0 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Section Trace Instability condition is NOT declared. 1 - Section Trace Instability condition is currently declared. 0 AIS_L Defect Declared R/O AIS-L (Line AIS) State: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS-3 TOH Processor block is currently detecting an AIS-L (Line AIS) pattern in the incoming STS-3 data stream. AIS-L is declared if bits 6, 7 and 8 (e.g., the Least Significant Bits, within the K2 byte) value the value "1, 1, 1" for five consecutive STS-1 frames. 0 - AIS-L is NOT currently declared. 1 - AIS-L is currently being declared. 224 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 154: Redundant Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1707) BIT 7 RDI-L Defect Declared R/O 0 BIT NUMBER 7 BIT 6 S1 Byte Unstable Defect Declared R/O 0 NAME RDI-L Defect Declared BIT 5 (K1, K2) APS Byte Unstable R/O 0 TYPE R/O BIT 4 SF Defect Declared BIT 3 SD Defect Declared BIT 2 LOF Defect Declared R/O 0 DESCRIPTION RDI-L (Line Remote Defect Indicator) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring a Line-Remote Defect Indicator (RDI-L), in the incoming STS-3 signal. RDI-L is declared when bits 6, 7 and 8 (e.g., the three least significant bits) of the K2 byte contains the "1, 1, 0" pattern in 5 consecutive STS-3 frames. 0 - RDI-L is NOT being declared. 1 - RDI-L is currently being declared. 6 S1 Byte Unstable Defect Declared R/O S1 Byte Unstable Defect Declared Condition: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the "S1 Byte Instability" condition. The Redundant Receive STS-3 TOH Processor block will declare an "S1 Byte Instability" condition whenever the "S1 Byte Unstable Counter" reaches the value 32. The "S1 Byte Unstable Counter" is incremented for each time that the Redundant Receive STS-3 TOH Processor block receives an S1 byte that differs from the previously received S1 byte. The "S1 Byte Unstable Counter" is cleared to "0" when the same S1 byte is received for 8 consecutive STS-3 frames. Note: Receiving a given S1 byte, in 8 consecutive STS-3 frames also sets this bit-field to "0". BIT 1 SEF Defect Declared R/O 0 BIT 0 LOS Defect Declared R/O 0 R/O 0 R/O 0 0 - S1 Instability Condition is NOT declared. 1 - S1 Instability Condition is currently declared. 5 (K1, K2) APS Byte Unstable R/O APS (K1, K2 Byte) Unstable Condition: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the "K1, K2 Byte Unstable" condition. The Redundant Receive STS-3 TOH Processor block will declare a "K1, K2 Byte Unstable" condition whenever the Redundant Receive STS-3 TOH Processor block fails to receive the same set of K1, K2 bytes, in 12 consecutive STS-3 frames. The "K1, K2 Byte Unstable" condition is cleared whenever the Redundant Receive STS-3 TOH Processor block receives a given set of K1, K2 byte values in three consecutive STS-3 frames. 0 - K1, K2 Unstable Condition is NOT currently declared. 1 - K1, K2 Unstable Condition is currently declared. 4 SF Defect Declared R/O SF (Signal Failure) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the SF defect. The SF defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SF Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given 225 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS interval of time) does not exceed the "SF Declaration" threshold. 1 - SF Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SF Declaration" threshold. 3 SD Defect Declared R/O SD (Signal Degrade) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the SD defect. The SD defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SD Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given interval of time) does not exceed the "SD Declaration" threshold. 1 - SD Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SD Declaration" threshold. 2 LOF Defect Declared R/O LOF (Loss of Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring an LOF defect condition. The Redundant Receive STS-3 TOH Processor block will declare an LOF defect condition, if continues to declare the SEF (Severely Errored Frame) condition for 3ms (or 24 SONET frame periods). 0 - LOF is NOT being declared. 1 - LOF is currently being declared. 1 SEF Defect Declared R/O SEF (Severely Errored Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring an SEF condition. The SEF condition is declared, if the "SEF Declaration Criteria"; per the settings of the FRPATOUT[1:0] bits, within the Redundant Receive STS-3 Transport - In-Sync Threshold Value Register (Address Location= 0x172B). 0 - SEF condition is NOT being declared. 1 - SEF condition is currently being declared. 0 LOS Defect Declared R/O LOS (Loss of Signal) Indicator: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring an LOS (Loss of Signal) defect condition. The Redundant Receive STS-3 TOH Processor block will declare an LOS defect condition if it detects "LOS_THRESHOLD[15:0]" consecutive "All Zero" bytes in the incoming STS-3 data stream. Note: The user can set the "LOS_THRESHOLD[15:0]" value by writing the appropriate data into the "Redundant Receive STS-3 Transport - LOS Threshold Value" Register (Address Location= 0x172E and 0x172F). 20 0 Rev2...0...0 200 0 - Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring an LOS defect condition. 1 - Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring an LOS defect condition. 226 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 155: Redundant Receive STS-3 Transport Interrupt Status Register - Byte 2 (Address Location= 0x1709) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Condition Interrupt Status R/O 0 R/O 0 R/O 0 RUR 0 BIT 0 Change of RDI-L Condition Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Condition Interrupt Status TYPE R/O RUR DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of AIS-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of AIS-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of AIS-L by reading the contents of Bit 0 (AIS-L Defect Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 1" (Address Location= 0x1706). 0 Change of RDI-L Condition Interrupt Status RUR Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of RDI-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of RDI-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of RDI-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of RDI-L by reading out the state of Bit 7 (RDI-L Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 0" (Address Location = 0x1707). 227 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 156: Redundant Receive STS-3 Transport Interrupt Status Register - Byte 1 (Address Location= 0x170A) BIT 7 New S1 Byte Interrupt Status BIT 6 Change in S1 Unstable State Interrupt Status BIT 5 Change in J0 Message Unstable State Interrupt Status RUR 0 BIT 4 New J0 Message Interrupt Status BIT 3 Change in J0 Mismatch Condition Interrupt Status BIT 2 Receive TOH CAP DONE Interrupt Status BIT 1 Change in (K1, K2) APS Bytes Unstable State Interrupt Status RUR 0 BIT 0 NEW K1K2 Byte Interrupt Status RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Status TYPE RUR DESCRIPTION New S1 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New S1 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New S1 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New S1 Byte Value" interrupt has occurred since the last read of this register. Note: The user can obtain the value for this most recently accepted value of the S1 byte by reading the "Redundant Receive STS-3 Transport S1 Value" register (Address Location= 0x1727). 6 Change in S1 Byte Unstable State Interrupt Status RUR Change in S1 Byte Unstable State - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 1 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has not occurred since the last read of this register. Note: The user can obtain the current "S1 Unstable" state by reading the contents of Bit 6 (S1 Unstable) within the "Redundant Receive STS-3 Transport Status Register - Byte 0" (Address Location= 0x1707). 5 Change in J0 Message Unstable State Interrupt Status RUR Change of J0 (Section Trace) Message Unstable condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 4 New J0 Message Interrupt Status RUR New J0 Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New J0 Trace Message" interrupt has occurred since the last read of this register. 228 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Indicates that the "New J0 Trace Message Interrupt" has not occurred since the last read of this register. 1 - Indicates that the "New J0 Trace Message Interrupt" has occurred since the last read of this register. Note: The user can read out the contents of the "Receive J0 Trace Buffer", which is located at Address location 0x1300 through 0x133F. 3 Change in J0 Mismatch Condition Interrupt Status RUR Change in J0 - Section Trace Mismatch Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared" or "declared" by reading the state of Bit 2 (J0_MIS) within the "Redundant Receive STS-3 Transport Status Register - Byte 1 (Address Location= 0x1706). 2 Receive TOH CAP DONE Interrupt Status RUR Receive TOH Capture DONE - Interrupt Status: This RESET-upon-READ bit-field indicates whether the "Receive TOH Data Capture" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the "Receive TOH Capture" buffer, it will remain there for one SONET frame period. 0 - Indicates that the "Receive TOH Data Capture" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Receive TOH Data Capture" Interrupt has occurred since the last read of this register. 1 Change in APS (K1, K2 Byte) Unstable Status Interrupt Status RUR Change of APS (K1, K2 Byte) Unstable Condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "K1, K2 Unstable Condition" is being declared or cleared by reading out the contents of Bit 5 (APS Unstable), within the "Redundant Receive STS-3 Transport Status Register - Byte 0" (Address Location = 0x1707). 0 NEW K1K2 Byte Interrupt Status RUR New K1, K2 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New K1, K2 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New K1, K2 Byte Value" Interrupt has occurred since 229 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS the last read of this register. Note: The user can obtain the contents of the new K1 byte by reading out the contents of the "Redundant Receive STS-3 Transport K1 Value" Register (Address Location= 0x171F). Further, the user can also obtain the contents of the new K2 byte by reading out the contents of the "Redundant Receive STS-3 Transport K2 Value" Register (Address Location= 0x1723). 20 0 Rev2...0...0 200 230 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 157: Redundant Receive STS-3 Transport Interrupt Status Register - Byte 0 (Address Location= 0x170B) BIT 7 Change in SF Condition Interrupt Status RUR 0 BIT 6 Change in SD Condition Interrupt Status RUR 0 BIT 5 Detection of REI-L Error Interrupt Status RUR 0 BIT 4 Detection of B2 Error Interrupt Status RUR 0 BIT 3 Detection of B1 Error Interrupt Status RUR 0 BIT 2 Change of LOF Condition Interrupt Status RUR 0 BIT 1 Change of SEF Condition Interrupt Status RUR 0 BIT 0 Change of LOS Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Change in SF Condition Interrupt Status TYPE RUR DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SF Condition Interrupt" has occurred since the last read of this register. 0 - The "Change of SF Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SF Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SF" condition by reading out the state of Bit 4 (SF Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1707). 6 Change of SD Condition Interrupt Status RUR Change of Signal Degrade (SD) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SD Condition Interrupt" has occurred since the last read of this register. 0 - The "Change of SD Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SD Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SD" condition by reading out the state of Bit 3 (SD Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1707). 5 Detection of REIL Interrupt Status RUR Detection of Line - Remote Error Indicator Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Declaration of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 0 - The "Declaration of Line - Remote Error Indicator" Interrupt has NOT occurred since the last read of this register. 1 - The "Declaration of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 4 Detection of B2 Error Interrupt Status RUR Detection of B2 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B2 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B2 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B2 Error Interrupt" has occurred since the last read of 231 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS this register. 3 Detection of B1 Error Interrupt Status RUR Detection of B1 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B1 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B1 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B1 Error Interrupt" has occurred since the last read of this register 2 Change of LOF Interrupt Status RUR Change of Loss of Frame (LOF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOF Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOF Condition" interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOF Condition" interrupt has occurred since the last read of this register. Note: The user can determine the current "LOF" condition by reading out the state of Bit 2 (LOF Defect Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1707). 20 0 Rev2...0...0 200 1 Change of SEF Condition Interrupt Status RUR Change of SEF Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SEF" Condition Interrupt has occurred since the last read of this register. 0 - The "Change of SEF Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of SEF Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "SEF" condition by reading out the state of Bit 1 (SEF Defect Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1707). 0 Change of LOS Condition Interrupt Status RUR Change of Loss of Signal (LOS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOS Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOS Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOS Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "LOS" status by reading out the contents of Bit 0 (LOS Defect Declared) within the Redundant Receive STS-3 Transport Status Register - Byte 0 (Address Location= 0x1707). 232 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 158: Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 2 (Address Location= 0x170D) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Condition Interrupt Enable R/O 0 R/O 0 R/O 0 R/W 0 BIT 0 Change of RDI-L Condition Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Condition Interrupt Enable TYPE R/O R/W DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Redundant Receive STS-3 TOH Processor block declares the "AIS-L" condition. * When the Redundant Receive STS-3 TOH Processor block clears the "AIS-L" condition. 0 - Disables the "Change of AIS-L Condition" Interrupt. 1 - Enables the "Change of AIS-L Condition" Interrupt. Note: The user can determine the current "AIS-L" condition by reading out the state of Bit 0 (AIS-L) within the "Redundant Receive STS3 Transport Status Register - Byte 1" (Address Location= 0x1706). 0 Change of RDI-L Condition Interrupt Enable R/W Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of RDI-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Redundant Receive STS-3 TOH Processor block declares the "RDI-L" condition. * When the Redundant Receive STS-3 TOH Processor block clears the "RDI-L" condition. 0 - Disables the "Change of RDI-L Condition" Interrupt. 1 - Enables the "Change of RDI-L Condition" Interrupt. 233 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 159: Redundant Receive STS-3 Transport Interrupt Enable Register - Byte 1 (Address Location= 0x170E) BIT 7 New S1 Byte Interrupt Enable BIT 6 Change in S1 Byte Unstable State Interrupt Enable R/W 0 BIT 5 Change in J0 Message Unstable State Interrupt Enable R/W 0 BIT 4 New J0 Message Interrupt Enable BIT 3 J0 Mismatch Interrupt Enable BIT 2 Receive TOH CAP DONE Interrupt Enable R/W 0 BIT 1 Change in APS Unstable State Interrupt Enable R/W 0 BIT 0 NEW K1K2 Byte Interrupt Enable R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Enable TYPE R/W DESCRIPTION New S1 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New S1 Byte Value" Interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new S1 byte value. The Redundant Receive STS-3 TOH Processor block will accept a new S1 byte after it has received it for 8 consecutive STS-3 frames. 0 - Disables the "New S1 Byte Value" Interrupt. 1 - Enables the "New S1 Byte Value" Interrupt. 6 Change in S1 Unstable State Interrupt Enable R/W Change in S1 Byte Unstable State Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in S1 Byte Unstable State" Interrupt. If the user enables this bit-field, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. * * When the Redundant Receive STS-3 TOH Processor block declares the "S1 Byte Instability" condition. When the Redundant Receive STS-3 TOH Processor block clears the "S1 Byte Instability" condition. 0 - Disables the "Change in S1 Byte Unstable State" Interrupt. 1 - Enables the "Change in S1 Byte Unstable State" Interrupt. 5 Change in J0 Message Unstable State Interrupt Enable R/W Change of J0 (Section Trace) Message Instability condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of J0 Message Instability Condition" Interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. * * Whenever the Redundant Receive STS-3 TOH Processor block declares the "J0 Message Instability" condition. Whenever the Redundant Receive STS-3 TOH Processor block clears the "J0 Message Instability" condition. 0 - Disable the "Change of J0 Message Instability" Interrupt. 1 - Enables the "Change of J0 Message Instability" Interrupt. 4 New J0 Message R/W New J0 Trace Message Interrupt Enable: 234 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Interrupt Enable This READ/WRITE bit-field permits the user to enable or disable the "New J0 Trace Message" interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new J0 Trace Message. The Redundant Receive STS-3 TOH Processor block will accept a new J0 Trace Message after it has received it 3 (or 5) consecutive times. 0 - Disables the "New J0 Trace Message" Interrupt. 1 - Enables the "New J0 Trace Message" Interrupt. 3 J0 Mismatch Interrupt Enable R/W Change in "J0 - Section Trace Mismatch Condition" interrupt enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in J0 - Section Trace Mismatch condition" interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following events. * * The Redundant Receive STS-3 TOH Processor block declares a "J0 - Section Trace Mismatch" condition. The Redundant Receive STS-3 TOH Processor block clears the "J0 - Section Trace Mismatch" condition. The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared or "declared" by reading the state of Bit 2 (J0 Message Mismatch Defect Declared) within the "Redundant Receive STS-3 Transport Status Register - Byte 1 (Address Location= 0x1706). Note: 2 Receive TOH CAP DONE Interrupt Enable R/W Receive TOH Capture DONE - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive TOH Data Capture" interrupt, within the Redundant Receive STS-3 TOH Processor Block. If this interrupt is enabled, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the "Receive TOH Capture" buffer, it will remain there for one SONET frame period. 0 - Disables the "Receive TOH Capture" Interrupt. 1 - Enables the "Receive TOH Capture" Interrupt. 1 Change in APS Unstable State Interrupt Enable R/W Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of APS (K1, K2 Byte) Instability condition" interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate an Interrupt in response to either of the following events. * * If the Redundant Receive STS-3 TOH Processor block declares a "K1, K2 Instability" condition. If the Redundant Receive STS-3 TOH Processor block clears the "K1, K2 Instability" condition. 0 New K1K2 Byte Interrupt Enable R/W New K1, K2 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New K1, K2 Byte Value" Interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new K1, K2 byte value. The Redundant Receive STS-3 TOH Processor block will accept a new K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-3 frames. 235 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Disables the "New K1, K2 Byte Value" Interrupt. 1 - Enables the "New K1, K2 Byte Value" Interrupt. 20 0 Rev2...0...0 200 236 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 160: Redundant Receive STS-3 Transport Interrupt Status Register - Byte 0 (Address Location= 0x170F) BIT 7 Change of SF Condition Interrupt Enable R/W 0 BIT 6 Change of SD Condition Interrupt Enable R/W 0 BIT 5 Detection of REI-L Error Interrupt Enable R/W 0 BIT 4 Detection of B2 Error Interrupt Enable R/W 0 BIT 3 Detection of B1 Error Interrupt Enable R/W 0 BIT 2 Change of LOF Condition Interrupt Enable R/W 0 BIT 1 Change of SEF Condition Interrupt Enable R/W 0 BIT 0 Change of LOS Condition Interrupt Enable R/W 0 BIT NUMBER 7 NAME Change of SF Condition Interrupt Enable TYPE R/W DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Failure (SF) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block either declares or clears the SF defect. 0 - Disables the "Change of SF Condition Interrupt". 1 - Enables the "Change of SF Condition Interrupt". 6 Change of SD Condition Interrupt Enable R/W Change of Signal Degrade (SD) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Degrade (SD) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block either declares or clears the SD defect. 0 - Disables the "Change of SD Condition Interrupt". 1 - Enables the "Change of SD Condition Interrupt". 5 Detection of REI-L Interrupt Enable R/W Detection of Line - Remote Error Indicator Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Declaration of Line - Remote Error Indicator" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block declares the "REI-L" defect. 0 - Disables the "Line - Remote Error Indicator" Interrupt. 1 - Enables the "Line - Remote Error Indicator" Interrupt. 4 Detection of B2 Error Interrupt Enable R/W Detection of B2 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B2 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block detects a B2 error. 0 - Disables the "Detection of B2 Error Interrupt". 1 - Enables the "Detection of B2 Error Interrupt". 3 Detection of B1 Error Interrupt Enable R/W Detection of B1 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B1 Error" Interrupt. If the user enables this interrupt, then the 237 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block detects a B1 error. 0 - Disables the "Detection of B1 Error Interrupt". 1 - Enables the "Detection of B1 Error Interrupt". 2 Change of LOF Condition Interrupt Enable R/W Change of Loss of Frame (LOF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Redundant Receive STS-3 TOH Processor block declares the "LOF" condition. * When the Redundant Receive STS-3 TOH Processor clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 1 Change of SEF Condition Interrupt Enable R/W Change of SEF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of SEF Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Redundant Receive STS-3 TOH Processor block declares the "SEF" condition. * When the Redundant Receive STS-3 TOH Processor block clears the "SEF" condition. 0 - Disables the "Change of SEF Condition Interrupt". 1 - Enables the "Change of SEF Condition Interrupt". 0 Change of LOS Condition Interrupt Enable R/W Change of Loss of Signal (LOS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. * When the Redundant Receive STS-3 TOH Processor block declares the "LOF" condition. * When the Redundant Receive STS-3 TOH Processor block clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 238 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 161: Redundant Receive STS-3 Transport - B1 Error Count Register - Byte 3 (Address Location= 0x1710) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[31:24] BIT NUMBER 7-0 NAME B1_Error_Count [31:24] TYPE RUR B1 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Redundant Receive Transport - B1 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 162: Redundant Receive STS-3 Transport - B1 Error Count Register - Byte 2 (Address Location= 0x1711) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[23:16] BIT NUMBER 7-0 NAME B1_Error_Count [23:16] TYPE RUR DESCRIPTION B1 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Redundant Receive Transport - B1 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. 239 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 163: Redundant Receive STS-3 Transport - B1 Error Count Register - Byte 1 (Address Location= 0x1712) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[15:8] BIT NUMBER 7-0 NAME B1_Error_Count [15:8] TYPE RUR DESCRIPTION B1 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Redundant Receive Transport - B1 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error Note: 1. If the B1 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 164: Redundant Receive STS-3 Transport - B1 Error Count Register - Byte 0 (Address Location= 0x1713) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[7:0] BIT NUMBER 7-0 NAME B1_Error_Count [7:0] TYPE RUR B1 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Redundant Receive Transport - B1 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 165: Redundant Receive STS-3 Transport - B2 Error Count Register - Byte 3 (Address Location= 0x1714) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 240 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS B2_Error_Count[31:24] RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7-0 NAME B2_Error_Count [31:24] TYPE RUR B2 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Redundant Receive STS-3 Transport - B2 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 166: Redundant Receive STS-3 Transport - B2 Error Count Register - Byte 2 Address Location= 0x1715) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[23:16] BIT NUMBER 7-0 NAME B2_Error_Count [23:16] TYPE RUR DESCRIPTION B2 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Redundant Receive STS-3 Transport - B2 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 167: Redundant Receive STS-3 Transport - B2 Error Count Register - Byte 1 (Address Location= 0x1716) BIT 7 RUR BIT 6 RUR BIT 5 RUR BIT 4 RUR BIT 3 RUR BIT 2 RUR BIT 1 RUR BIT 0 RUR B2_Error_Count[15:8] 241 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 0 0 0 0 0 0 20 0 Rev2...0...0 200 0 BIT NUMBER 7-0 NAME B2_Error_Count [15:8] TYPE RUR DESCRIPTION B2 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Redundant Receive STS-3 Transport - B2 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 168: Redundant Receive STS-3 Transport - B2 Error Count Register - Byte 0 (Address Location= 0x1717) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[7:0] BIT NUMBER 7-0 NAME B2_Error_Count[7:0] TYPE RUR B2 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Redundant Receive Transport - B2 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 169: Redundant Receive STS-3 Transport - REI-L Error Count Register - Byte 3 (Address Location= 0x1718) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[31:24] 242 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT NUMBER 7-0 NAME REI_L_Error_Count [31:24] TYPE RUR REI-L Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Redundant Receive Transport - REI-L Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 170: Redundant Receive STS-3 Transport - REI_L Error Count Register - Byte 2 (Address Location= 0x1719) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[23:16] BIT NUMBER 7-0 NAME REI_L_Error_Count [23:16] TYPE RUR DESCRIPTION REI-L Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Redundant Receive Transport - REI-L Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 171: Redundant Receive STS-3 Transport - REI_L Error Count Register - Byte 1 (Address Location= 0x171A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[15:8] 243 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT NUMBER 7-0 NAME REI_L_Error_Count[15:8] TYPE RUR DESCRIPTION REI-L Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Redundant Receive Transport - REI-L Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line -Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 20 0 Rev2...0...0 200 Table 172: Redundant Receive STS-3 Transport - REI_L Error Count Register - Byte 0 (Address Location= 0x171B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_L_Error_Count [7:0] TYPE RUR REI-L Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Redundant Receive Transport - REI-L Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the value within the REI-L fields of the M1 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Redundant Receive STS-3 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 173: Redundant Receive STS-3 Transport K1 Value (Address Location= 0x171F) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Filtered_K1_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K1_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K1 Value: These READ-ONLY bit-fields contain the value of the most recently 244 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS "filtered" K1 value, that the Redundant Receive STS-3 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. Table 174: Redundant Receive STS-3 Transport K2 Value (Address Location= 0x1723) BIT 7 R/O 0 BIT NUMBER 7-0 BIT 6 R/O 0 NAME Filtered_K2_Value [7:0] BIT 5 R/O 0 TYPE R/O BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 DESCRIPTION Filtered/Accepted K2 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K2 value, that the Redundant Receive STS-3 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. BIT 1 R/O 0 BIT 0 R/O 0 Filtered_K2_Value[7:0] Table 175: Redundant Receive STS-3 Transport S1 Value (Address Location= 0x1727) BIT 7 R/O 0 BIT NUMBER 7-0 BIT 6 R/O 0 NAME Filtered_S1_Value[7:0] BIT 5 R/O 0 TYPE R/O BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 DESCRIPTION Filtered/Accepted S1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" S1 value that the Redundant Receive STS-3 TOH Processor block has received. These bit-fields are valid if it has been received for 8 consecutive STS-3 frames. BIT 1 R/O 0 BIT 0 R/O 0 Filtered_S1_Value[7:0] Table 176: Redundant Location=0x172B) BIT 7 R/O 0 BIT 6 Unused R/O 0 Receive BIT 5 R/O 0 STS-3 BIT 4 R/W 0 Transport BIT 3 R/W 0 - In-Sync BIT 2 R/W 0 Threshold BIT 1 R/W 0 Value (Address BIT 0 FRPATOUT[1:0] FRPATIN[1:0] Unused R/O 0 BIT NUMBER 7-5 4-3 NAME Unused FRPATOUT[1:0] TYPE R/O R/W DESCRIPTION Framing Pattern - SEF Declaration Criteria: These two READ/WRITE bit-fields permit the user to define the SEF 245 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Declaration criteria for the Redundant Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Declaration Criteria are presented below. FRPATOUT[1:0] 00 01 SEF Declaration Criteria The Redundant Receive STS-3 TOH Processor block will declare an SEF condition if either of the following conditions are true for four consecutive SONET frame periods. * * If the last (of the 3) A1 bytes, in the STS-3 data stream is erred, or If the first (of the 3) A2 bytes, in the STS-3 data stream, is erred. Hence, for this selection, a total of 16 bits are evaluated for SEF declaration. 10 The Redundant Receive STS-3 TOH Processor block will declare an SEF condition if either of the following conditions are true for four consecutive SONET frame periods. * * If the last two (of the 3) A1 bytes, in the STS-3 data stream, are erred, or If the first two (of the 3) A2 bytes, in the STS-3 data stream, are erred. Hence, for this selection, a total of 32 bits are evaluated for SEF declaration. 11 The Redundant Receive STS-3 TOH Processor block will declare an SEF condition if either of the following conditions are true for four consecutive SONET frame periods. * * If the last three (of the 3) A1 bytes, in the STS3 data stream, are erred, or If the first three (of the 3) A2 bytes, in the STS3 data stream, are erred. Hence, for this selection, a total of 48 bits are evaluated for SEF declaration. 2-1 FRPATIN[1:0] R/W Framing Pattern - SEF Clearance Criteria: These two READ/WRITE bit-fields permit the user to define the "SEF Clearance" criteria for the Redundant Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Clearance Criteria are presented below. FRPATIN[1:0] 00 SEF Clearance Criteria The Redundant Receive STS-3 TOH Processor bl k ill l h SEF di i if b h f h 246 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS evaluated for SEF clearance. 10 The Redundant Receive STS-3 TOH Processor block will clear the SEF condition if both of the following conditions are true for two consecutive SONET frame periods. * * If the last two (of the 3) A1 bytes, in the STS-3 data stream, are un-erred, and If the first two (of the 3) A2 bytes, in the STS-3 data stream, are un-erred. Hence, for this selection, a total of 32 bits/frame are evaluated for SEF clearance. 11 The Redundant Receive STS-3 TOH Processor block will clear the SEF condition if both of the following conditions are true for two consecutive SONET frame periods. * * If the last three (of the 3) A1 bytes, in the STS-3 data-stream, are un-erred, and If the first three (of the 3) A2 bytes, in the STS3 data stream, are un-erred. Hence, for this selection, a total of 48 bits/frame are evaluated for SEF declaration. 0 Unused R/O 247 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 177: Redundant Receive STS-3 Transport - LOS Threshold Value - MSB (Address Location= 0x172E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 LOS_THRESHOLD[15:8] BIT NUMBER 7-0 NAME LOS_THRESHOLD[15:8] TYPE R/W DESCRIPTION LOS Threshold Value - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - LOS Threshold Value - LSB" register specify the number of consecutive (All Zero) bytes that the Redundant Receive STS-3 TOH Processor block must detect before it can declare an LOS condition. Table 178: Redundant Receive STS-3 Transport - LOS Threshold Value - LSB (Address Location= 0x172F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 LOS_THRESHOLD[7:0] BIT NUMBER 7-0 NAME LOS_THRESHOLD[7:0] TYPE R/W DESCRIPTION LOS Threshold Value - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - LOS Threshold Value - MSB" register specify the number of consecutive (All Zero) bytes that the Redundant Receive STS-3 TOH Processor block must detect before it can declare an LOS condition. 248 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 179: Redundant Receive STS-3 Transport -Receive SF SET Monitor Interval - Byte 2 (Address Location= 0x1731) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_SET_MONITOR_ WINDOW [23:16] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Redundant Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds that of programmed into the "Redundant Receive STS-3 Transport SF SET Threshold" register, then an SF condition will be declared. Table 180: Redundant Receive STS-3 Transport - Receive SF SET Monitor Interval - Byte 1 (Address Location= 0x1732) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL (Bits 15 through 8): These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Redundant Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Redundant Receive STS-3 Transport SF SET Threshold" register, then an SF condition will be declared. 249 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 181: Redundant Receive STS-3 Transport - Receive SF SET Monitor Interval - Byte 0 (Address Location= 0x1733) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[7:0] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Redundant Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Redundant Receive STS-3 Transport SF SET Threshold" register, then an SF condition will be declared. Table 182: Redundant Receive STS-3 Transport - Receive SF SET Threshold - Byte 1 (Address Location= 0x1736) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to declare an SF (Signal Failure) condition. When the Redundant Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Redundant Receive STS-3 Transport SF SET Threshold - Byte 0" register, then an SF condition will be declared. Table 183: Redundant Receive STS-3 Transport - Receive SF SET Threshold - Byte 0 Address Location= 0x1737) 250 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 BIT 7 R/W 1 SF_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[7: 0] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to declare an SF (Signal Failure) condition. When the Redundant Receive STS-3 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Redundant Receive STS-3 Transport SF SET Threshold - Byte 1" register, then an SF condition will be declared. Table 184: Redundant Receive STS-3 Transport - Receive SF CLEAR Threshold - Byte 1 (Address Location= 0x173A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [15:8] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SF (Signal Failure) condition. When the Redundant Receive STS-3 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Redundant Receive STS-3 Transport SF CLEAR Threshold - Byte 0" register, then an SF condition will be cleared. Table 185: Redundant Receive STS-3 Transport - Receive SF CLEAR Threshold - Byte 0 (Address Location= 0x173B) BIT 7 R/W BIT 6 R/W BIT 5 R/W BIT 4 R/W BIT 3 R/W BIT 2 R/W BIT 1 R/W BIT 0 R/W SF_CLEAR_THRESHOLD[7:0] 251 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 1 1 1 1 1 1 20 0 Rev2...0...0 200 1 BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [7:0] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SF (Signal Failure) condition. When the Redundant Receive STS-3 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Redundant Receive STS-3 Transport SF CLEAR Threshold - Byte 1" register, then an SF condition will be cleared. Table 186: Redundant Receive STS-3 Transport - Receive SD Set Monitor Interval - Byte 2 (Address Location= 0x173D) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Redundant Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Redundant Receive STS-3 Transport SD SET Threshold" register, then an SD condition will be declared. Table 187: Redundant Receive STS-3 Transport - Receive SD Set Monitor Interval - Byte 1 (Address Location= 0x173E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[15:8] 252 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW[15:8] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Redundant Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Redundant Receive STS-3 Transport SD SET Threshold" register, then an SD condition will be declared. Table 188: Redundant Receive STS-3 Transport - Receive SD Set Monitor Interval - Byte 0 (Address Location= 0x173F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW[ 7:0] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Redundant Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Redundant Receive STS-3 Transport SD SET Threshold" register, then an SD condition will be declared. Table 189: Redundant Receive STS-3 Transport - Receive SD SET Threshold - Byte 1 (Address Location= 0x1742) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[15:8] BIT NUMBER NAME TYPE DESCRIPTION 253 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 7-0 SD_SET_THRESHOLD[15:8] R/W SD_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to declare an SD (Signal Degrade) condition. When the Redundant Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Redundant Receive STS-3 Transport SD SET Threshold - Byte 0" register, then an SD condition will be declared. 20 0 Rev2...0...0 200 Table 190: Redundant Receive STS-3 Transport - Receive SD SET Threshold - Byte 0 (Address Location= 0x1743) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to declare an SD (Signal Degrade) condition. When the Redundant Receive STS-3 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Redundant Receive STS-3 Transport SD SET Threshold - Byte 1" register, then an SD condition will be declared. 254 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 191: Redundant Receive STS-3 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0x1746) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD[15:8] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) condition. When the Redundant Receive STS-3 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Redundant Receive STS-3 Transport SD CLEAR Threshold - Byte 0" register, then an SD condition will be cleared. Table 192: Redundant Receive STS-3 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0x1747) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) condition. When the Redundant Receive STS-3 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Redundant Receive STS-3 Transport SD CLEAR Threshold - Byte 1" register, then an SD condition will be cleared. Table 193: Redundant Receive STS-3 Transport - Force SEF Condition Register (Address Location= 0x174B) 255 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 SEF FORCE R/W 0 20 0 Rev2...0...0 200 BIT NUMBER 7-1 0 NAME Unused SEF FORCE TYPE R/O R/W SEF Force: DESCRIPTION This READ/WRITE bit-field permits the user to force the Redundant Receive STS-3 TOH Processor block to declare an SEF defect. The Redundant Receive STS-3 TOH Processor block will then attempt to reacquire framing. Writing a "1" into this bit-field configures the Redundant Receive STS-3 TOH Processor block to declare the SEF defect. The Redundant Receive STS-3 TOH Processor block will automatically set this bit-field to "0" once it has reacquired framing (e.g., has detected two consecutive STS-3 frames with the correct A1 and A2 bytes). Table 194: Redundant Receive STS-3 Transport - Receive J0 Trace Buffer Control Register (Address Location= 0x174F) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 READ SEL R/W 0 BIT 3 ACCEPT THRD R/W 0 BIT 2 MSG TYPE R/W 0 BIT 1 BIT 0 MSG LENGTH R/W 0 R/W 0 BIT NUMBER 7-5 4 NAME Unused READ SEL TYPE R/O R/W DESCRIPTION Receive Section Trace (J0) Message Buffer Read Selection: This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. k. l. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive Section Trace (J0) Message Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive Section Trace (J0) Message Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Redundant Receive STS-3 TOH Processor block, the "Receive J0 Trace Buffer" is located at Address location 0x1300 through 0x133F. 3 ACCEPT THRD R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Redundant Receive STS-3 TOH Processor block must receive a given Section Trace Message, before it is accepted, as described below. 256 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - The Redundant Receive STS-3 TOH Processor block accepts the Section Message after it has received it the third time in succession. 1 - The Redundant Receive STS-3 TOH Processor block accepts the Section Message after it has received in the fifth time in succession. 2 MSG TYPE R/W Message Alignment Type: This READ/WRITE bit-field permits a user to specify how the Redundant Receive STS-3 TOH Processor block will locate the boundary of the incoming Section Trace Message, as indicated below. 0 - The Section Trace Message boundary is indicated by "Line Feed". 1 - The Section Trace Message boundary is indicated by the presence of a "1" in the MSB of the first byte (within the J0 Trace Message). 1-0 MSG LENGTH R/W J0 Message Length: These READ/WRITE bit-fields permit the user to specify the length of the J0 Trace Message that the Redundant Receive STS-3 TOH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J0 Trace Message Length is presented below. MSG LENGTH 00 01 10/11 Resulting J0 Trace Message Length 1 Byte 16 Bytes 64 Bytes Table 195: Redundant Receive STS-3 Transport - Receive SD Burst Error Tolerance - Byte 1 (Address Location= 0x1752) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SD_BURST_ TOLERANCE [15:8] TYPE R/W DESCRIPTION SD_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Redundant Receive STS-3 Transport - SD BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single SubInterval period (e.g., an STS-3 frame period), when determining whether or not to declare an SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Redundant Receive STS3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. Table 196: Redundant Receive STS-3 Transport - Receive SD Burst Error Tolerance - Byte 0 (Address Location= 0x1753) 257 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 20 0 Rev2...0...0 200 BIT 0 R/W 1 SD_BURST_TOLERANCE[7:0] BIT NUMBER 7-0 NAME SD_BURST_ TOLERANCE [7:0] TYPE R/W DESCRIPTION SD_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Redundant Receive STS-3 Transport - SD BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. Table 197: Redundant Receive STS-3 Transport - Receive SF Burst Error Tolerance - Byte 1 (Address Location= 0x1756) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SF_BURST_ TOLERANCE [15:8] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Redundant Receive STS-3 Transport - SF BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SF (Signal Failure) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SF defect condition. Table 198: Redundant Receive STS-3 Transport - Receive SF Burst Error Tolerance - Byte 0 (Address Location= 0x1757) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SF_BURST_TOLERANCE[7:0] 258 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 BIT NUMBER 7-0 NAME SF_BURST_ TOLERANCE [7:0] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Redundant Receive STS-3 Transport - SF BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare an SF (Signal Failure) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SF defect condition. Table 199: Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 2 (Address Location= 0x1759) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW[23: 16] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Redundant Receive STS-3 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Redundant Receive STS-3 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 200: Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 1 (Address Location= 0x175A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[15:8] 259 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW[15:8] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL through 8: - Bits 15 These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Redundant Receive STS-3 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Redundant Receive STS-3 Transport SD Clear Threshold" register, then the SD defect will be cleared. 260 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 201: Redundant Receive STS-3 Transport - Receive SD Clear Monitor Interval - Byte 0 (Address Location= 0x175B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW[ 7:0] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SD Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Redundant Receive STS-3 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Redundant Receive STS-3 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 202: Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 2 (Address Location= 0x175D) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDO W [23:16] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Redundant Receive STS-3 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Redundant Receive STS-3 Transport SF Clear Threshold" register, then the SF defect will be cleared. 261 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 203: Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 1 (Address Location= 0x175E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Redundant Receive STS-3 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Redundant Receive STS-3 Transport SF Clear Threshold" register, then the SF defect will be cleared. Table 204: Redundant Receive STS-3 Transport - Receive SF Clear Monitor Interval - Byte 0 (Address Location= 0x175F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Redundant Receive STS-3 Transport - SF Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-3 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Redundant Receive STS-3 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Redundant Receive STS-3 Transport SF Clear Threshold" register, then the SF defect will be cleared. 262 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 205: Redundant Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1763) BIT 7 Transmit AIS-P (Downstream) Upon J0 Message Unstable R/W 0 BIT 6 Transmit AIS-P (Downstream) Upon J0 Message Mismatch R/W 0 BIT 5 Transmit AIS-P (Downstream) Upon SF BIT 4 Transmit AIS-P (Downstream) Upon SD BIT 3 Transmit AIS-P (Downstream) upon Loss of Optical Carrier AIS R/W 0 BIT 2 Transmit AIS-P (Downstream) upon LOF BIT 1 Transmit AIS-P (Downstream) upon LOS BIT 0 Transmit AIS-P (Downstream) Enable R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER NAME TYPE DESCRIPTION Transmit Path AIS upon Detection of Unstable Section Trace (J0): This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it detects an Unstable Section Trace (J0) condition in the "incoming" STS-3 data-stream. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. 1 - Configures the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 7 Transmit AIS-P (Down-stream) upon J0 Message Unstable R/W 6 Transmit AIS-P (Down-stream) Upon J0 Message Mismatch R/W Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0) Message Mismatch: This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it detects a Section Trace (J0) Message Mismatch condition in the "incoming" STS-3 data stream. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Message Mismatch" condition. 1 - Configures the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Message Mismatch" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Down-stream) upon SF R/W Transmit Path AIS upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive 263 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 SONET POH Processor blocks), anytime it declares an SF condition. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF defect. 1 - Configures the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Down-stream) upon SD R/W Transmit Path AIS upon Signal Degrade (SD): This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it declares an SD condition. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. 1 - Configures the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 Transmit AIS-P (Down-stream) upon Loss of Optical Carrier R/W Transmit Path AIS upon Loss of Optical Carrier condition: This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks), anytime it detects a "Loss of Optical Carrier" condition. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator upon detection of a "Loss of Optical Carrier" condition. 1 - Configures the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator upon detection of a "Loss of Optical Carrier" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 264 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 2 Transmit AIS-P (Down-stream) upon LOF R/W Transmit Path AIS upon Loss of Frame (LOF): This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor block), anytime it declares an LOF condition. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. 1 - Configures the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Down-stream) upon LOS R/W Transmit Path AIS upon Loss of Signal (LOS): This READ/WRITE bit-field permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor block), anytime it declares an LOS condition. 0 - Does not configure the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. 1 - Configures the Redundant Receive STS-3 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 Transmit AIS-P (Down-stream) Enable R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Redundant Receive Processor block to automatically transmit the Path indicator, via the down-stream traffic (e.g., towards SONET POH Processor blocks), upon detection of Section Trace Mismatch, Section Trace Unstable, LOF, of Optical Carrier conditions. STS-3 TOH AIS (AIS-P) the Receive an SF, SD, LOS or Loss It also permits the user to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive SONET POH Processor blocks) anytime it detects an AIS-L condition in the "incoming " STS-3 data-stream. 0 - Configures the Redundant Receive STS-3 TOH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of the AIS-L or any of the "above-mentioned" conditions. 1 - Configures the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this 265 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 register) to "1" in order to configure the Redundant Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. Table 206: Redundant Receive STS-3 Transport - Serial Port Control Register (Address Location= 0x1767) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 RxTOH_CLOCK_SPEED[7:0] BIT NUMBER 7-4 3-0 NAME Unused RxTOH_CLOCK_SPEED[7:0] TYPE R/O R/W DESCRIPTION RxTOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the "RxTOHClk output clock signal. The formula that relates the contents of these register bits to the "RxTOHClk" frequency is presented below. FREQ = 19.44 /[2 * (RxTOH_CLOCK_SPEED + 1) Note: For STS-3/STM-1 applications, the frequency of the RxTOHClk output signal must be in the range of 0.6075MHz to 9.72MHz 266 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 207: Redundant Receive STS-3 Transport - Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0x176B) BIT 7 Unused BIT 6 Unused BIT 5 Transmit AIS-P (via Downstream STS-1s) upon LOS R/W 0 BIT 4 Transmit AIS-P (via Downstream STS-1s) upon LOF R/W 0 BIT 3 Transmit AIS-P (via Downstream STS-1s) upon SD R/W 0 BIT 2 Transmit AIS-P (via Downstream STS-1s) upon SF R/W 0 BIT 1 AIS-L Output Enable BIT 0 Transmit AIS-P (via Downstream STS-1s) Enable R/W 0 R/O 0 R/O 0 R/W 0 BIT NUMBER 7-6 5 NAME Unused Transmit AIS-P (via Downstream STS-1s) upon LOS TYPE R/O R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of Signal): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the LOS defect. 0 - Does not configure all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the LOS defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the LOS defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 1 (Transmit AIS-P Down-stream - Upon LOS), within the Redundant Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1763). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Redundant Receive STS-3 TOH Processor block declares the LOS defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. 2. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOS), several SONET frame periods are required (after the Redundant Receive STS-3 TOH Processor block has declared the LOS defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3.In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 4 Transmit AIS-P (via Downstream STS-1s) upon LOF R/W Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of Frame): 267 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the LOF defect. 0 - Does not configures all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the LOF defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the LOF defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 2 (Transmit AIS-P Down-stream - Upon LOF), within the Redundant Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1763). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Redundant Receive STS-3 TOH Processor block declares the LOF defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOF defect. 2. In the case of Bit 2 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Redundant Receive STS-3 TOH Processor block has declared the LOS defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 3 Transmit AIS-P (via Downstream STS-1s) upon SD R/W Transmit AIS-P (via Downstream STS-1s) upon SD (Signal Degrade): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the SD defect. 0 - Does not configures all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the SD defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the SD defect. Note: 1.In the "long-run" the function of this bit-field is exactly the same as that of Bit 4 (Transmit AIS-P Down-stream - Upon SD), within the Redundant Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1763). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Redundant Receive STS-3 TOH Processor block declares the SD defect. This will permit the user to easily comply with the Telcordia GR-253CORE requirements of an NE transmitting the AIS-P indicator 268 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS downstream within 125us of the NE declaring the LOS defect. 2. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Redundant Receive STS-3 TOH Processor block has declared the SD defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 2 Transmit AIS-P (via Downstream STS-1s) upon SF R/W Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor blocks (in each channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares an SF condition. 0 - Does not configures all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the SF defect. 1 - Configures all "activated" Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor block declares the SF defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 5 (Transmit AIS-P Down-stream - Upon SF), within the Redundant Receive STS-3 Transport - Auto AIS Control Register (Address Location= 0x1763). The only difference is that this register bit will cause each of the "downstream" Transmit STS-1 POH Processor blocks to IMMEDIATELY begin transmit the AIS-P condition whenever the Redundant Receive STS-3 TOH Processor block declares the SF defect. This will permit the user to easily comply with the Telcordia GR-253CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the SF defect. 2. In the case of Bit 5 (Transmit AIS-P Downstream - Upon SF), several SONET frame periods are required (after the Redundant Receive STS-3 TOH Processor block has declared the SF defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 1 AIS-L Output Enable R/W AIS-L Output Enable: This READ/WRITE bit-field, along with Bits 7 (8kHz or STUFF Out Enable) within the "Operation Output Control Register - Byte 1" (Address Location= 0x0150) permit the user to configure the "AIS-L" indicator to be output via the "LOF" output pin (pin AD11). If Bit 7 (within the "Operation Output Control Register - Byte 1") is set to "0", then setting this bit-field to "1" configures pin AD11 to function as the AIS-L output indicator. If Bit 7 (within the "Operation Output Control Register - Byte 1") is set to "0", then setting this bit-field to "0" configures pin AD11 to function as the LOF output indicator. If Bit 7 (within the "Operation Output Control Register - Byte 1) is set to 269 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS "1", then this register bit is ignored. 0 Transmit AIS-P (via Downstream STS-1s) Enable R/W Automatic Transmission of AIS-P (via the downstream STS-1s) Enable: This READ/WRITE bit-field permits the user to configure all "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AISP indicator, via its "outbound" STS-1 signals, upon detection of an SF, SD, LOS and LOF condition. 0 - Does not configure the "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P indicator, whenever the Redundant Receive STS-3 TOH Processor block declares either the LOS, LOF, SD or SF defects. 1 - Configures the "activated" Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P indicator, whenever the Redundant Receive STS-3 TOH Processor block declares either the LOS, LOF, SD or SF defects. 20 0 Rev2...0...0 200 1.8 TRANSMIT ATM CELL PROCESSOR BLOCK 270 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS The register map for the Transmit ATM Cell Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Transmit ATM Cell Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33 device, with the "Transmit ATM Cell Processor Blocks "highlighted" is presented below in Figure 9. Figure 9: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Transmit ATM Cell Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 271 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.8.1 TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 208: Transmit ATM Cell Processor Block Register Address Map TRANSMIT ATM CELL PROCESSOR/ PPP PROCESSOR BLOCK REGISTERS Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Transmit ATM Cell Processor Control Register - Byte 3 Transmit ATM Cell Processor Control Register - Byte 2 Transmit ATM Cell Processor Control Register - Byte 1 Transmit ATM Cell/PPP Processor Control Register - Byte 0 Transmit ATM Status Register Reserved Transmit ATM Cell/PPP Processor Interrupt Status Register Reserved Transmit ATM Cell/PPP Processor Interrupt Enable Register Reserved Transmit ATM Cell Insertion/Extraction Memory Control Register Transmit ATM Cell Insertion/Extraction Memory - Byte 3 Transmit ATM Cell Insertion/Extraction Memory - Byte 2 Transmit ATM Cell Insertion/Extraction Memory - Byte 1 Transmit ATM Cell Insertion/Extraction Memory - Byte 0 Transmit ATM Cell - Idle Cell Header Byte # 1 Register Transmit ATM Cell - Idle Cell Header Byte # 2 Register Transmit ATM Cell - Idle Cell Header Byte # 3 Register Transmit ATM Cell - Idle Cell Header Byte # 4 Register Reserved Transmit ATM Cell - Idle Cell Payload Byte Register Transmit ATM Cell - Test Cell Header Byte # 1 Register Transmit ATM Cell - Test Cell Header Byte # 2 Register Transmit ATM Cell - Test Cell Header Byte # 3 Register Transmit ATM Cell - Test Cell Header Byte # 4 Register Reserved Transmit ATM Cell - Cell Count Register - Byte 3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF00 0xNF01 0xNF02 0xNF03 0xNF04 0xNF05 - 0xNF0A 0xNF0B 0xNF0C - 0xNF0E 0xNF0F 0xNF10 - 0xNF12 0xNF13 0xNF14 0xNF15 0xNF16 0xNF17 0xNF18 0xNF19 0xNF1A 0xNF1B 0xNF1C - 0xNF1E 0xNF1F 0xNF20 0xNF21 0xNF22 0xNF23 0xNF24 - 0xNF27 0xNF28 272 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Transmit ATM Cell - Discard Cell Count Register - Byte 3 Transmit ATM Cell - Discard Cell Count Register - Byte 2 Transmit ATM Cell - Discard Cell Count Register - Byte 1 Transmit ATM Cell - Discard Cell Count Register - Byte 0 Transmit ATM Cell - HEC Byte Error Count Register - Byte 3 Transmit ATM Cell - HEC Byte Error Count Register - Byte 2 Transmit ATM Cell - HEC Byte Error Count Register - Byte 1 Transmit ATM Cell - HEC Byte Error Count Register - Byte 0 Transmit ATM Cell - Parity Error Count Register - Byte 3 Transmit ATM Cell - Parity Error Count Register - Byte 2 Transmit ATM Cell - Parity Error Count Register - Byte 1 Transmit ATM Cell - Parity Error Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 0 Control Register Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 1 Control Register Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF29 0xNF2A 0xNF2B 0xNF2C 0xNF2D 0xNF2E 0xNF2F 0xNF30 0xNF31 0xNF32 0xNF33 0xNF34 0xNF35 0xNF36 0xNF37 0xNF38 - 0xNF42 0xNF43 0xNF44 0xNF45 0xNF46 0xNF47 0xNF48 0xNF49 0xNF4A 0xNF4B 0xNF4C 0xNF4D 0xNF4E 0xNF4F 0xNF50 - 0xNF52 0xNF53 0xNF54 273 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xNF55 0xNF56 0xNF57 0xNF58 0xNF59 0xNF5A 0xNF5B 0xNF5C 0xNF5D 0xNF5E 0xNF5F 0xNF60 - 0xNF62 0xNF63 0xNF64 0xNF65 0xNF66 0xNF67 0xNF68 0xNF69 0xNF6A 0xNF6B 0xNF6C 0xNF6D 0xNF6E 0xNF6F 0xNF70 - 0xNF72 0xNF73 0xNF74 0xNF75 0xNF76 0xNF77 0xNF78 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 2 Control Register Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 3 Control Register Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 1 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 274 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF79 0xNF7A 0xNF7B 0xNF7C 0xNF7D 0xNF7E 0xNF7F 0xNF80 - 0xN102 275 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.8.2 TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 209: Transmit ATM Cell Processor Block - Transmit ATM Control Register - Byte 3 (Address = 0xNF00) BIT 7 Unused BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 210: Transmit ATM Cell Processor Block - Transmit ATM Control Register - Byte 2 (Address = 0xNF01) BIT 7 BIT 6 BIT 5 BIT 4 Unused R/O 0 BIT NUMBER 7-1 0 R/O 0 NAME Unused Transmit ATM Cell Processor Enable R/O 0 TYPE R/O R/W Transmit ATM Cell Processor Block Enable: This READ/WRITE bit-field permits the user to either enable or disable the Transmit ATM Cell Processor block. If the user wishes to operate a given Channel in the ATM Mode, then he/she must enable the Transmit ATM Cell Processor Block. 0 - Disables the Transmit ATM Cell Processor Block 1 - Enables the Transmit ATM Cell Processor Block Note: The user must set this bit-field to "1" before he/she begins to write ATM cell data into the Transmit UTOPIA Interface block. R/O 0 R/O 0 R/O 0 R/O 0 DESCRIPTION BIT 3 BIT 2 BIT 1 BIT 0 Transmit ATM Cell Processor Enable R/W 0 276 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 211: Transmit ATM Cell Processor Block - Transmit ATM Control Register - Byte 1 (Address = 0xNF02) BIT 7 Test Cell Transmit Mode Enable R/W 0 BIT NUMBER 7 BIT 6 ONE SHOT MODE BIT 5 GFC Insertion Enable - Bit 3 R/W 0 NAME Test Cell Transmit Mode Enable TYPE R/W BIT 4 GFC Insertion Enable - Bit 2 R/W 0 BIT 3 GFC Insertion Enable - Bit 1 R/W 0 BIT 2 GFC Insertion Enable - Bit 0 R/W 0 DESCRIPTION Test Cell Transmit Mode Enable: This READ/WRITE bit-field permits the user to enable the Test Cell Transmitter (within the Transmit ATM Cell Processor Block). The user must implement this configuration option in order to perform diagnostic operations with Test Cells. 0 - Disables the Test Cell Transmitter. 1 - Enables the Test Cell Transmitter. Notes: 6 One Shot Mode R/W For normal operation, the user should set this bit-field to "1". BIT 1 COSET Polynomial Addition R/W 0 BIT 0 Regenerate HEC Byte Enable R/W 0 R/W 0 One Shot Mode: If the user has enabled the Test Cell Transmitter, then this READ/WRITE bit-field permits the user to either configure the Test Cell Transmitter into the "One-Shot" or in the "Continuous" Mode. If the user configures the Test Cell Transmitter into the "One-Shot" Mode, then (whenever the user implements a "0 to 1" transition within Bit 7 [Test Cell Transmit Mode Enable] of this register) then the Test Cell Transmitter will generate and transmit 1024 test cells. Afterwards, the Test Cell Transmitter will halt its transmission of Test Cells until the user implements another "0 to 1 transition" within Bit 7 (Test Cell Transmit Mode Enable) within this register. If the user configures the Test Cell Transmitter into the "Continuous" Mode, then the Test Cell Transmitter will continuously generate and transmit test cells for the duration that Bit 7(Test Cell Transmit Mode Enable) is set to "1". 0 - Configures the Test Cell Transmitter to operate in the "Continuous" Mode. 1 - Configures the "Test Cell Transmitter" to operate in the "One-Shot" Mode. 5 4 3 2 1 GFC Insertion Enable - Bit 3 GFC Insertion Enable - Bit 2 GFC Insertion Enable - Bit 1 GFC Insertion Enable - Bit 0 COSET Polynomial Addition R/W R/W R/W R/W R/W COSET Polynomial Addition: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to modulo-add the COSET Polynomial (e.g., x^6 + x^4 + x^2 + 1) to the HEC byte value, within each "outbound" 277 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ATM cell. 0 - Configures the Transmit ATM Cell Processor block to NOT modulo-add the COSET Polynomial to the HEC byte within each outbound ATM cell. 1 - Configures the Transmit ATM Cell Processor block to modulo-add the COSET Polynomial to the HEC byte within each outbound ATM cell. 0 Regenerate HEC Byte Enable R/W Regenerate HEC Byte Enable: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to automatically re-compute and insert a new HEC byte into each ATM cell (that it receives from the Transmit UTOPIA Interface block) that contains an uncorrectable HEC byte. 0 - Does not configure the Transmit ATM Cell Processor block to compute and insert a new HEC byte into ATM cells that contains an "uncorrectable" HEC Byte error. 1 - Configures the Transmit ATM Cell Processor block to compute and insert a new HEC byte into ATM cells that contains an "uncorrectable" HEC Byte error. 20 0 Rev2...0...0 200 278 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 212: Transmit ATM Cell Processor Block - Transmit ATM Control - Byte 0 (Address = 0xNF03) BIT 7 HEC Byte Invert BIT 6 HEC Byte Check Enable BIT 5 Transmit UTOPIA Parity Check Enable R/W 0 NAME HEC Byte Invert HEC Byte Check Enable TYPE R/W R/W HEC Byte Invert: HEC Byte Check Enable: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to perform HEC byte checking of all ATM cells that it receives via the Transmit UTOPIA Interface block. 0 - Configures the Transmit ATM Cell Processor block to NOT perform HEC byte checking on all ATM cells that it receives via the Transmit UTOPIA Interface block. 1 - Configures the Transmit ATM Cell Processor block to perform HEC byte checking on all ATM cells that it receives via the Transmit UTOPIA Interface block. 5 Transmit UTOPIA Parity Check Enable R/W Transmit UTOPIA Parity Check Enable: This READ/WRITE bit-field permits the user to either enable or disable "Transmit UTOPIA Interface" Parity checking. If the user enables "Transmit UTOPIA Interface" Parity Checking, then the Transmit ATM Cell Processor block will compute either the EVEN or ODD parity value (depending upon the setting of Bit 3 within this register) of each byte or 16-bit word that is input via the Transmit UTOPIA Data Bus input pins: (TxUData[15:0]). Afterwards, the Transmit ATM Cell Processor block will compare this "locally computed" parity value with that which the ATM Layer Processor has provided to the "TxUPrty" input pin. If the Transmit ATM Cell Processor detects any discrepancies between these two parity values (e.g., any parity errors) then it will take action based upon the user's settings for Bit 4 (Transmit UTOPIA Parity Error - Discard). 0 - Disables "Transmit UTOPIA Interface" Parity Checking. 1 - Enables "Transmit UTOPIA Interface" Parity Checking. 4 Transmit UTOPIA Parity Error - Discard R/W Transmit UTOPIA Parity Error - Discard Cell: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to either discard or retain (for further processing) any ATM cell that contains a "Transmit UTOPIA Interface" parity error. 0 - Configures the Transmit ATM Cell Processor block to retain (for further processing) all cells that contain "Transmit UTOPIA Interface" parity errors. 1 - Configures the Transmit ATM Cell Processor block to discard all cells that contain "Transmit UTOPIA Interface" parity errors. BIT 4 Transmit UTOPIA Parity Error - Discard R/W 0 BIT 3 Transmit UTOPIA - ODD Parity BIT 2 Reserved BIT 1 BIT 0 Scrambler Enable R/W 0 BIT NUMBER 7 6 R/W 0 R/W 0 R/O 0 DESCRIPTION R/O 0 R/W 0 279 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Notes: 3 Transmit UTOPIA - Odd Parity R/W 20 0 Rev2...0...0 200 This bit-field is only valid if "Transmit UTOPIA Interface" Parity Checking has been enabled. Transmit UTOPIA Parity Value - ODD Parity: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to compute either the EVEN or ODD parity value for each byte or 16-bit word within each cell that it processes. Each of these parity values will ultimately be compared with the value that is input via the "TxUPrty" input pin (on the Transmit UTOPIA Interface block) coincident to when ATM cell data is being applied to the "TxUData[15:0]" input pins. 0 - Configures the Transmit ATM Cell Processor block to compute and verify the EVEN Parity value of each byte (or 16-bit word) of ATM cell data that it processes. 1 - Configures the Transmit ATM Cell Processor block to compute and verify the ODD Parity value of each byte (or 16-bit word) of ATM cell data that it processes. Notes: This bit-field is only value if "Transmit UTOPIA Interface" Parity Checking has been enabled. 2-1 0 Reserved Scrambler Enable R/O Cell Payload Scrambler Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Cell Payload Scrambler". If the user enables the "Cell Payload Scrambler" then the Transmit ATM Cell Processor will payload self-synchronous scrambling on all cell payloads bytes (within each outbound ATM cell) with the x^43+1 polynomial. 0 - Disables the Cell Payload Scrambler 1 - Enables the Cell Payload Scrambler 280 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 213: Transmit ATM Cell Processor Block - Transmit ATM Status Register (Address = 0xNF04) BIT 7 R/O 0 BIT NUMBER 7-1 0 BIT 6 R/O 0 NAME Unused One Shot DONE BIT 5 R/O 0 TYPE R/O R/O One Shot DONE: This READ-ONLY bit-field indicates whether or not the Test Cell Transmitter has completed its transmission of 1024 test cells, following the instant that the user has commanded the Test Cell to transmit this burst of 1024 cells. 0 - Indicates that the Test Cell Transmitter has NOT completed its transmission of 1024 test cells. 1 - Indicates that the Test Cell Transmitter has completed its transmission of 1024 test cells since the last "Transmit Test Cell - One Shot" command. Notes: 1. This bit-field is only valid if (1) the Test Cell Transmitter is active and (2) if the Test Cell Transmitter has been configured to operate in the "One-Shot" Mode. 2. Once this bit-field has been set to "1", it will remain at "1" until the user executes another "Transmit Test Cell - One Shot" command. BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 DESCRIPTION BIT 3 BIT 2 BIT 1 BIT 0 One Shot DONE R/O 0 281 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 214: Transmit ATM Cell Processor Block - Transmit ATM Interrupt Status Register (Address = 0xNF0B) BIT 7 Unused BIT 6 BIT 5 Transmit Cell Extraction Interrupt Status BIT 4 Transmit Cell Insertion Interrupt Status BIT 3 Transmit Cell Extraction Memory Overflow Interrupt Status RUR 0 BIT 2 Transmit Cell Insertion Memory Overflow Interrupt Status RUR 0 DESCRIPTION BIT 1 Detection of HEC Byte Error Interrupt Status BIT 0 Detection of Transmit UTOPIA Parity Error Interrupt Status RUR 0 R/O 0 BIT NUMBER 7-6 5 R/O 0 NAME Unused RUR 0 TYPE R/O RUR RUR 0 RUR 0 Transmit Cell Extraction Interrupt Status Transmit Cell Extraction Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit Cell Extraction" interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate the "Transmit Cell Extraction" Interrupt anytime it receives an incoming ATM cell (from the TxFIFO) and loads an ATM cell into the "Extraction Memory" Buffer. 0 - Indicates that the "Transmit Cell Extraction" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Transmit Cell Extraction" Interrupt has occurred since the last read of this register. 4 Transmit Cell Insertion Interrupt Status RUR Transmit Cell Insertion Interrupt This RESET-upon-READ bit-field indicates whether or not the "Transmit Cell Insertion" interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate the "Transmit Cell Insertion" Interrupt anytime a cell (residing in the Transmit Cell Insertion Buffer) is read out of the "Transmit Cell Insertion Buffer" and is loaded into the outbound ATM cell traffic. 0 - Indicates that the "Transmit Cell Insertion" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Transmit Cell Insertion" Interrupt has occurred since the last read of this register. 3 Transmit Cell Extraction Memory Overflow Interrupt Status RUR Transmit Cell Extraction Memory Overflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit Cell Extraction Memory Overflow" Interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime an overflow event has occurred in the "Transmit Cell Extraction Memory" Buffer. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Transmit Cell Extraction Memory Overflow" Interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Transmit Cell Extraction Memory Overflow" interrupt since the last 282 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS read of this register. 2 Transmit Cell Insertion Memory Overflow Interrupt Status RUR Transmit Cell Insertion Memory Overflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the Transmit Cell Insertion Memory Overflow" Interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime an overflow event has occurred in the "Transmit Cell Insertion Memory" Buffer. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Transmit Cell Insertion Memory Overflow" interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Transmit Cell Insertion Memory Overflow" interrupt since the last read of this register. 1 Detection of HEC Byte Error Interrupt RUR Detection of HEC Byte Error Interrupt: This RESET-upon-READ bit-field indicates whether or not the "Transmit ATM Cell Processor block" has declared the "Detection of HEC Byte Error" Interrupt since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime it has received an ATM cell (from the TxFIFO) that contains a HEC byte error. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Detection of HEC Byte Error" Interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Detection of HEC Byte Error" Interrupt since the last read of this register. 0 Detection of Transmit UTOPIA Parity Error Interrupt Detection of Transmit UTOPIA Parity Error Interrupt: This RESET-upon-READ bit-field indicates whether or not the "Transmit ATM Cell Processor" block has declared the "Detection of Transmit UTOPIA Parity Error" Interrupt since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime it has received an ATM cell byte or 16-bit word (from the Transmit UTOPIA Interface block) that contains a parity error. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Detection of Transmit UTOPIA Parity Error" Interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Detection of Transmit UTOPIA Parity Error" Interrupt since the last read of this register. 283 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 215: Transmit ATM Cell Processor Block - Transmit ATM Interrupt Enable Register (Address = 0xNF0F) BIT 7 Unused BIT 6 BIT 5 Transmit Cell Extraction Interrupt Enable BIT 4 Transmit Cell Insertion Interrupt Enable BIT 3 Transmit Cell Extraction Memory Overflow Interrupt Enable R/W 0 BIT 2 Transmit Cell Insertion Memory Overflow Interrupt Enable R/W 0 DESCRIPTION BIT 1 Detection of HEC Byte Error Interrupt Enable BIT 0 Detection of Transmit UTOPIA Parity Error Interrupt Enable R/W 0 R/O 0 BIT NUMBER 7-6 5 R/O 0 NAME Unused Transmit Cell Extraction Interrupt Enable R/W 0 TYPE R/W 0 R/W 0 R/W Transmit Cell Extraction Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Extraction" Interrupt. If the user enables this feature, then the Transmit ATM Cell Processor block will generate the "Transmit Cell Extraction" Interrupt anytime it receives an incoming ATM cell (from the TxFIFO) and loads this ATM cell into the "Transmit Extraction Memory" Buffer. 0 - Disables the "Transmit Cell Extraction" Interrupt. 1 - Enables the "Transmit Cell Extraction" Interrupt 4 Transmit Cell Insertion Interrupt Enable R/W Transmit Cell Insertion Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Insertion" Interrupt. If the user enables this feature, then the Transmit ATM Cell Processor block will generate the "Transmit Cell Insertion" Interrupt anytime a cell (residing in the "Transmit Cell Insertion" Buffer) is read out of the "Transmit Cell Insertion" Buffer and is loaded into the "outbound" ATM cell traffic. 0 - Disables the Transmit Cell Insertion Interrupt. 1 - Enables the Transmit Cell Insertion Interrupt. 3 Transmit Cell Extraction Memory Overflow Interrupt Enable R/W Transmit Cell Extraction Memory Overflow Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Extraction Memory Overflow" Interrupt. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt any time an overflow event has occurred in the "Transmit Cell Extraction Memory" buffer. 0 - Disables the Transmit Cell Extraction Memory Overflow Interrupt. 1 - Enables the Transmit Cell Extraction Memory Overflow Interrupt. 2 Transmit Cell Insertion Memory Overflow Interrupt Enable R/W Transmit Cell Insertion Memory Overflow Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Insertion Memory Overflow" Interrupt. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt any time an overflow event has occurred in the "Transmit Cell Insertion Memory" buffer. 284 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Disables the Transmit Cell Insertion Memory Overflow Interrupt. 1 - Enables the Transmit Cell Insertion Memory Overflow Interrupt. 1 Detection of HEC Byte Error Interrupt Enable R/W Detection of HEC Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of HEC Byte Error Interrupt" within the Transmit ATM Cell Processor Block. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt each time it receives an ATM cell (from the TxFIFO) that contains a HEC Byte error. 0 - Disables the "Detection of HEC Byte Error" Interrupt. 1 - Enables the "Detection of HEC Byte Error" Interrupt 0 Detection of Transmit UTOPIA Parity Error Interrupt Enable Detection of Transmit UTOPIA Parity Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Transmit UTOPIA Parity Error" Interrupt within the Transmit ATM Cell Processor block. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt each time it receives an ATM cell byte or 16-bit word (from the TxFIFO) that contains a parity error. 0 - Disables the "Detection of Transmit UTOPIA Parity Error" Interrupt. 1 - Enables the "Detection of Transmit UTOPIA Parity Error" Interrupt. 285 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 216: Transmit ATM Cell Processor Block - Transmit ATM Cell Insertion/Extraction Memory Control Register (0xNF13) BIT 7 BIT 6 Unused BIT 5 BIT 4 Transmit Cell Extraction Memory RESET* R/O 0 NAME Unused Transmit Cell Extraction Memory RESET* R/W Transmit Cell Extraction Memory RESET*: This READ/WRITE bit-field permits the user to perform a REST operation to the Transmit Cell Extraction Memory. If the user writes a "1-to-0 transition" into this bit-field, then the following events will occur. * * BIT 3 Transmit Cell Extraction Memory CLAV R/O 0 BIT 2 Transmit Cell Insertion Memory RESET* R/W 1 DESCRIPTION BIT 1 Transmit Cell Insertion Memory ROOM R/O 0 BIT 0 Transmit Cell Insertion Memory WSOC W/O 0 R/O 0 BIT NUMBER 7-5 4 R/O 0 R/W 1 TYPE All of the contents of the Transmit Cell Extraction Memory will be flushed. All READ and WRITE pointers will be reset to their default positions. Following this RESET event, the user must write the value "1" into this bit-field in order to enable normal operation within the Transmit Cell Extraction Memory. Notes: 3 Transmit Cell Extraction Memory CLAV R/O Transmit Cell Extraction Memory - Cell Available Indicator: This READ-ONLY bit-field indicates whether or not there is at least ATM cell of data (residing within the Transmit Cell Extraction Memory) that needs to be read out via the Microprocessor Interface. 0 - Indicates that the Transmit Cell Extraction Memory is empty and contains no ATM cell data. 1 - Indicates that the Transmit Cell Extraction Memory contains at least one ATM cell of data that needs to be read out. Notes: The user should validate each ATM cell that is being read out from the Transmit Cell Extraction memory by checking the state of this bit-field prior to reading out the contents of ATM cell data residing within the Transmit Cell Extraction Memory 2 Transmit Cell Insertion Memory RESET* R/W Transmit Cell Insertion Memory RESET*: This READ/WRITE bit-field permits the user to perform a RESET operation to the Transmit Cell Insertion Memory. If the user writes a "1-to-0 transition" into this bit-field, then the following events will occur. * * All of the contents of the Transmit Cell Insertion Memory will be flushed. All READ and WRITE pointers will be reset to their default positions. Following this RESET event, the user must write the value "1" into this bit-field in order to enable normal Notes: 286 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS operation of the Transmit Cell Insertion Memory. 1 Transmit Cell Insertion Memory ROOM R/O Transmit Cell Insertion Memory - ROOM Indicator: This READ-ONLY bit-field indicates whether or not there is room (e.g., empty space) available for the contents of another ATM cell to be written into the Transmit Cell Insertion Memory. 0 - Indicates that the Transmit Cell Insertion Memory does not contain enough empty space to receive another ATM cell via the Microprocessor Interface. 1 - Indicates that the Transmit Cell Insertion Memory does contain enough empty space to receive another ATM cell via the Microprocessor Interface. Notes: The user should verify that the Transmit Cell Insertion Memory has sufficient empty space to accept another ATM cell of data (via the Microprocessor Interface) by polling the state of this bit-field prior to writing each cell into the Transmit Cell Insertion Memory. 0 Transmit Cell Insertion Memory WSOC W/O Transmit Cell Insertion Memory - Write SOC (Start of Cell): Whenever the user is writing the contents of an ATM cell into the Transmit Cell Insertion Memory, then he/she is suppose to identify/designate the very first byte of this ATM cell by setting this bit-field to "1". Whenever the user does this, then the Transmit Cell Insertion Memory will "know" that the next octet that is written into the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data Register - Byte 3 (Address = 0xNF14) is designated as the first byte of the ATM cell currently being written into the Transmit Cell Insertion Memory. This bit-field must be set to "0" during all other WRITE operations to the Transmit ATM Cell Processor - Transmit Cell Insertion/Extraction Memory Data Register 287 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 217: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 3 (Address = 0xNF14) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[31:24] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[31:24]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 2 through 0" support the following functions. * BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[31:24] They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. * Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from this particular address location. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 2 register. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 1 register. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 0 register. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. 288 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 218: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 2 (Address = 0xNF15) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[23:16] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[23:16]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 3, 1 and 0" support the following functions. They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4-byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 3" register. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to this particular address location. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 1 register. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 0 register. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[23:16] 289 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 219: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 1 (Address = 0xNF16) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[15:8] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[15:8]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 3, 2 and 0" support the following functions. * BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[15:8] They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. * Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4-byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 3 register. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 2 register. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to this particular register location. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 0 register. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. 290 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 220: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 0 (Address = 0xNF17) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[7:0]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 3, through 1" support the following functions. * BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[7:0] They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. * Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 3 register. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 2 register. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 1" register. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to this particular register location. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. 291 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 221: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 1 (Address = 0xNF18) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 1 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 1[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 2 through Byte 4" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 1 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 1 [7:0] Table 222: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 2 (Address = 0xNF19) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 2 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 2[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Bytes 1, 3 and 4" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 2 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 2 [7:0] 292 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 223: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 3 (Address = 0xNF1A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 3 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 3[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Bytes 1, 2 and 4" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 3 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 3 [7:0] Table 224: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 4 (Address = 0xNF1B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 4 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 4[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 1 through Byte 3" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 4 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 4 [7:0] 293 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 225: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Payload Register (Address = 0xNF1F) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Payload Byte[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Payload Byte [7:0]: These READ/WRITE register bits permit the user to define the value of the payload bytes of all Idle Cells that are generated and transmitted by the Transmit ATM Cell Processor block. Notes: Each of the 48 payload bytes (within each outbound Idle Cell) will be assigned the value that is written into this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Payload Byte[7:0] Table 226: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 1 (Address = 0xNF20) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 1[7:0] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 1: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 2 through 4" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 1. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 1 [7:0] 294 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 227: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 2 (Address = 0xNF21) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 2[7:0] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 2: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 1, 3 and 4" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 2. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 2 [7:0] Table 228: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 3 (Address = 0xNF22) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 3[7:0] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 3: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 1, 2 and 4" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 3. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 3 [7:0] 295 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 229: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 4 (Address = 0xNF23) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 4[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 4: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 1 through 3" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 4. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 4 [7:0] Table 230: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF28) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 3[31:24]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 2 through 0" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[31:24] 296 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 231: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF29) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 2[23:16]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 3, 1 and 0" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[23:16] Table 232: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF2A) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 1[15:8]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 3, 2 and 0" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[15:8] 297 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 233: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF2B) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 3 through 1" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[7:0] 298 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 234: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 3 (Address = 0xNF2C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 3[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 2 through 0" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. This particular register contains the MSB (Most Significant Byte) value of this 32-bit expression. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[31:24] Table 235: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 2 (Address = 0xNF2D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 2[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 3, 1 and 0" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[23:16] 299 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 236: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 1 (Address = 0xNF2E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 1[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 3, 2 and 0" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[15:8] Table 237: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 0 (Address = 0xNF2F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 3 through 1" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. This particular register contains the LSB (Least Significant Byte) value of this 32-bit expression. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[7:0] 300 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 238: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 3 (Address = 0xNF30) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 3[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 2 through 0" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the MSB (Most Significant Byte) for this 32-bit expression. Notes: 1. This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[31:24] Table 239: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 2 (Address = 0xNF31) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 2[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 3, 1 and 0" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). Notes: 1.This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[23:16] 301 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 240: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 1 (Address = 0xNF32) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 1[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 3, 2 and 0" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). Notes: 1. This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[15:8] Table 241: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 0 (Address = 0xNF33) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 3 through 1" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the LSB (Least Significant Byte) for this 32-bit expression. Notes: 1. This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[7:0] 302 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 242: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 3 (Address = 0xNF34) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 3[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 2 through 0" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the MSB (Most Significant Byte) for this 32-bit expression. Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[31:24] Table 243: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 2 (Address = 0xNF35) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 2[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 3, 1 and 0" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[23:16] 303 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 244: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 1 (Address = 0xNF36) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 1[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 3, 2 and 0" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[15:8] Table 245: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 0 (Address = 0xNF37) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 3 through 1" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the LSB (Least Significant Byte) for this 32-bit expression. Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[7:0] 304 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 246: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 0 (Address = 0xNF43) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 0 Enable R/O 0 NAME Unused Transmit User Cell Filter # 0 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 0 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 0. If the user enables Transmit User Cell Filter # 0, then Transmit User Cell Filter # 0 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 0, then Transmit User Cell Filter # 0 then all cells that are applied to the input of Transmit User Cell Filter # 0 will pass through to the output of Transmit User Cell Filter # 0. 0 - Disables Transmit User Cell Filter # 0. 1 - Enables Transmit User Cell Filter # 0. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 0: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 0 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 0, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 0 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 0 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 0 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 0 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 0" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 0: This READ/WRITE bit-field permits the user to either 305 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 0 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 0, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 0 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 0 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 0 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 0" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 0: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 0 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 0 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 0 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 0" has been enabled. 306 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 247: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1 (Address = 0xNF44) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 1 [7:0] 307 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 248: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2 (Address = 0xNF45) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 2 [7:0] 308 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 249: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3 (Address = 0xNF46) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 3 [7:0] 309 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 250: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4 (Address = 0xNF47) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 4 [7:0] 310 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 251: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 1 (Address = 0xNF48) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 1 [7:0] 311 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 252: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 2 (Address = 0xNF49) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 2 [7:0] 312 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 253: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 3 (Address = 0xNF4A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 3 [7:0] 313 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 254: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 4 (Address = 0xNF4B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 4 [7:0] 314 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 255: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 3 (Address = 0xNF4C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[31:24] 315 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 256: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 2 (Address = 0xNF4D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[23:16] 316 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 257: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 1 (Address = 0xNF4E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime Transmit User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[15:8] 317 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 258: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 0 (Address = 0xNF4F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime Transmit User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[7:0] 318 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 259: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 1 (Address = 0xNF53) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 1 Enable R/O 0 NAME Unused Transmit User Cell Filter # 1 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 1 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 1. If the user enables Transmit User Cell Filter # 1, then Transmit User Cell Filter # 1 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 1, then Transmit User Cell Filter # 1 then all cells that are applied to the input of Transmit User Cell Filter # 1 will pass through to the output of Transmit User Cell Filter # 1. 0 - Disables Transmit User Cell Filter # 1. 1 - Enables Transmit User Cell Filter # 1. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 1: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 1 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 1, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 1 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 1 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 1 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 1 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 1" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 1: This READ/WRITE bit-field permits the user to either 319 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 1 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 1, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 1 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 1 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 1 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 1" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 1: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 1 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 1 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 1 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 1" has been enabled. 320 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 260: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1 (Address = 0xNF54) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 1 [7:0] 321 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 261: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2 (Address = 0xNF55) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 2 [7:0] 322 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 262: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3 (Address = 0xNF56) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 3 [7:0] 323 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 263: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4 (Address = 0xNF57) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 4 [7:0] 324 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 264: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 1 (Address = 0xNF58) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 1 [7:0] 325 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 265: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 2 (Address = 0xNF59) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 2 [7:0] 326 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 266: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 3 (Address = 0xNF5A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 3 [7:0] 327 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 267: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 4 (Address = 0xNF5B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 4 [7:0] 328 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 268: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 3 (Address = 0xNF5C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[31:24] 329 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 269: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 2 (Address = 0xNF5D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[23:16] 330 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 270: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 1 (Address = 0xNF5E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime Transmit User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[15:8] 331 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 271: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 0 (Address = 0xNF5F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime Transmit User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[7:0] 332 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 272: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 2 (Address = 0xNF63) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 2 Enable R/O 0 NAME Unused Transmit User Cell Filter # 2 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 2 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 2. If the user enables Transmit User Cell Filter # 2, then Transmit User Cell Filter # 2 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 2, then Transmit User Cell Filter # 2 then all cells that are applied to the input of Transmit User Cell Filter # 2 will pass through to the output of Transmit User Cell Filter # 2. 0 - Disables Transmit User Cell Filter # 2. 1 - Enables Transmit User Cell Filter # 2. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 2: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 2 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 2, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 2 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 2 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 2 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 2 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 2" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 2: This READ/WRITE bit-field permits the user to either 333 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 2 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 2, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 2 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 2 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 2 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 2" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 2: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 2 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 2 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 2 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 2" has been enabled. 334 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 273: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1 (Address = 0xNF64) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 1 [7:0] 335 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 274: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2 (Address = 0XNF65) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 2 [7:0] 336 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 275: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3 (Address = 0xNF66) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 3 [7:0] 337 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 276: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4 (Address = 0xNF67) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 4 [7:0] 338 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 277: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 1 (Address = 0xNF68) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 1 [7:0] 339 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 278: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 2 (Address = 0xNF69) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 2 [7:0] 340 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 279: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 3 (Address = 0xNF6A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 3 [7:0] 341 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 280: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 4 (Address = 0xNF6B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 4 [7:0] 342 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 281: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 3 (Address = 0xNF6C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[31:24] 343 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 282: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 2 (Address = 0xNF6D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[23:16] 344 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 283: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 1 (Address = 0xNF6E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[15:8] 345 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 284: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 0 (Address = 0xNF6F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[7:0] 346 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 285: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 3 (Address = 0xNF63) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 3 Enable R/O 0 NAME Unused Transmit User Cell Filter # 3 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 3 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 3. If the user enables Transmit User Cell Filter # 3, then Transmit User Cell Filter # 3 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 3, then Transmit User Cell Filter # 3 then all cells that are applied to the input of Transmit User Cell Filter # 3 will pass through to the output of Transmit User Cell Filter # 3. 0 - Disables Transmit User Cell Filter # 3. 1 - Enables Transmit User Cell Filter # 3. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 3: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 3 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 3, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 3 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 3 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 3 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 3 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 3" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 3: This READ/WRITE bit-field permits the user to either 347 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 3 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 3, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 3 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 3 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 3 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 3" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 3: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 3 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 3 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 3 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 3" has been enabled. 348 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 286: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1 (Address = 0xNF64) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 1 [7:0] 349 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 287: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2 (Address = 0xNF65) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 2 [7:0] 350 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 288: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3 (Address = 0xNF66) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 3 [7:0] 351 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 289: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4 (Address = 0xNF67) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 4 [7:0] 352 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 290: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 1 (Address = 0xNF68) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 1 [7:0] 353 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 291: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 2 (Address = 0xNF69) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 2 [7:0] 354 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 292: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 3 (Address = 0xNF6A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 3 [7:0] 355 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 293: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 4 (Address = 0xNF6B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 4 [7:0] 356 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 294: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 3 (Address = 0xNF6C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[31:24] 357 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 295: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 2 (Address = 0xNF6D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[23:16] 358 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 296: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 1 (Address = 0xNF6E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[15:8] 359 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 297: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 0 (Address = 0xNF6F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[7:0] 360 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.9 RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK The register map for the Receive STS-1 TOH and POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Receive STS-1 TOH and POH Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33 device, with the "Receive STS-1 TOH and POH Processor Blocks "highlighted" is presented below in Figure 10 Figure 10: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Receive STS1 TOH and POH Processor Blocks "High-lighted". Receive STS-1 Receive STS-1 Telecom Bus Telecom Bus Interface Interface Block Block Receive Receive STS-1 TOH STS-1 TOH Processor Processor Block Block Transmit Transmit STS-1 TOH STS-1 TOH Processor Processor Block Block Transmit STS-1 Transmit STS-1 Telecom Bus Telecom Bus Interface Interface Block Block DS3/E3 DS3/E3 Framer Framer Block Block Receive Receive STS-1 POH STS-1 POH Processor Processor Block Block Transmit Transmit STS-1 POH STS-1 POH Processor Processor Block Block Channel 0 Clock Clock Synthesizer Synthesizer Block Block From Channels 1&2 Transmit Transmit STS-3 TOH STS-3 TOH Processor Processor Block Block Receive Receive STS-3 TOH STS-3 TOH Processor Processor Block Block Transmit Transmit STS-3 PECL STS-3 PECL Interface Interface Block Block Transmit STS-3 Transmit STS-3 Telecom Bus Telecom Bus Interface Interface Block Block Clock & Clock & Data Data Recovery Recovery Block Block Transmit Transmit SONET POH SONET POH Processor Processor Block Block Receive Receive SONET POH SONET POH Processor Processor Block Block Receive STS-3 Receive STS-3 Telecom Bus Telecom Bus Interface Interface Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block To Channels 1 & 2 Receive Receive STS-3 PECL STS-3 PECL Interface Interface Block Block DS3/E3 Jitter DS3/E3 Jitter Attenuator Attenuator Block Block 361 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.9.1 RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 298: Receive STS-1 TOH and POH Processor Block Control Register Address Map INDIVIDUAL REGISTER ADDRESS 0x00 - 0x02 0x03 0x04, 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D, 0x1E 0x1F ADDRESS LOCATION 0xN000 - 0xN102 0xN103 0xN104 - 0xN105 0xN106 0xN107 0xN108 0xN109 0xN10A 0xN10B 0xN10C 0xN10D 0xN10E 0xN10F 0xN110 0xN111 0xN112 0xN113 0xN114 0xN115 0xN116 0xN117 0xN118 0xN119 0xN11A 0xN11B 0xN11C 0xN11D - 0xN11E 0xN11F Reserved Receive STS-1 Transport Control Register - Byte 0 Reserved Receive STS-1 Transport Status Register - Byte 1 Receive STS-1 Transport Status Register - Byte 0 Reserved Receive STS-1 Transport Interrupt Status Register - Byte 2 Receive STS-1 Transport Interrupt Status Register - Byte 1 Receive STS-1 Transport Interrupt Status Register - Byte 0 Reserved Receive STS-1 Transport Interrupt Enable Register - Byte 2 Receive STS-1 Transport Interrupt Enable Register - Byte 1 Receive STS-1 Transport Interrupt Enable Register - Byte 0 Receive STS-1 Transport B1 Byte Error Count - Byte 3 Receive STS-1 Transport B1 Byte Error Count - Byte 2 Receive STS-1 Transport B1 Byte Error Count - Byte 1 Receive STS-1 Transport B1 Byte Error Count - Byte 0 Receive STS-1 Transport B2 Byte Error Count - Byte 3 Receive STS-1 Transport B2 Byte Error Count - Byte 2 Receive STS-1 Transport B2 Byte Error Count - Byte 1 Receive STS-1 Transport B2 Byte Error Count - Byte 0 Receive STS-1 Transport REI-L Error Count - Byte 3 Receive STS-1 Transport REI-L Error Count - Byte 2 Receive STS-1 Transport REI-L Error Count - Byte 1 Receive STS-1 Transport REI-L Error Count - Byte 0 Reserved Reserved Receive STS-1 Transport - Received K1 Byte Value Register REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 362 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0xN120 - 0xN122 0xN123 0xN124 - 0xN126 0xN127 0xN128 - 0xN12D 0xN12E 0xN12F 0xN130 0xN131 0xN132 0xN133 0xN134, 0xN135 0xN136 0xN137 0xN138 - 0xN139 0xN13A 0xN13B 0xN13C 0xN13D 0xN13E 0xN13F 0xN140 - 0xN141 0xN142 0xN143 0xN144, 0xN145 0xN146 Reserved Receive STS-1 Transport - Received K2 Byte Value Register Reserved Receive STS-1 Transport - Received S1 Byte Value Register Reserved Receive STS-1 Transport - LOS Threshold Value - MSB Receive STS-1 Transport - LOS Threshold Value - LSB Reserved Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SF Set Threshold - Byte 1 Receive STS-1 Transport - Receive SF Set Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SF Clear Threshold - Byte 1 Receive STS-1 Transport - Receive SF Clear Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SD Set Threshold - Byte 1 Receive STS-1 Transport - Receive SD Set Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SD Clear Threshold - Byte 1 REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 INDIVIDUAL REGISTER ADDRESS 0x20 - 0x22 0x23 0x24 - 0x26 0x27 0x28 - 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34, 0x35 0x36 0x37 0x38, 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40, 0x41 0x42 0x43 0x44, 0x45 0x46 363 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x47 0x48 - 0x4A 0x4B 0x4C - 0x4E 0x4F 0x50 - 0x51 0x52 0x53 0x54, 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 - 0x62 0x63 0x64 - 0x6A 0x6B ADDRESS LOCATION 0xN147 0xN14B - 0xN14A 0xN14B 0xN14C - 0xN14E 0xN14F 0xN150 - 0xN151 0xN152 0xN153 0xN154, 0xN155 0xN156 0xN157 0xN158 0xN159 0xN15A 0xN15B 0xN15C 0xN15D 0xN15E 0xN15F 0xN160 - 0xN162 0xN163 0xN164 - 0xN16A 0xN16B REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 Receive STS-1 Transport - Receive SD Clear Threshold - Byte 0 Reserved Receive STS-1 Transport - Force SEF Condition Reserved Receive STS-1 Transport - Receive J0 Byte Trace Buffer Control Register Reserved Receive STS-1 Transport - Receive SD Burst Error Count Tolerance - Byte 1 Receive STS-1 Transport - Receive SD Burst Error Count Tolerance - Byte 0 Reserved Receive STS-1 Transport - Receive SF Burst Error Count Tolerance - Byte 1 Receive STS-1 Transport - Receive SF Burst Error Count Tolerance - Byte 0 Reserved Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Auto AIS Control Register Reserved Receive STS-1 Transport - Auto AIS (in Downstream STS-1s) Control Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 364 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0xN16C - 0xN182 0xN183 0xN184 0xN185 0xN186 0xN187 0xN188 0xN189 0xN18A 0xN18B 0xN18C 0xN18D 0xN18E 0xN18F 0xN190 - 0xN192 0xN193 0xN194, 0xN195 0xN196 0xN197 0xN198 0xN199 0xN19A 0xN19B 0xN19C 0xN19D 0xN19E 0xN19F 0xN1A0 - 0xN1A5 0xN1A6 0xN1A7 Reserved Receive STS-1 Path - Control Register - Byte 2 Reserved Receive STS-1 Path - Control Register - Byte 1 Receive STS-1 Path - Status Register - Byte 0 Reserved Receive STS-1 Path - Interrupt Status Register - Byte 2 Receive STS-1 Path - Interrupt Status Register - Byte 1 Receive STS-1 Path - Interrupt Status Register - Byte 0 Reserved Receive STS-1 Path - Interrupt Enable Register - Byte 2 Receive STS-1 Path - Interrupt Enable Register - Byte 1 Receive STS-1 Path - Interrupt Enable Register - Byte 0 Reserved Receive STS-1 Path - SONET Receive RDI-P Register Reserved Receive STS-1 Path - Received Path Label Value (C2 Byte) Register Receive STS-1 Path - Expected Path Label Value (C2 Byte) Register Receive STS-1 Path - B3 Error Count Register - Byte 3 Receive STS-1 Path - B3 Error Count Register - Byte 2 Receive STS-1 Path - B3 Error Count Register - Byte 1 Receive STS-1 Path - B3 Error Count Register - Byte 0 Receive STS-1 Path - REI-P Error Count Register - Byte 3 Receive STS-1 Path - REI-P Error Count Register - Byte 2 Receive STS-1 Path - REI-P Error Count Register - Byte 1 Receive STS-1 Path - REI-P Error Count Register - Byte 0 Reserved Receive STS-1 Path - Pointer Value Register - Byte 1 Receive STS-1 Path - Pointer Value Register - Byte 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 INDIVIDUAL REGISTER ADDRESS 0x6C - 0x82 0x83 0x84, 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 - 0x92 0x93 0x94, 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 - 0xA5 0xA6 0xA7 365 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0xA8 - 0xBA 0xBB 0xBC - 0xBE 0xBF 0xC0 - 0xC2 0xC3 0xC4 - 0xD2 0xD3 0xC4-0xC6 0xD7 0xD8 - 0xDA 0xDB 0xDC - 0xDE 0xDF 0xE0 - 0xE2 0xE3 0xE4 - 0xE6 0xE7 0xE8 - 0xEA 0xEB 0xEC - 0xEE 0xEF 0xF0 - 0xF2 0xF3 0xF6 - 0xFF ADDRESS LOCATION 0xN1A8 - 0xN1BA 0xN1BB 0xN1BC - 0xN1BE 0xN1BF 0xN1C0 - 0xN1C2 0xN1C3 0xN1C4 - 0xN1D2 0xN1D3 0xN1C4 - 0xN1C6 0xN1D7 0xN1D8 - 0xN1DA 0xN1DB 0xN1DC - 0xN1DE 0xN1DF 0xN1E0 - 0xN1E2 0xN1E3 0xN1E4 - 0xN1E6 0xN1E7 0xN1E8 - 0xN1EA 0xN1EB 0xN1EC - 0xN1EE 0xN1EF 0xN1F0 - 0xN1F2 0xN1F3 0xN1F6 - 0xN1FF Reserved Receive STS-1 Path - AUTO AIS Control Register Reserved Receive STS-1 Path - Serial Port Control Register Reserved Receive STS-1 Path - SONET Receive Auto Alarm Register - Byte 0 Reserved Receive STS-1 Path - Receive J1 Byte Capture Register Reserved Receive STS-1 Path - Receive B3 Byte Capture Register Reserved Receive STS-1 Path - Receive C2 Byte Capture Register Reserved Receive STS-1 Path - Receive G1 Byte Capture Register Reserved Receive STS-1 Path - Receive F2 Byte Capture Register Reserved Receive STS-1 Path - Receive H4 Byte Capture Register Reserved Receive STS-1 Path - Receive Z3 Byte Capture Register Reserved Receive STS-1 Path - Receive Z4 (K3) Byte Capture Register Reserved Receive STS-1 Path - Receive Z5 Byte Capture Register Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 366 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTER DESCRIPTION 1.9.2 Table 299: Receive STS-1 Transport Control Register - Byte 0 (Address Location = 0xN103) BIT 7 Unused R/O 0 BIT 6 SF Detect Enable R/W 0 BIT 5 SD Detect Enable R/W 0 BIT 4 Descramble Disable R/W 0 BIT 3 Unused R/O 0 BIT 2 REI-L Error Type R/W 0 BIT 1 B2 Error Type R/W 0 BIT 0 B1 Error Type R/W 0 BIT NUMBER 7 6 NAME Unused SF Detect Enable TYPE R/O R/W DESCRIPTION Signal Failure (SF) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SF Detection by the Receive STS-1 TOH Processor block. 0 - SF Detection is disabled. 1 - SF Detection is enabled: 5 SD Detect Enable R/W Signal Degrade (SD) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SD Detection by the Receive STS-1 TOH Processor block. 0 - SD Detection is disabled. 1 - SD Detection is enabled. 4 Descramble Disable R/W De-Scramble Disable: This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Receive STS-1 TOH Processor block, associated with channel N. 0 - De-Scrambling is enabled. 1 - De-Scrambling is disabled. 3 2 Unused REI-L Error Type R/O R/W REI-L Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport REI-L Error Count" register is incremented. 0 - Configures the Receive STS-1 TOH Processor block to count REI-L Bit Errors. In this case the "Receive Transport REI-L Error Count" register will be incremented by the value of the lower nibble within the M0/M1 byte. 1 - Configures the Receive STS-1 TOH Processor block to count REI-L Frame Errors. In this case the "Receive Transport REI-L Error Count" register will be incremented each time the Receive STS-1 TOH Processor block receives a "non-zero" M0/M1 byte. 1 B2 Error Type R/W B2 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive 367 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transport B2 Error Count" register is incremented. 0 - Configures the Receive STS-1 TOH Processor block to count B2 bit errors. In this case, the "Receive Transport B2 Error Count" register will be incremented by the number of bits, within the B2 value, that is in error. 1 - Configures the Receive STS-1 TOH Processor block to count B2 frame errors. In this case, the "Receive Transport B2 Error Count" register will be incremented by the number of erred STS-1 frames. 0 B1 Error Type R/W B1 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport B1 Error Count" register is incremented. 0 - Configures the Receive STS-1 TOH Processor block to count B1 bit errors. In this case, the "Receive Transport B1 Error Count" register will be incremented by the number of bits, within the B1 value, that is in error. 1 - Configures the Receive STS-1 TOH Processor block to count B2 bit errors. In this case, the "Receive Transport B1 Error Count" register will be incremented by the number of erred STS-1 frames. 20 0 Rev2...0...0 200 368 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 300: Receive STS-1 Transport Status Register - Byte 1 (Address Location= 0xN106) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 J0 Message Mismatch R/O 0 BIT 1 J0 Message Unstable R/O 0 BIT 0 AIS_L Detected R/O 0 BIT NUMBER 7-3 2 NAME Unused J0 Message Mismatch TYPE R/O R/O DESCRIPTION J0 - Section Trace Mismatch Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the Section Trace Mismatch condition. The Receive STS-1 TOH Processor block will declare a J0 (Section Trace) Mismatch condition, whenever it accepts a J0 Message that differs from the "Expected J0 Message". 0 - Section Trace Mismatch Condition is NOT declared. 1 - Section Trace Mismatch Condition is currently declared. 1 J0 Message Unstable R/O J0 - Section Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the Section Trace Instability condition. The Receive STS-1 TOH Processor block will declare a J0 (Section Trace) Unstable condition, whenever the "J0 Unstable" counter reaches the value 8. The "J0 Unstable" counter will be incremented for each time that it receives a J0 message that differs from the "Expected J0 Message". The "J0 Unstable" counter is cleared to "0" whenever the Receive STS-3 TOH Processor block has received a given J0 Message 3 (or 5) consecutive times. Note: Receiving a given J0 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Section Trace Instability condition is NOT declared. 1 - Section Trace Instability condition is currently declared. 0 AIS_L Detected R/O AIS-L State: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently detecting an AIS-L (Line AIS) pattern in the incoming STS-1 data stream. AIS-L is declared if bits 6, 7 and 8 (e.g., the Least Significant Bits, within the K2 byte) value the value "1, 1, 1" for five consecutive STS-1 frames. 0 - AIS-L is NOT currently declared. 1 - AIS-L is currently being declared. 369 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 301: Receive STS-1 Transport Status Register - Byte 0 (Address Location = 0xN107) BIT 7 RDI-L Declared R/O 0 BIT 6 S1 Unstable BIT 5 APS Unstable R/O 0 BIT 4 SF Detected R/O 0 BIT 3 SD Detected R/O 0 BIT 2 LOF Defect Detected R/O 0 BIT 1 SEF Defect Declared R/O 0 BIT 0 LOS Defect Declared R/O 0 20 0 Rev2...0...0 200 R/O 0 BIT NUMBER 7 NAME RDI-L Declared TYPE R/O RDI-L Indicator: DESCRIPTION This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is detecting a Line-Remote Defect Indicator, in the incoming STS-1 signal. RDI-L is declared when bits 6, 7 and 8 (e.g., the three least significant bits) of the K2 byte contains the "1, 1, 0" pattern in 5 consecutive STS-1 frames. 0 - RDI-L is NOT being declared. 1 - RDI-L is currently being declared. 6 S1 Unstable R/O S1 Unstable Condition: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the "S1 Byte Instability" condition. The Receive STS-1 TOH Processor block will declare an "S1 Byte Instability" condition whenever the "S1 Byte Unstable Counter" reaches the value 32. The "S1 Byte Unstable Counter" is incremented for each time that the Receive STS-1 TOH Processor block receives an S1 byte that differs from the previously received S1 byte. The "S1 Byte Unstable Counter" is cleared to "0" when the same S1 byte is received for 8 consecutive STS-1 frames. Note: Receiving a given S1 byte, in 8 consecutive STS-1 frames also sets this bit-field to "0". 0 - S1 Instability Condition is NOT declared. 1 - S1 Instability Condition is currently declared. 5 APS Unstable R/O APS (K1, K2 Byte) Instability: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the "K1, K2 Byte Unstable" condition. The Receive STS-1 TOH Processor block will declare a "K1, K2 Byte Unstable" condition whenever the Receive STS-1 TOH Processor block fails to receive the same set of K1, K2 bytes, in 12 consecutive STS-1 frames. The "K1, K2 Byte Instability" condition is cleared whenever the STS-1 Receiver receives a given set of K1, K2 byte values in three consecutive STS-1 frames. 0 - K1, K2 Instability Condition is NOT declared. 1 - K1, K2 Instability Condition is currently declared. 4 SF Detected R/O SF (Signal Failure) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the SF defect. The SF defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SF Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given 370 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS interval of time) does not exceed the "SF Declaration" threshold. 1 - SF Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SF Declaration" threshold. 3 SD Detected R/O SD (Signal Degrade) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the SD defect. The SD defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SD Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given interval of time) does not exceed the "SD Declaration" threshold. 1 - SD Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SD Declaration" threshold. 2 LOF Defect Declared R/O LOF (Loss of Frame) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the LOF defect. The Receive STS-1 TOH Processor block will declare the LOF defect if it has been declaring the SEF condition for 24 consecutive STS-1 frame periods. Once the LOF defect is declared, then the Receive STS-1 TOH Processor block will clear the LOF defect if it has not been declaring the SEF condition for 3ms (or 24 consecutive STS-1 frame periods). 0 - The Receive STS-1 TOH Processor block is NOT currently declaring the LOF condition. 1 - The Receive STS-1 TOH Processor block is currently declaring the LOF condition. 1 SEF Defect Declared R/O SEF (Severely Errored Frame): This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring an SEF condition. The Receive STS-1 TOH Processor block will declare an SEF condition if it detects Framing Alignment byte errors in four consecutive STS-1 frames. Once the SEF condition is declared the Receive STS-1 TOH Processor block will clear the SEF condition if it detects two consecutive STS-1 frames with un-erred framing alignment bytes. 0 - Indicates that the Receive STS-1 TOH Processor block is NOT declaring the SEF condition. 1 - Indicates that the Receive STS-1 TOH Processor block is currently declaring the SEF condition. 0 LOS Defect Declared R/O LOS (Loss of Signal) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring an LOS (Loss of Signal) condition. The Receive STS-1 TOH Processor block will declare an LOS condition if it detects "LOS_THRESHOLD[15:0]" consecutive "All Zero" bytes in the incoming STS-1 data stream. Note: The user can set the "LOS_THRESHOLD[15:0]" value by writing the appropriate data into the "Receive STS-1 Transport - LOS Threshold Value" Register (Address Location= 0xN12E and 0xN12F). 0 - Indicates that the Receive STS-1 TOH Processor block is NOT currently 371 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS declaring an LOS condition. 1 - Indicates that the Receive STS-1 TOH Processor block is currently declaring an LOS condition. 20 0 Rev2...0...0 200 372 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 302: Receive STS-1 Transport Interrupt Status Register - Byte 2 (Address Location= 0xN109) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Interrupt Status RUR 0 BIT 0 Change of RDI-L Interrupt Status RUR 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Interrupt Status TYPE R/O RUR DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of AIS-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of AIS-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of AIS-L by reading the contents of Bit 0 (AIS-L Defect Declared) within the "Receive STS-1 Transport Status Register - Byte 1" (Address Location= 0xN106). 0 Change of RDI-L Interrupt Status RUR Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of RDI-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of RDI-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of RDI-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of RDI-L by reading out the state of Bit 7 (RDI-L Declared) within the "Receive STS-1 Transport Status Register - Byte 0" (Address Location= 0xN107). 373 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 303: Receive STS-1 Transport Interrupt Status Register - Byte 1 (Address Location= 0xN10A) BIT 7 New S1 Byte Interrupt Status BIT 6 Change in S1 Unstable State Interrupt Status RUR 0 BIT 5 Change in J0 Unstable State Interrupt Status RUR 0 BIT 4 New J0 Message Interrupt Status BIT 3 J0 Mismatch Interrupt Status BIT 2 Unused BIT 1 Change in APS Unstable State Interrupt Status RUR 0 BIT 0 NEW K1K2 Byte Interrupt Status RUR 0 RUR 0 RUR 0 R/O 0 RUR 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Status TYPE RUR DESCRIPTION New S1 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New S1 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New S1 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New S1 Byte Value" interrupt has occurred since the last read of this register. Note: The user can obtain the value for this most recently accepted value of the S1 byte by reading the "Receive STS-1 Transport S1 Value" register (Address Location= 0xN127). 6 Change in S1 Byte Unstable State Interrupt Status RUR Change in S1 Byte Unstable State - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 1 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has not occurred since the last read of this register. Note: The user can obtain the current "S1 Unstable" state by reading the contents of Bit 6 (S1 Unstable) within the "Receive STS-1 Transport Status Register - Byte 0" (Address Location= 0xN107). 5 Change in J0 Message Unstable State Interrupt Status RUR Change of J0 (Section Trace) Message Unstable condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 4 New J0 Message Interrupt Status RUR New J0 Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the 374 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS "New J0 Trace Message" interrupt has occurred since the last read of this register. 0 - Indicates that the "New J0 Trace Message Interrupt" has not occurred since the last read of this register. 1 - Indicates that the "New J0 Trace Message Interrupt" has occurred since the last read of this register. Note: The user can read out the contents of the "Receive J0 Trace Buffer", which is located at Address Locations 0xN300 through 0xN33F. 3 J0 Mismatch Interrupt Status RUR Change in J0 - Section Trace Mismatch Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared" or "declared" by reading the state of Bit 2 (J0_MIS) within the "Receive STS-1 Transport Status Register - Byte 1 (Address Location= 0xN106). 2 1 Unused Change in APS Unstable State Interrupt Status R/O RUR Change of APS (K1, K2 Byte) Instability Condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "K1, K2 Instability Condition" is being declared or cleared by reading out the contents of Bit 5 (APS_INV), within the "Receive STS-1 Transport Status Register - Byte 0" (Address Location= 0xN107). 0 New K1K2 Byte Interrupt Status RUR New K1, K2 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New K1, K2 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the new K1 byte by 375 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 reading out the contents of the "Receive STS-1 Transport K1 Value" Register (Address Location= 0xN11F). Further, the user can also obtain the contents of the new K2 byte by reading out the contents of the "Receive STS-1 Transport K2 Value" Register (Address Location= 0xN123). 376 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 304: Receive STS-1 Transport Interrupt Status Register - Byte 0 (Address Location= 0xN10B) BIT 7 Change of SF Condition Interrupt Status RUR 0 BIT 6 Change of SD Condition Interrupt Status RUR 0 BIT 5 Detection of REI-L Error Interrupt Status RUR 0 BIT 4 Detection of B2 Error Interrupt Status RUR 0 BIT 3 Detection of B1 Error Interrupt Status RUR 0 BIT 2 Change of LOF Condition Interrupt Status RUR 0 BIT 1 Change of SEF Interrupt Status RUR 0 BIT 0 Change of LOS Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Change of SF Condition Interrupt Status TYPE RUR DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of SF Interrupt" has occurred since the last read of this register. 0 - The "Change of SF Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SF Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SF" condition by reading out the state of Bit 4( SF Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 6 Change of SD Condition Interrupt Status RUR Change of Signal Degrade (SD) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SD Condition Interrupt" has occurred since the last read of this register. 0 - The "Change of SD Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SD Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SD" condition by reading out the state of Bit 3 (SD Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 5 Detection of REI-L Interrupt Status RUR Detection of Line - Remote Error Indicator Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 0 - The "Detection of Line - Remote Error Indicator" Interrupt has NOT occurred since the last read of this register. 1 - The "Detection of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 4 Detection of B2 Error Interrupt Status RUR Detection of B2 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B2 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B2 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B2 Error Interrupt" has occurred since the last read of this register. 377 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 3 Detection of B1 Error Interrupt Status RUR Detection of B1 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B1 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B1 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B1 Error Interrupt" has occurred since the last read of this register 2 Change of LOF Condition Interrupt Status RUR Change of Loss of Frame (LOF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOF Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOF Condition" interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOF Condition" interrupt has occurred since the last read of this register. Note: The user can determine the current "LOF" condition by reading out the state of Bit 2 (LOF Defect Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 20 0 Rev2...0...0 200 1 Change of SEF Condition Interrupt Status RUR Change of SEF Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SEF Condition" Interrupt has occurred since the last read of this register. 0 - The "Change of SEF Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of SEF Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "SEF" condition by reading out the state of Bit 1 (SEF Defect Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 0 Change of LOS Condition Interrupt Status RUR Change of Loss of Signal (LOS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOS Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOS Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOS Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "LOS" status by reading out the contents of Bit 0 (LOS Defect Declared) within the Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 378 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 305: Receive STS-1 Transport Interrupt Enable Register - Byte 2 (Address Location= 0xN10D) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Condition Interrupt Enable R/O 0 R/O 0 R/O 0 R/W 0 BIT 0 Change of RDI-L Condition Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Condition Interrupt Enable TYPE R/O R/W DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "AIS-L" condition. * When the STS-1 Receiver clears the "AIS-L" condition. 0 - Disables the "Change of AIS-L Condition" Interrupt. 1 - Enables the "Change of AIS-L Condition" Interrupt. 0 Change of RDI-L Condition Interrupt Enable R/W Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of RDI-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "RDI-L" condition. * When the Receive STS-1 TOH Processor clears the "RDI-L" condition. 0 - Disables the "Change of RDI-L Condition" Interrupt. 1 - Enables the "Change of RDI-L Condition" Interrupt. 379 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 306: Receive STS-1 Transport Interrupt Enable Register - Byte 1 (Address Location= 0xN10E) BIT 7 New S1 Byte Interrupt Enable BIT 6 Change in S1 Byte Unstable State Interrupt Enable R/W 0 BIT 5 Change in J0 Message Unstable State Interrupt Enable R/W 0 BIT 4 New J0 Message Interrupt Enable BIT 3 J0 Mismatch Interrupt Enable BIT 2 Unused BIT 1 Change in APS Unstable State Interrupt Enable R/W 0 BIT 0 New K1K2 Byte Interrupt Enable R/W 0 R/W 0 R/W 0 R/O 0 R/W 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Enable TYPE R/W DESCRIPTION New S1 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New S1 Byte Value" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate this interrupt anytime it receives and accepts a new S1 byte value. The Receive STS-1 TOH Processor block will accept a new S1 byte after it has received it for 8 consecutive STS-1 frames. 0 - Disables the "New S1 Byte Value" Interrupt. 1 - Enables the "New S1 Byte Value" Interrupt. 6 Change in S1 Unstable State Interrupt Enable R/W Change in S1 Byte Unstable State Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in S1 Byte Unstable State" Interrupt. If the user enables this bit-field, then the Receive STS-1 TOH Processor block will generate an interrupt in response to either of the following conditions. * * When the Receive STS-1 TOH Processor block declares the "S1 Byte Instability" condition. When the Receive STS-1 TOH Processor block clears the "S1 Byte Instability" condition. 0 - Disables the "Change in S1 Byte Unstable State" Interrupt. 1 - Enables the "Change in S1 Byte Unstable State" Interrupt. 5 Change in J0 Message Unstable State Interrupt Enable R/W Change of J0 (Section Trace) Message Instability condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of J0 Message Instability Condition" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an interrupt in response to either of the following conditions. * * Whenever the Receive STS-1 TOH Processor block declares the "J0 Message Instability" condition. Whenever the Receive STS-1 TOH Processor block clears the "J0 Message Instability" condition. 0 - Disable the "Change of J0 Message Instability" Interrupt. 1 - Enables the "Change of J0 Message Instability" Interrupt. 4 New J0 Message Interrupt Enable R/W New J0 Trace Message Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New J0 Trace Message" interrupt. If the user enables this interrupt, then the 380 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive STS-1 TOH Processor block will generate this interrupt anytime it receives and accepts a new J0 Trace Message. The Receive STS-1 TOH Processor block will accept a new J0 Trace Message after it has received it 3 (or 5) consecutive times. 0 - Disables the "New J0 Trace Message" Interrupt. 1 - Enables the "New J0 Trace Message" Interrupt. 3 J0 Mismatch Interrupt Enable R/W Change in "J0 - Section Trace Mismatch Condition" interrupt enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in J0 - Section Trace Mismatch condition" interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an interrupt in response to either of the following events. a. b. Note: The Receive STS-1 TOH Processor block declares a "J0 - Section Trace Mismatch" condition. The Receive STS-1 TOH Processor block clears the "J0 - Section Trace Mismatch" condition. The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared or "declared" by reading the state of Bit 2 (J0_MIS) within the "Receive STS-1 Transport Status Register - Byte 1 (Address Location= 0xN106). 2 1 Unused Change in APS Unstable State Interrupt Enable R/O R/W Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of APS (K1, K2 Byte) Instability condition" interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an Interrupt in response to either of the following events. a. b. If the Receive STS-1 TOH Processor block declares a "K1, K2 Instability" condition. If the Receive STS-1 TOH Processor block clears the "K1, K2 Instability" condition. 0 New K1K2 Byte Interrupt Enable R/W New K1, K2 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New K1, K2 Byte Value" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate this interrupt anytime it receives and accepts a new K1, K2 byte value. The Receive STS-1 TOH Processor block will accept a new K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-1 frames. 0 - Disables the "New K1, K2 Byte Value" Interrupt. 1 - Enables the "New K1, K2 Byte Value" Interrupt. 381 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 307: Receive STS-1Transport Interrupt Status Register - Byte 0 (Address Location= 0xN10F) BIT 7 Change of SF Condition Interrupt Enable R/W 0 BIT 6 Change of SD Condition Interrupt Enable R/W 0 BIT 5 Detection of REI-L Error Interrupt Enable R/W 0 BIT 4 Detection of B2 Error Interrupt Enable R/W 0 BIT 3 Detection of B1 Error Interrupt Enable R/W 0 BIT 2 Change of LOF Condition Interrupt Enable R/W 0 BIT 1 Change of SEF Condition Interrupt Enable R/W 0 BIT 0 Change of LOS Condition Interrupt Enable R/W 0 BIT NUMBER 7 NAME Change of SF Condition Interrupt Enable TYPE R/W DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Failure (SF) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects an SF condition. 0 - Disables the "Change of SF Condition Interrupt". 1 - Enables the "Change of SF Condition Interrupt". 6 Change of SD Condition Interrupt Enable R/W Change of Signal Degrade (SD) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Degrade (SD) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects an SD condition. 0 - Disables the "Change of SD Condition Interrupt". 1 - Enables the "Change of SD Condition Interrupt". 5 Detection of REI-L Interrupt Enable R/W Detection of Line - Remote Error Indicator Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Line - Remote Error Indicator" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects an REI-L condition. 0 - Disables the "Line - Remote Error Indicator" Interrupt. 1 - Enables the "Line - Remote Error Indicator" Interrupt. 4 Detection of B2 Error Interrupt Enable R/W Detection of B2 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B2 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects a B2 error. 0 - Disables the "Detection of B2 Error Interrupt". 1 - Enables the "Detection of B2 Error Interrupt". 3 Detection of B1 Error Interrupt Enable R/W Detection of B1 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B1 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects a B1 error. 0 - Disables the "Detection of B1 Error Interrupt". 1 - Enables the "Detection of B1 Error Interrupt". 382 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Change of LOF Condition Interrupt Enable R/W Change of Loss of Frame (LOF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "LOF" condition. * When the Receive STS-1 TOH Processor block clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 2 1 Change of SEF Condition Interrupt Enable R/W Change of SEF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of SEF Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "SEF" condition. * When the Receive STS-1 TOH Processor block clears the "SEF" condition. 0 - Disables the " Change of SEF Condition Interrupt". 1 - Enables the "Change of SEF Condition Interrupt". 0 Change of LOS Condition Interrupt Enable R/W Change of Loss of Signal (LOS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "LOF" condition. * When the Receive STS-1 TOH Processor block clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 383 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 308: Receive STS-1 Transport - B1 Error Count Register - Byte 3 (Address Location= 0xN110) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[31:24] BIT NUMBER 7-0 NAME B1_Error_Count[31:24] TYPE RUR B1 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 309: Receive STS-1 Transport - B1 Error Count Register - Byte 2 (Address Location= 0xN111) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[23:16] BIT NUMBER 7-0 NAME B1_Error_Count[23:16] TYPE RUR DESCRIPTION B1 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 310: Receive STS-1 Transport - B1 Error Count Register - Byte 1 (Address Location= 0xN112) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 384 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS B1_Error_Count[15:8] RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7-0 NAME B1_Error_Count[15:8] TYPE RUR DESCRIPTION B1 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 311: Receive STS-1 Transport - B1 Error Count Register - Byte 0 (Address Location= 0xN113) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[7:0] BIT NUMBER 7-0 NAME B1_Error_Count[7:0] TYPE RUR B1 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. 385 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 312: Receive STS-1 Transport - B2 Error Count Register - Byte 3 (Address Location= 0xN114) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[31:24] BIT NUMBER 7-0 NAME B2_Error_Count[31:24] TYPE RUR B2 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Transport - B2 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 313: Receive STS-1 Transport - B2 Error Count Register - Byte 2 (Address Location= 0xN115) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[23:16] BIT NUMBER 7-0 NAME B2_Error_Count[23:16] TYPE RUR DESCRIPTION B2 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. 386 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 314: Receive STS-1 Transport - B2 Error Count Register - Byte 1 (Address Location= 0xN116) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[15:8] BIT NUMBER 7-0 NAME B2_Error_Count[15:8] TYPE RUR DESCRIPTION B2 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 315: Receive STS-1 Transport - B2 Error Count Register - Byte 0 (Address Location= 0xN117) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[7:0] BIT NUMBER 7-0 NAME B2_Error_Count[7:0] TYPE RUR B2 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. 387 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 316: Receive STS-1 Transport - REI-L Error Count Register - Byte 3 (Address Location = 0xN118) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[31:24] BIT NUMBER 7-0 NAME REI_L_Error_Count[31:24] TYPE RUR DESCRIPTION REI-L Error Count - MSB: This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 317: Receive STS-1 Transport - REI_L Error Count Register - Byte 2 (Address Location= 0xN119) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[23:16] BIT NUMBER 7-0 NAME REI_L_Error_Count[23:16] TYPE RUR DESCRIPTION REI-L Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 388 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 318: Receive STS-1 Transport - REI_L Error Count Register - Byte 1 (Address Location= 0xN11A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[15:8] BIT NUMBER 7-0 NAME REI_L_Error_Count[15:8] TYPE RUR DESCRIPTION REI-L Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line -Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 319: Receive STS-1 Transport - REI_L Error Count Register - Byte 0 (Address Location= 0xN11B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_L_Error_Count[7:0] TYPE RUR REI-L Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 389 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 320: Receive STS-1 Transport - Received K1 Byte Value (Address Location= 0xN11F) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 Filtered_K1_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K1_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K1 value, that the Receive STS-1 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-1 frames. This register should be polled by Software in order to determine various APS codes. Table 321: Receive STS-1Transport - Received K2 Byte Value (Address Location= 0xN123) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Filtered_K2_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K2_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K2 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K2 value, that the Receive STS-1 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-1 frames. This register should be polled by Software in order to determine various APS codes. 390 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 322: Receive STS-1 Transport - Received S1 Byte Value (Address Location= 0xN127) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Filtered_S1_Value[7:0] BIT NUMBER 7-0 NAME Filtered_S1_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted S1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" S1 value that the Receive STS-1 TOH Processor block has received. These bit-fields are valid if it has been received for 8 consecutive STS-1 frames. Table 323: Receive STS-1 Transport - LOS Threshold Value - MSB (Address Location= 0xN12E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 LOS_THRESHOLD[15:8] BIT NUMBER 7-0 NAME LOS_THRESHOLD[15:8] TYPE R/W DESCRIPTION LOS Threshold Value - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - LOS Threshold Value - LSB" register specify the number of consecutive (All Zero) bytes that the Receive STS-1 TOH Processor block must detect before it can declare an LOS condition. 391 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 324: Receive STS-1 Transport - LOS Threshold Value - LSB (Address Location= 0xN12F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 20 0 Rev2...0...0 200 LOS_THRESHOLD[7:0] BIT NUMBER 7-0 NAME LOS_THRESHOLD[7:0] TYPE R/W DESCRIPTION LOS Threshold Value - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1Transport - LOS Threshold Value - MSB" register specify the number of consecutive (All Zero) bytes that the Receive STS-1 TOH Processor block must detect before it can declare an LOS condition. Table 325: Receive STS-1 Transport - Receive SF SET Monitor Interval - Byte 2 (Address Location= 0xN131 ) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[23:1 6] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into the "Receive Transport SF SET Threshold" register, then an SF condition will be declared. 392 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 326: Receive STS-1 Transport - Receive SF SET Monitor Interval - Byte 1 (Address Location= 0xN132) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[15:8] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL (Bits 15 through 8): These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SF SET Threshold" register, then an SF condition will be declared. Table 327: Receive STS-1 Transport - Receive SF SET Monitor Interval - Byte 0 (Address Location= 0xN133) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[7:0 ] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SF SET Threshold" register, then an SF condition will be declared. 393 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 328: Receive STS-1 Transport - Receive SF SET Threshold - Byte 1 (Address Location= 0xN136) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SF SET Threshold - Byte 0" register, then an SF condition will be declared. Table 329: Receive STS-1 Transport - Receive SF SET Threshold - Byte 0 (Address Location= 0xN137) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[7:0] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SF SET Threshold - Byte 1" register, then an SF condition will be declared. 394 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 330: Receive STS-1 Transport - Receive SF CLEAR Threshold - Byte 1 (Address Location= 0xN13A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [15:8] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SF CLEAR Threshold - Byte 0" register, then an SF condition will be cleared. Table 331: Receive STS-1 Transport - Receive SF CLEAR Threshold - Byte 0 (Address Location= 0xN13B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [7:0] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SF CLEAR Threshold - Byte 1" register, then an SF condition will be cleared. 395 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 332: Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 2 (Address Location= 0xN13D) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SD SET Threshold" register, then an SD condition will be declared. Table 333: Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 1 (Address Location= 0xN13E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SD SET Threshold" register, then an SD condition will be declared. 396 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 334: Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 0 (Address Location= 0xN13F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SD SET Threshold" register, then an SD condition will be declared. Table 335: Receive STS-1 Transport - Receive SD SET Threshold - Byte 1 (Address Location= 0xN142) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SD SET Threshold - Byte 0" register, then an SD condition will be declared. 397 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 336: Receive STS-1 Transport - Receive SD SET Threshold - Byte 0 (Address Location= 0xN143) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SD SET Threshold - Byte 1" register, then an SD condition will be declared. Table 337: Receive STS-1 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0xN146) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD [15:8] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SD CLEAR Threshold - Byte 0" register, then an SD condition will be cleared. 398 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 338: Receive STS-1 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0xN147) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SD CLEAR Threshold - Byte 1" register, then an SD condition will be cleared. Table 339: Receive STS-1 Transport - Force SEF Condition Register (Address Location= 0xN14B) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 SEF FORCE R/W 0 BIT NUMBER 7-1 0 NAME Unused SEF FORCE TYPE R/O R/W SEF Force: DESCRIPTION This READ/WRITE bit-field permits the user to force the Receive STS-1 TOH Processor block (within Channel N) to declare an SEF defect. The Receive STS-1 TOH Processor block will then attempt to reacquire framing. Writing a "1" into this bit-field configures the Receive STS-1 TOH Processor block to declare the SEF defect. The Receive STS-1 TOH Processor block will automatically set this bit-field to "0" once it has reacquired framing (e.g., has detected two consecutive STS-1 frames with the correct A1 and A2 bytes). 399 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 340: Receive STS-1 Transport - Receive J0 Trace Buffer Control Register (Address Location= 0xN14F) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 READ SEL R/W 0 BIT 3 ACCEPT THRD R/W 0 BIT 2 MSG TYPE R/W 0 R/W 0 BIT 1 MSG LENGTH R/W 0 BIT 0 BIT NUMBER 7-5 4 NAME Unused READ SEL TYPE R/O R/W J0 Buffer Read Selection: DESCRIPTION This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. a. b. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive J0 Trace Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive J0 Trace Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Receive STS-3 TOH Processor block, the "Receive J0 Trace Buffer" is located at Address Location 0xN300 through 0xN33F. 3 ACCEPT THRD R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-1 TOH Processor block must receive a given J0 Trace Message, before it is accepted, as described below. 0 - The Receive STS-1 TOH Processor block accepts the J0 Message after it has received it the third time in succession. 1 - The Receive STS-1 TOH Processor block accepts the J0 Message after it has received in the fifth time in succession. 2 MSG TYPE R/W Message Alignment Type: This READ/WRITE bit-field permits a user to specify have the Receive STS-1 TOH Processor block will locate the boundary of the J0 Trace Message, as indicated below. 0 - Message boundary is indicated by "Line Feed". 1 - Message boundary is indicated by the presence of a "1" in the MSB of the first byte (within the J0 Trace Message). 1-0 MSG LENGTH R/W J0 Message Length: These READ/WRITE bit-fields permit the user to specify the length of the J0 Trace Message, that the Receive STS-1 TOH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J0 Trace Message Length is presented below. MSG LENGTH Resulting J0 Trace Message Length 400 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 00 01 10/11 1 Byte 16 Bytes 64 Bytes Table 341: Receive STS-1 Transport - Receive SD Burst Error Tolerance - Byte 1 (Address Location= 0xN152) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SD_BURST_TOLERANCE [15:8] TYPE R/W DESCRIPTION SD_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SD BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. 401 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 342: Receive STS-1 Transport - Receive SD Burst Error Tolerance - Byte 0 (Address Location= 0xN153) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_BURST_TOLERANCE[7:0] BIT NUMBER 7-0 NAME SD_BURST_TOLERANCE[7:0] TYPE R/W DESCRIPTION SD_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SD BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SD (Signal Degrade) condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. 402 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 343: Receive STS-1 Transport - Receive SF Burst Error Tolerance - Byte 1 (Address Location= 0xN156) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SF_BURST_TOLERANCE[15:8] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SF BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SF (Signal Failure) condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SF defect condition. 403 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 344: Receive STS-1 Transport - Receive SF Burst Error Tolerance - Byte 0 (Address Location= 0xN157) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_BURST_TOLERANCE[7:0] BIT NUMBER 7-0 NAME SF_BURST_TOLERANCE[7:0] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SF BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SF (Signal Failure) condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "SubInterval" periods before it will declare the SF defect condition. Table 345: Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 2 (Address Location= 0xN159) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-1 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SD Clear Threshold" register, then the SD defect will be cleared. 404 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 346: Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 1 (Address Location= 0xN15A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-1 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 347: Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 0 (Address Location= 0xN15B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-1 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SD Clear Threshold" register, then the SD defect will be cleared. 405 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 348: Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 2 (Address Location= 0xN15D) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SF Clear Threshold" register, then the SF defect will be cleared. Table 349: Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 1 (Address Location= 0xN15E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SF Clear Threshold" register, then the SF defect will be cleared. 406 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 350: Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 0 (Address Location= 0xN15F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SF Clear Threshold" register, then the SF defect will be cleared. 407 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 351: Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163) BIT 7 Transmit AIS-P (Downstream) upon J0 Message Unstable BIT 6 Transmit AIS-P (Downstream) Upon Section Trace Message Mismatch R/W 0 BIT 5 Transmit AIS-P (Downstream) upon SF BIT 4 Transmit AIS-P (Downstream) upon SD BIT 3 Unused BIT 2 Transmit AIS-P (Downstream) upon LOF BIT 1 Transmit AIS-P (Downstream) upon LOS BIT 0 Transmit AIS-P (Downstream) Enable 20 0 Rev2...0...0 200 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME Transmit AIS-P (Downstream) upon J0 Message Unstable TYPE R/W DESCRIPTION Transmit Path AIS upon Detection of Unstable Section Trace (J0): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor blocks), anytime it detects an Unstable Section Trace (J0) condition in the "incoming" STS-1 datastream. 0 - Does not configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. 1 - Configures the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 6 Transmit AIS-P (Downstream) Upon J0 Message Mismatch R/W Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0) Mismatch: This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor blocks), anytime it detects a Section Trace (J0) Mismatch condition in the "incoming" STS-1 data stream. 0 - Does not configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Mismatch" condition. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Mismatch" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Downstream) upon SF R/W Transmit Path AIS upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Receive 408 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block), anytime it declares an SF condition. 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF detect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Downstream) upon SD R/W Transmit Path AIS upon Signal Degrade (SD): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block) anytime it declares an SD condition. 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 2 Unused Transmit AIS-P (Downstream) upon LOF R/O R/W Transmit Path AIS upon Loss of Frame (LOF): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block), anytime it declares an LOF condition. 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Downstream) upon LOS R/W Transmit Path AIS upon Loss of Signal (LOS): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block), anytime it declares an LOS condition. 409 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 AUTO AIS R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit the Path AIS (AIS-P) indicator, via the down-stream traffic (e.g., towards the Receive STS-1 POH Processor block), upon detection of an SF, SD, Section Trace Mismatch, Section Trace Unstability, LOF or LOS conditions. It also permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS1 POH Processor block) anytime it detects an AIS-L condition in the "incoming" STS-1 datastream. 0 - Configures the Receive STS-1 TOH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of the AIS-L or any of the "above-mentioned" conditions. 1 - Configures the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of the AIS-L or any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this register) to "1" in order to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 410 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 352: Receive STS-1 Transport - Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0xN16B) BIT 7 Unused BIT 6 BIT 5 Transmit AISP (via Downstream STS-1s) upon LOS R/O 0 R/W 0 BIT 4 Transmit AISP (via Downstream STS-1s) upon LOF R/W 0 BIT 3 Transmit AISP (via Downstream STS-1s) upon SD R/W 0 BIT 2 Transmit AISP (via Downstream STS-1s) upon SF R/W 0 BIT 1 Unused BIT 0 Transmit AIS-P (via Downstream STS-1s) Enable R/W 0 R/O 0 R/O 0 BIT NUMBER 7-6 5 NAME Unused Transmit AIS-P (via Downstream STS-1s) upon LOS TYPE R/O R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of Signal): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOS defect. 0 - Does not configure the corresponding Transmit SONET POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOS defect. 1 - Configure the corresponding Transmit SONETPOH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOS defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 1 (Transmit AIS-P Down-stream - Upon LOS), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor block to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares the LOS defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOS), several SONET frame periods are required (after the Receive STS-1 TOH Processor block has declared the LOS defect), before the corresponding Transmit SONET POH Processor block will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 4 Transmit AIS-P (via Downstream STS-1s) upon LOF R/W Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of Frame): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to 411 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOF defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOF defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOF defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 2 (Transmit AIS-P Down-stream - Upon LOF), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares the LOF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOF defect. In the case of Bit 2 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the LOS defect), before the corresponding Transmit SONET POH Processor block will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 3 Transmit AIS-P (via Downstream STS-1s) upon SD R/W Transmit AIS-P (via Downstream STS-1s) upon SD (Signal Degrade): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SD defect. 0 - Does not configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SD defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SD defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 4 (Transmit AIS-P Down-stream - Upon SD), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares 412 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS the SD defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Receive STS-1 TOH Processor block has declared the SD defect), before the corresponding Transmit SONET POH Processor block will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 2 Transmit AIS-P (via Downstream STS-1s) upon SF R/W Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares an SF condition. 0 - Does not configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SF defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SF defect. Note: In the "long-run" the function of this bit-field is exactly the same as that of Bit 5 (Transmit AIS-P Down-stream - Upon SF), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares the SF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the SF defect. In the case of Bit 5 (Transmit AIS-P Downstream - Upon SF), several SONET frame periods are required (after the Receive STS-1 TOH Processor block has declared the SF defect), before the corresponding Transmit SONET POH Processor blocks will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 1 0 Unused Transmit AIS-P (via Downstream STS-1s) Enable R/O R/W Automatic Transmission of AIS-P (via the downstream STS-1s) Enable: This READ/WRITE bit-field permits the user to configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P indicator, via its "outbound" STS-1 signal (within the outbound STS-3 signal), upon detection of an SF, SD, LOS and LOF condition via the Receive STS-1 TOH Processor block. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P indicator, whenever the Receive STS-1 TOH Processor block declares either the LOS, LOF, 413 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS SD or the SF defects. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P indicator, whenever the Receive STS-1 TOH Processor block declares either the LOS, LOF, SD or the SF defects. 20 0 Rev2...0...0 200 414 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 353: Receive STS-1 Path - Control Register - Byte 2 (Address Location= 0xN183) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 Check Stuff R/W 0 BIT 2 RDI-P Type R/W 0 BIT 1 REI-P Error Type R/W 0 BIT 0 B3 Error Type R/W 0 BIT NUMBER 7-4 3 NAME Unused Check Stuff TYPE R/O R/W DESCRIPTION Check (Pointer Adjustment) Stuff Select: This READ/WRITE bit-field permits the user to enable/disable the SONET standard recommendation that a pointer increment or decrement operation, detected within 3 SONET frames of a previous pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. 0 - Disables this SONET standard implementation. In this mode, all pointeradjustment operations that are detected will be accepted. 1 - Enables this "SONET standard" implementation. In this mode, all pointeradjustment operations that are detected within 3 SONET frame periods of a previous pointer-adjustment operation, will be ignored. 2 RDI-P Type R/W Path - Remote Defect Indicator Type Select: This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to support either the "Single-Bit" or the "Enhanced" RDIP, as described below. 0 - Configures the Receive STS-1 POH Processor block to support the Single-Bit RDI-P. In this mode, the Receive STS-1 POH Processor block will only monitor Bit 5, within the G1 byte (of the incoming SPE data), in order to declare and clear the RDI-P indicator. 1 - Configures the Receive STS-1 POH Processor block to support the Enhanced RDI-P (ERDI-P). In this mode, the Receive STS-1 POH Processor block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare and clear the RDI-P indicator. 1 REI-P Error Type R/W REI-P Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Path REI-P Error Count" register is incremented. 0 - Configures the Receive STS-1 POH Processor block to count REI-P Bit Errors. In this case, the "Receive Path REI-P Error Count" register will be incremented by the value of the lower nibble within the G1 byte. 1 - Configures the Receive STS-1 POH Processor block to count REI-P Frame Errors. In this case, the "Receive Path REI-P Error Count" register will be incremented by a single count each time the Receive STS-1 POH Processor block receives a G1 byte, in which bits 1 through 4 are set to a "non-zero" value. 0 B3 Error Type R/W B3 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Path B3 Error Count" register is incremented. 415 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 0 - Configures the Receive STS-1 POH Processor block to count B3 bit errors. In this case, the "Receive Path B3 Error Count" register will be incremented by the number of bits, within the B3 value, that is in error. 1 - Configures the Receive STS-1 POH Processor block to count B3 frame errors. In this case, the "Receive Path B3 Error Count" register will be incremented by the number of erred STS-1 frames. 416 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 354: Receive STS-1 Path - Control Register - Byte 1 (Address Location= 0xN186) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 J1 Unstable Indicator R/O 0 R/O 0 R/O 0 R/W 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-1 0 NAME Unused J1 Unstable Indicator TYPE R/O R/O DESCRIPTION J1 - Path Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the Path Trace Unstable condition. The Receive STS-1 POH Processor block will declare a J1 (Path Trace) Unstable condition, whenever the "J1 Unstable" counter reaches the value "8". The "J0 Unstable" counter will be incremented for each time that it receives a J1 message that differs from the previously received message. The "J1 Unstable" counter is cleared to "0" whenever the Receive STS-1 POH Processor block has received a given J1 Message 3 (or 5) consecutive times. Note: Receiving a given J1 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Path Trace Instability condition is NOT declared. 1 - Path Trace Instability condition is currently declared. 417 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 355: Receive STS-1 Path - SONET Receive POH Status - Byte 0 (Address Location= 0xN187) BIT 7 TIM-P Defect Declared R/O 0 BIT 6 C2 Byte Unstable Condition R/O 0 BIT 5 UNEQ-P Defect Declared R/O 0 BIT 4 PLM-P Defect Declared R/O 0 BIT 3 RDI-P Defect Declared R/O 0 BIT 2 RDI-P Unstable Condition R/O 0 BIT 1 LOP-P Defect Declared R/O 0 BIT 0 AIS-P Defect Declared R/O 0 BIT NUMBER 7 NAME TIM-P Defect Declared TYPE R/O DESCRIPTION Trace Identification Mismatch (TIM-P) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the "Trace Identification Mismatch" condition. The Receive STS-1 POH Processor block will declare the "TIM-P" condition, when none of the received 64 byte string (received via the J1 byte) matches the expected 64 byte message. The Receive STS-1 POH Processor block will clear the "TIM-P" condition, when 80% of the received 64 byte string (received via the J1 byte) matches the expected 64 byte message. 0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the TIM-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the TIM-P condition. 6 C2 Byte Unstable Condition R/O C2 Byte (Path Signal Label Byte) Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the "Path Signal Label Byte" Unstable condition. The Receive STS-1 POH Processor block will declare a C2 (Path Signal Label Byte) Unstable condition, whenever the "C2 Unstable" counter reaches the value "5". The "C2 Unstable" counter will be incremented for each time that it receives an SPE with a C2 byte value that differs from the previously received C2 byte value. The "C2 Unstable" counter is cleared to "0" whenever the Receive STS-1 POH Processor block has received 3 (or 5) consecutive SPEs of the same C2 byte value. Note: Receiving a given C2 byte value in 3 (or 5) consecutive SPEs also sets this bit-field to "0". 0 - C2 (Path Signal Label Byte) Unstable condition is NOT declared. 1 - C2 (Path Signal Label Byte) Unstable condition is currently declared. 5 UNEQ-P R/O Path - Unequipped Indicator (UNEQ-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the UNEQ-P condition. The Receive STS-1 POH Processor block will declare a UNEQ-P condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to 0x00 (which indicates that the SPE is "Unequipped"). The Receive STS-1 POH Processor block will clear the UNEQ-P condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to a value other than 0x00. 0 - Indicates that the Receive STS-1 POH Processor block is NOT declaring the 418 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS UNEQ-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the UNEQ-P condition. Note: The Receive STS-1 POH Processor block will not declare the UNEQ-P condition if it configured to expect to receive STS-1 frames with C2 bytes being set to "0x00" (e.g., if the "Receive STS-1 Path - Expected Path Label Value" Register -Address Location= 0xN197) is set to "0x00". 4 PLM-P Defect Declared R/O Path Payload Mismatch Indicator (PLM-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the PLM-P condition. The Receive STS-1 POH Processor block will declare an PLM-P condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to a value other than that which it is expecting to receive. Whenever the Receive STS-1 POH Processor block is determine whether or not it should declare the PLM-P defect, it checks the contents of the following two registers. * The "Receive STS-1 Path - Received Path Label Value" Register (Address Location= 0xN196). * The "Receive STS-1 Path - Expected Path Label Value" Register (Address Location= 0xN197). The "Receive STS-1 Path - Expected Path Label Value" Register contains the value of the C2 bytes, that the Receive STS-1 POH Processor blocks expects to receive. The "Receive STS-1 Path - Received Path Label Value" Register contains the value of the C2 byte, that the Receive STS-1 POH Processor block has most received "validated" (by receiving this same C2 byte in five consecutive STS-1 frames). The Receive STS-1 POH Processor block will declare a PLM-P condition, if the contents of these two register do not match. The Receive STS-1 POH Processor block will clear the PLM-P condition if whenever the contents of these two registers do match. 0 - PLM-P defect is currently not being declared. 1 - PLM-P defect is currently being declared. Note: The Receive STS-1 POH Processor block will clear the PLM-P defect, upon detecting the UNEQ-P condition. 3 RDI-P R/O Path Remote Defect Indicator (RDI-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the RDI-P condition. If the Receive STS-1 POH Processor block is configured to support the "Single-bit RDI-P" function, then it will declare an RDI-P condition if Bit 5 (within the G1 byte of the incoming STS-1 frame) is set to "1" for "RDI-P_THRD" number of consecutive STS-1 frames. If the Receive STS-1 POH Processor block is configured to support the Enhanced RDI-P" (ERDI-P) function, then it will declare an RDI-P condition if Bits 5, 6 and 7 (within the G1 byte of the incoming STS-1 frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for "RDI-P_THRD" number of consecutive STS-1 frames. 0 - Indicates that the Receive STS-1 POH Processor block is NOT declaring an RDI-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring an RDI-P condition. 419 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Note: 20 0 Rev2...0...0 200 The user can specify the value for "RDI-P_THRD" by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the "Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0xN193). 2 RDI-P Unstable R/O RDI-P (Path - Remote Defect Indicator) Unstable: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the "RDI-P Unstable" condition. The Receive STS-1 POH Processor block will declare a "RDI-P I Unstable" condition whenever the "RDI-P Unstable Counter" reaches the value "RDI-P THRD". The "RDI-P Unstable" counter is incremented for each time that the Receive STS-1 POH Processor block receives an RDI-P value that differs from that of the previous STS-1 frame. The "RDI-P Unstable" counter is cleared to "0" whenever the same RDI-P value is received in "RDI-P_THRD" consecutive STS-1 frames. Note: Receiving a given RDI-P value, in "RDI-P_THRD" consecutive STS-1 frames also clears this bit-field to "0". 0 - RDI-P Unstable condition is NOT declared. 1 - RDI-P Unstable condition is currently declared. Note: The user can specify the value for "RDI-P_THRD" by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the "Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0xN193). 1 LOP-P Defect Declared R/O Loss of Pointer Indicator (LOP-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the LOP (Loss of Pointer) condition. The Receive STS-1 POH Processor block will declare the LOP-P condition, if it cannot detect a valid pointer (H1 and H2 bytes, within the TOH) within 8 to 10 consecutive SONET frames. Further, the Receive STS-1 POH Processor block will declare the LOP-P condition, if it detects 8 to 10 consecutive NDF events. The Receive STS-1 POH Processor block will clear the LOP-P condition, whenever the Receive STS-1 POH Processor detects valid pointer bytes (e.g., the H1 and H2 bytes, within the TOH) and normal NDF value for three consecutive STS-1 frames. 0 - Indicates that the Receive STS-1 POH Processor block is NOT declaring the LOP-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the LOP-P condition. 0 AIS-P R/O Path AIS (AIS-P) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring an AIS-P condition. The Receive STS-1 POH Processor block will declare an AIS-P if it detects all of the following conditions for three consecutive STS-1 frames. * * The H1, H2 and H3 bytes are set to an "All Ones" pattern. The entire SPE is set to an "All Ones" pattern. The Receive STS-1 POH Processor block will clear the AIS-P indicator when it detects a valid STS-1 pointer (H1 and H2 bytes) and a "set" or "normal" NDF for three consecutive STS-1 frames. 0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the AIS-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the AIS-P condition. Note: The Receive STS-1 POH Processor block will NOT declare the LOP-P 420 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS condition if it detects an "All Ones" pattern in the H1, H2 and H3 bytes. It will, instead, declare the AIS-P condition. 421 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 356: Receive STS-1 Path - SONET Receive Path Interrupt Status - Byte 2 (Address Location= 0xN189) BIT 7 BIT 6 Unused BIT 5 BIT 4 Detection of AIS Pointer Interrupt Status R/O 0 RUR 0 BIT 3 Detection of Pointer Change Interrupt Status RUR 0 BIT 2 Unused BIT 1 Change in TIM-P Condition Interrupt Status RUR 0 BIT 0 Change in J1 Unstable Condition Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused Detection of AIS Pointer Interrupt Status TYPE R/O RUR DESCRIPTION Detection of AIS Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of AIS Pointer" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate this interrupt anytime it detects an "AIS Pointer" in the incoming STS-1 data stream. Note: An "AIS Pointer" is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an "All Ones" pattern. 0 - Indicates that the "Detection of AIS Pointer" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of AIS Pointer" interrupt has occurred since the last read of this register. 3 Detection of Pointer Change Interrupt Status RUR Detection of Pointer Change Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Change" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it accepts a new pointer value (e.g., H1 and H2 bytes, in the TOH bytes). 0 - Indicates that the "Detection of Pointer Change" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Change" Interrupt has occurred since the last read of this register. 2 1 Unused Change in TIM-P Condition Interrupt Status R/O RUR Change in TIM-P (Trace Identification Mismatch) Condition Interrupt. This RESET-upon-READ bit-field indicates whether or not the "Change in TIM-P" Condition interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. 422 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS * If the TIM-P condition is declared. * If the TIM-P condition is cleared. 0 - Indicates that the "Change in TIM-P Condition" Interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in TIM-P Condition" Interrupt has occurred since the last read of this register. 0 Change in J1 Unstable Condition Interrupt Status RUR Change in "J1 (Trace Identification Message) Unstable Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J1 Unstable Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declare the "J1 Unstable" Condition. * When the Receive STS-1 POH Processor block clears the "J1 Unstable" condition. 0 - Indicates that the "Change in J1 Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in J1 Unstable Condition" Interrupt has occurred since the last read of this register. 423 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 357: Receive STS-1 Path - SONET Receive Path Interrupt Status - Byte 1 (Address Location= 0xN18A) BIT 7 New J1 Message Interrupt Status BIT 6 Detection of REI-P Event Interrupt Status BIT 5 Change in UNEQ-P Condition Interrupt Status RUR 0 BIT 4 Change in PLM-P Condition Interrupt Status RUR 0 BIT 3 New C2 Byte Interrupt Status BIT 2 Change in C2 Byte Unstable Condition Interrupt Status RUR 0 BIT 1 Change in RDI-P Unstable Condition Interrupt Status RUR 0 BIT 0 New RDI-P Value Interrupt Status RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7 NAME New J1 Message Interrupt Status TYPE RUR DESCRIPTION New J1 (Trace Identification) Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New J1 Message" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted (or validated) and new J1 (Trace Identification) Message. 0 - Indicates that the "New J1 Message" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New J1 Message" Interrupt has occurred since the last read of this register. 6 Detection of REI-P Event Interrupt Status RUR Detection of REI-P Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of REI-P Event" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an REI-P condition in the coming STS-1 data-stream. 0 - Indicates that the "Detection of REI-P Event" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of REI-P Event" Interrupt has occurred since the last read of this register. 5 Change in UNEQ-P Condition Interrupt Status RUR Change in UNEQ-P (Path - Unequipped) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in UNEQ-P Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the UNEQ-P Condition. * When the Receive STS-1 POH Processor block clears the UNEQ-P Condition. 0 - Indicates that the "Change in UNEQ-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in UNEQ-P Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of UNEQ-P by reading 424 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS out the state of Bit 5 (UNEQ-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 4 Change in PLMP Condition Interrupt Status RUR Change in PLM-P (Path - Payload Mismatch) Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the "Change in PLM-P Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the "PLM-P" Condition. * When the Receive STS-1 POH Processor block clears the "PLM-P" Condition. 0 - Indicates that the "Change in PLM-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in PLM-P Condition" Interrupt has occurred since the last read of this register. 3 New C2 Byte Interrupt Status RUR New C2 Byte Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New C2 Byte" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 - Indicates that the "New C2 Byte" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New C2 Byte" Interrupt has occurred since the last read of this register. 2 Change in C2 Byte Unstable Condition Interrupt Status RUR Change in C2 Byte Unstable Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in C2 Byte Unstable Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares the "C2 Byte Unstable" condition. * When the Receive STS-1 POH Processor block clears the "C2 Byte Unstable" condition. 0 - Indicates that the "Change in C2 Byte Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in C2 Byte Unstable Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of "C2 Byte Unstable Condition" by reading out the state of Bit 6 (C2 Byte Unstable Condition) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 1 Change in RDIP Unstable Condition Interrupt Status RUR Change in RDI-P Unstable Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in RDI-P Unstable Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will 425 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares an "RDI-P Unstable" condition. * When the Receive STS-1 POH Processor block clears the "RDI-P Unstable" condition. 0 - Indicates that the "Change in RDI-P Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in RDI-P Unstable Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of "RDI-P Unstable" by reading out the state of Bit 2 (RDI-P Unstable Condition) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 0 New RDI-P Value Interrupt Status RUR New RDI-P Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New RDI-P Value" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate this interrupt anytime it receives and "validates" a new RDI-P value. 0 - Indicates that the "New RDI-P Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New RDI-P Value" Interrupt has occurred since the last read of this register. Note: The user can obtain the "New RDI-P Value" by reading out the contents of the "RDI-P ACCEPT[2:0]" bit-fields. These bit-fields are located in Bits 6 through 4, within the "Receive STS-1 Path - SONET Receive RDI-P Register" (Address Location= 0xN193). 426 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 358: Receive STS-1 Path - SONET Receive Path Interrupt Status - Byte 0 (Address Location= 0xN18B) BIT 7 Detection of B3 Byte Error Interrupt Status RUR 0 BIT 6 Detection of New Pointer Interrupt Status RUR 0 BIT 5 Detection of Unknown Pointer Interrupt Status RUR 0 BIT 4 Detection of Pointer Decrement Interrupt Status RUR 0 BIT 3 Detection of Pointer Increment Interrupt Status RUR 0 BIT 2 Detection of NDF Pointer Interrupt Status RUR 0 BIT 1 Change of LOP-P Condition Interrupt Status RUR 0 BIT 0 Change of AIS-P Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Detection of B3 Byte Error Interrupt Status TYPE RUR DESCRIPTION Detection of B3 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B3 Byte Error" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a B3 byte error in the incoming STS-1 data stream. 0 - Indicates that the "Detection of B3 Byte Error" Interrupt has NOT occurred since the last read of this interrupt. 1 - Indicates that the "Detection of B3 Byte Error" Interrupt has occurred since the last read of this interrupt. 6 Detection of New Pointer Interrupt Status RUR Detection of New Pointer Interrupt Status: This RESET-upon-READ indicates whether the "Detection of New Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-1 frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 - Indicates that the "Detection of New Pointer" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of New Pointer" Interrupt has occurred since the last read of this register. 5 Detection of Unknown Pointer Interrupt Status RUR Detection of Unknown Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Unknown Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime that it detects a "pointer" that does not fit into any of the following categories. * An Increment Pointer * A Decrement Pointer * An NDF Pointer * An AIS (e.g., All Ones) Pointer * New Pointer 0 - Indicates that the "Detection of Unknown Pointer" interrupt has NOT 427 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS occurred since the last read of this register. 1 - Indicates that the "Detection of Unknown Pointer" interrupt has occurred since the last read of this register. 4 Detection of Pointer Decrement Interrupt Status RUR Detection of Pointer Decrement Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Decrement" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Decrement" event. 0 - Indicates that the "Detection of Pointer Decrement" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Decrement" interrupt has occurred since the last read of this register. 3 Detection of Pointer Increment Interrupt Status RUR Detection of Pointer Increment Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Increment" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Increment" event. 0 - Indicates that the "Detection of Pointer Increment" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Increment" interrupt has occurred since the last read of this register. 2 Detection of NDF Pointer Interrupt Status RUR Detection of NDF Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of NDF Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 - Indicates that the "Detection of NDF Pointer" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of NDF Pointer" interrupt has occurred since the last read of this register. 1 Change of LOP-P Condition Interrupt Status RUR Change of LOP-P Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in LOP-P Condition" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * * 20 0 Rev2...0...0 200 When the Receive STS-1 POH Processor block declares an "Loss of Pointer" condition. When the Receive "STS-1 POH Processor" block clears the "Loss of Pointer" condition. 0 - Indicates that the "Change in LOP-P Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in LOP-P Condition" interrupt has 428 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS occurred since the last read of this register. Note: The user can determine the current state of LOP-P by reading out the state of Bit 1 (LOP-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location=0xN187). 0 Change of AIS-P Condition Interrupt Status RUR Change of AIS-P Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-P Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares an AIS-P condition. * When the Receive STS-1 POH Processor block clears the AIS-P condition. 0 - Indicates that the "Change of AIS-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of AIS-P Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of AIS-P by reading out the state of Bit 0 (AIS-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 429 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 359: Receive STS-1 Path - SONET Receive Path Interrupt Enable - Byte 2 (Address Location = 0xN18D) BIT 7 BIT 6 Unused BIT 5 BIT 4 Detection of AIS Pointer Interrupt Enable R/O 0 R/W 0 BIT 3 Detection of Pointer Change Interrupt Enable R/W 0 BIT 2 Unused BIT 1 Change in TIM-P Condition Interrupt Enable R/W 0 BIT 0 Change in J1 Unstable Condition Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused Detection of AIS Pointer Interrupt Enable TYPE R/O R/W DESCRIPTION Detection of AIS Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of AIS Pointer" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an "AIS Pointer", in the incoming STS-1 data stream. Note: An "AIS Pointer" is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an "All Ones" Pattern. 0 - Disables the "Detection of AIS Pointer" Interrupt. 1 - Enables the "Detection of AIS Pointer" Interrupt. 3 Detection of Pointer Change Interrupt Enable R/W Detection of Pointer Change Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Pointer Change" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted a new pointer value. 0 - Disables the "Detection of Pointer Change" Interrupt. 1 - Enables the "Detection of Pointer Change" Interrupt. 2 1 Unused Change in TIM-P Condition Interrupt Enable R/O R/W Change in TIM-P (Trace Identification Mismatch) Condition Interrupt: This READ/WRITE bit-field permits the user to either enable or disable the "Change in TIM-P Condition" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * If the TIM-P condition is declared. * If the TIM-P condition is cleared. 0 - Disables the "Change in TIM-P Condition" Interrupt. 1 - Enables the "Change in TIM-P Condition" Interrupt. 0 Change in J1 Unstable Condition Interrupt R/W Change in "J1 (Trace Identification Condition" Interrupt Status: Message) Unstable 430 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Enable Condition" Interrupt Status: This READ/WRITE bit-field permits the user to either enable or disable the "Change in J1 (Trace Identification) Message Unstable Condition" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares the "J1 Unstable" Condition. * When the Receive STS-1 POH Processor block clears the "J1 Unstable" Condition. 0 - Disables the "Change in J1 Message Unstable Condition" interrupt. 1 - Enables the "Change in J1 Message Unstable Condition" interrupt. 431 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 360: Receive STS-1 Path - SONET Receive Path Interrupt Enable - Byte 1 (Address Location= 0xN18E) BIT 7 New J1 Message Interrupt Enable BIT 6 Detection of REI-P Event Interrupt Enable BIT 5 Change in UNEQ-P Condition Interrupt Enable R/W 0 BIT 4 Change in PLM-P Condition Interrupt Enable R/W 0 BIT 3 New C2 Byte Interrupt Enable BIT 2 Change in C2 Byte Unstable Condition Interrupt Enable R/W 0 BIT 1 Change in RDI-P Unstable Condition Interrupt Enable R/W 0 BIT 0 New RDI-P Value Interrupt Enable R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME New J1 Message Interrupt Enable TYPE R/W DESCRIPTION New J1 (Trace Identification) Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New J1 Message" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted (or validated) and new J1 (Trace Identification) Message. 0 - Disables the "New J1 Message" Interrupt. 1 - Enables the "New J1 Message" Interrupt. 6 Detection of REI-P Event Interrupt Enable R/W Detection of REI-P Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of REI-P Event" Interrupt. If this interrupt is enabled, then he Receive STS-1 POH Processor block will generate an interrupt anytime it detects an REI-P condition in the coming STS-1 data-stream. 0 - Disables the "Detection of REI-P Event" Interrupt. 1 - Enables the "Detection of REI-P Event" Interrupt. 5 Change in UNEQ-P Condition Interrupt Enable R/W Change in UNEQ-P (Path - Unequipped) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in UNEQ-P Condition" interrupt. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the UNEQP Condition. * When the Receive STS-1 POH Processor block clears the UNEQ-P Condition. 0 - Disables the "Change in UNEQ-P Condition" Interrupt. 1 - Enables the "Change in UNEQ-P Condition" Interrupt. 4 Change in PLM-P Condition Interrupt Enable R/W Change in PLM-P (Path - Payload Mismatch) Condition Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the "Change in PLM-P Condition" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor 432 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the "PLMP" Condition. * When the Receive STS-1 POH Processor block clears the "PLM-P" Condition. 0 - Disables the "Change in PLM-P Condition" Interrupt. 1 - Enables the "Change in PLM-P Condition" Interrupt. 3 New C2 Byte Interrupt Enable R/W New C2 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New C2 Byte" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 - Disables the "New C2 Byte" Interrupt. 1 - Enables the "New C2 Byte" Interrupt. Note: The user can obtain the value of this "New C2" byte by reading the contents of the "Receive STS-1 Path - Received Path Label Value" Register (Address Location= 0xN196). 2 Change in C2 Byte Unstable Condition Interrupt Enable R/W Change in C2 Byte Unstable Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in C2 Byte Unstable Condition" Interrupt. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares the "C2 Byte Unstable" condition. * When the Receive STS-1 POH Processor block clears the "C2 Byte Unstable" condition. 0 - Disables the "Change in C2 Byte Unstable Condition" Interrupt. 1 - Enables the "Change in C2 Byte Unstable Condition" Interrupt. 1 Change in RDI-P Unstable Condition Interrupt Enable R/W Change in RDI-P Unstable Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in RDI-P Unstable Condition" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares an "RDI-P Unstable" condition. * When the Receive STS-1 POH Processor block clears the "RDI-P Unstable" condition. 0 - Disables the "Change in RDI-P Unstable Condition" Interrupt. 1 - Enables the "Change in RDI-P Unstable Condition" Interrupt. 0 New RDI-P Value Interrupt Enable R/W New RDI-P Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New RDI-P Value" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate this interrupt anytime it receives and "validates" a 433 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS new RDI-P value. 0 - Disables the "New RDI-P Value" Interrupt. 1 - Enable the "New RDI-P Value" Interrupt. 20 0 Rev2...0...0 200 434 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 361: Receive STS-1 Path - SONET Receive Path Interrupt Enable - Byte 0 (Address Location= 0xN18F) BIT 7 Detection of B3 Byte Error Interrupt Enable R/W 0 BIT NUMBER 7 BIT 6 Detection of New Pointer Interrupt Enable R/W 0 NAME Detection of B3 Byte Error Interrupt Enable TYPE R/W BIT 5 Detection of Unknown Pointer Interrupt Enable R/W 0 BIT 4 Detection of Pointer Decrement Interrupt Enable R/W 0 BIT 3 Detection of Pointer Increment Interrupt Enable R/W 0 BIT 2 Detection of NDF Pointer Interrupt Enable R/W 0 DESCRIPTION Detection of B3 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B3 Byte Error" Interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a B3-byte error in the incoming STS-1 data-stream. 0 - Disables the "Detection of B3 Byte Error" interrupt. 1 - Enables the "Detection of B3 Byte Error" interrupt. 6 Detection of New Pointer Interrupt Enable R/W Detection of New Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of New Pointer" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-1 frame. Note: Pointer Adjustments with NDF will not generate this interrupt. BIT 1 Change of LOP-P Condition Interrupt Enable R/W 0 BIT 0 Change of AIS-P Condition Interrupt Enable R/W 0 0 - Disables the "Detection of New Pointer" Interrupt. 1 - Enables the "Detection of New Pointer" Interrupt. 5 Detection of Unknown Pointer Interrupt Enable R/W Detection of Unknown Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Unknown Pointer" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Adjustment" that does not fit into any of the following categories. * An Increment Pointer. * A Decrement Pointer * An NDF Pointer * AIS Pointer * New Pointer. 0 - Disables the "Detection of Unknown Pointer" Interrupt. 1 - Enables the "Detection of Unknown Pointer" Interrupt. 4 Detection of Pointer Decrement Interrupt Enable R/W Detection of Pointer Decrement Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "Detection of Pointer Decrement" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an interrupt anytime it detects a "Pointer-Decrement" event. 0 - Disables the "Detection of Pointer Decrement" Interrupt. 435 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Enables the "Detection of Pointer Decrement" Interrupt. 3 Detection of Pointer Increment Interrupt Enable R/W Detection of Pointer Increment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Pointer Increment" Interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Increment" event. 0 - Disables the "Detection of Pointer Increment" Interrupt. 1 - Enables the "Detection of Pointer Increment" Interrupt. 2 Detection of NDF Pointer Interrupt Enable R/W Detection of NDF Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of NDF Pointer" Interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 - Disables the "Detection of NDF Pointer" interrupt. 1 - Enables the "Detection of NDF Pointer" interrupt. 1 Change of LOP-P Condition Interrupt Enable R/W Change of LOP-P Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOP (Loss of Pointer)" Condition interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * * 20 0 Rev2...0...0 200 When the Receive STS-1 POH Processor block declares a "Loss of Pointer" condition. When the Receive STS-1 POH Processor block clears the "Loss of Pointer" condition. 0 - Disable the "Change of LOP" Interrupt. 1 - Enables the "Change of LOP" Interrupt. Note: The user can determine the current state of "LOP" by reading out the contents of Bit 1 (LOP) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" (Address Location= 0xN187). 0 Change of AIS-P Interrupt Enable R/W Change of AIS-P Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-P (Path AIS)" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * * When the Receive STS-1 POH Processor block declares an "AIS-P" condition. When the Receive STS-1 POH Processor block clears the "AIS-P" condition. 0 - Disables the "Change of AIS-P" Interrupt. 1 - Enables the "Change of AIS-P" Interrupt. Note: The user can determine the current state of "AIS-P" by reading out the contents of Bit 0 (AIS-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" (Address Location= 0xN187). Table 362: Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0xN193) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 436 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RDI-P_ACCEPT[2:0] R/O 0 R/O 0 R/O 0 R/W 0 RDI-P THRESHOLD[3:0] R/W 0 R/W 0 R/W 0 Unused R/O 0 BIT NUMBER 7 6-4 NAME Unused RDI-P_ACCEPT[2:0] TYPE R/O R/O Accepted RDI-P Value: DESCRIPTION These READ-ONLY bit-fields contain the value of the most recently "accepted" RDI-P (e.g., bits 5, 6 and 7 within the G1 byte) value. Note: A given RDI-P value will be "accepted" by the Receive STS-1 POH Processor block, if this RDI-P value has been consistently received in "RDI-P THRESHOLD[3:0]" number of STS-1 frames. 3-0 RDI-P THRESHOLD[3:0] R/W RDI-P Threshold: These READ/WRITE bit-fields permit the user to defined the "RDI-P Acceptance Threshold" for the Receive STS-1 POH Processor Block. The "RDI-P Acceptance Threshold" is the number of consecutive STS-1 frames, in which the Receive STS-1 POH Processor block must receive a given RDI-P value, before it "accepts" or "validates" it. The most recently "accepted" RDI-P value is written into the "RDI-P ACCEPT[2:0]" bit-fields, within this register. 437 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 363: Receive STS-1 Path - Received Path Label Value (Address Location= 0xN196) BIT 7 R/O 1 BIT 6 R/O 1 BIT 5 R/O 1 BIT 4 R/O 1 BIT 3 R/O 1 BIT 2 R/O 1 BIT 1 R/O 1 BIT 0 R/O 1 20 0 Rev2...0...0 200 Received_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Received C2 Byte Value[7:0] TYPE R/O DESCRIPTION Received "Filtered" C2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently "accepted" C2 byte, via the Receive STS-1 POH Processor block. The Receive STS-1 POH Processor block will "accept" a C2 byte value (and load it into these bit-fields) if it has received a consistent C2 byte, in five (5) consecutive STS-1 frames. Note: The Receive STS-1 POH Processor block uses this register, along the "Receive STS-1 Path - Expected Path Label Value" Register (Address Location = 0xN197), when declaring or clearing the UNEQ-P and PLM-P alarm conditions. Table 364: Receive STS-1 Path - Expected Path Label Value (Address Location= 0xN197) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 Expected_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Expected C2 Byte Value[7:0] TYPE R/W DESCRIPTION Expected C2 Byte Value: These READ/WRITE bit-fields permits the user to specify the C2 (Path Label Byte) value, that the Receive STS-1 POH Processor block should expect when declaring or clearing the UNEQ-P and PLM-P alarm conditions. If the contents of the "Received C2 Byte Value[7:0]" (see "Receive STS-1 Path - Received Path Label Value" register) matches the contents in these register, then the Receive STS1 POH will not declare any alarm conditions. 438 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 365: Receive STS-1 Path - B3 Error Count Register - Byte 3 (Address Location= 0xN198) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[31:24] BIT NUMBER 7-0 NAME B3_Error_Count[31:24] TYPE RUR B3 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 366: Receive STS-1 Path - B3 Error Count Register - Byte 2 (Address Location= 0xN199) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[23:16] BIT NUMBER 7-0 NAME B3_Error_Count[23:16] TYPE RUR DESCRIPTION B3 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. 439 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 367: Receive STS-1 Path - B3 Error Count Register - Byte 1 (Address Location= 0xN19A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[15:8] BIT NUMBER 7-0 NAME B3_Error_Count[15:8] TYPE RUR DESCRIPTION B3 Error Count - (Bits 15 through 8): This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 368: Receive STS-1 Path - B3 Error Count Register - Byte 0 (Address Location= 0xN19B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[7:0] BIT NUMBER 7-0 NAME B3_Error_Count[7:0] TYPE RUR B3 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. 440 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 369: Receive STS-1 Path - REI-P Error Count Register - Byte 3 (Address Location= 0xN19C) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[31:24] BIT NUMBER 7-0 NAME REI_P_Error_Count[31:24] TYPE RUR DESCRIPTION REI-P Error Count - MSB: This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. Table 370: Receive STS-1 Path - REI_P Error Count Register - Byte 2 (Address Location= 0xN19D) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[23:16] BIT NUMBER 7-0 NAME REI_P_Error_Count[23:16] TYPE RUR DESCRIPTION REI-P Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS1 POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. 441 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 371: Receive STS-1 Path - REI_P Error Count Register - Byte 1 (Address Location= 0xN19E) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[15:8] BIT NUMBER 7-0 NAME REI_P_Error_Count[15:8] TYPE RUR DESCRIPTION REI-P Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a Path -Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. Table 372: Receive STS-1 Path - REI_P Error Count Register - Byte 0 (Address Location= 0xN19F) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_P_Error_Count[7:0] TYPE RUR REI-P Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. 442 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 373: Receive STS-1 Path - Receive J1 Control Register (Address Location= 0xN1A3) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 Receive J1 Message Buffer Read Select R/W 0 BIT 3 Accept Threshold R/W 0 BIT 2 Message Type R/W 0 BIT 1 BIT 0 Message Length[1:0] R/W 0 R/W 0 BIT NUMBER 7-5 4 NAME Unused Received J1 Message Buffer Read Select TYPE R/O R/W J1 Buffer Read Selection: DESCRIPTION This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. a. b. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Receive STS-1 POH Processor block, the "Receive J1 Trace Buffer" is located at Address Location 0xN500 through 0xN53F. 3 Accept Threshold R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-1 POH Processor block must receive a given J1 Trace Message, before it is accepted, as described below. 0 - The Receive STS-1 POH Processor block accepts the J1 Message after it has received it the third time in succession. 1 - The Receive SONET POH Processor block accepts the J1 Message after it has received in the fifth time in succession. 2 Message Type R/O Message Alignment Type: This READ/WRITE bit-field permits a user to specify have the Receive STS-1 POH Processor block will locate the boundary of the J1 Trace Message, as indicated below. 0 - Message boundary is indicated by "Line Feed". 1 - Message boundary is indicated by the presence of a "1" in the MSB of a the first byte (within the J1 Trace Message). 1-0 Message Length[1:0] R/W J1 Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the J1 Trace Message, that the Receive STS-1 POH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J1 Trace Message Length is presented below. MSG LENGTH 00 Resulting J1 Trace Message Length 1 Byte 443 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 01 10/11 16 Bytes 64 Bytes 20 0 Rev2...0...0 200 444 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 374: Receive STS-1 Path - Pointer Value - Byte 1 (Address Location= 0xN1A6) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Current_Pointer Value MSB[9:8] R/O 0 R/O 0 BIT NUMBER 7-2 1-0 NAME Unused Current_Pointer_Value_MSB[7:0] TYPE R/O R/O DESCRIPTION Current Pointer Value - MSB: These READ-ONLY bit-fields, along with that from the "Receive STS-1 Path - Pointer Value - Byte 0" Register combine to reflect the current value of the pointer that the "Receive STS-1 POH Processor" block is using to locate the SPE within the incoming STS-1 data stream. Note: These register bits comprise the Upper Byte value of the Pointer Value. Table 375: Receive STS-1 Path - Pointer Value - Byte 0 (Address Location= 0xN1A7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Current_Pointer_Value_LSB[7:0] BIT NUMBER 7-0 NAME Current_Pointer_Value_LSB[7:0] TYPE R/O DESCRIPTION Current Pointer Value - LSB: These READ-ONLY bit-fields, along with that from the "Receive STS-1 Path - Pointer Value - Byte 1" Register combine to reflect the current value of the pointer that the "Receive STS-1 POH Processor" block is using to locate the SPE within the incoming STS-1 data stream. Note: These register bits comprise the Lower Byte value of the Pointer Value. 445 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 376: Receive STS-1 Path - AUTO AIS Control Register (Address Location= 0xN1BB) BIT 7 Unused BIT 6 Transmit AIS-P (Downstream) Upon C2 Byte Unstable R/W 0 BIT 5 Transmit AIS-P (Downstream) Upon UNEQ-P R/W 0 BIT 4 Transmit AIS-P (Downstream) Upon PLMP R/W 0 BIT 3 Transmit AIS-P (Downstream) Upon J1 Message Unstable R/W 0 BIT 2 Transmit AIS-P (Downstream) upon TIM-P R/W 0 BIT 1 Transmit AIS-P (Downstream) upon LOP-P BIT 0 Transmit AIS-P (Downstream) Enable 20 0 Rev2...0...0 200 R/O 0 R/W 0 R/W 0 BIT NUMBER 7 6 NAME Unused Transmit AIS-P (Downstream) upon C2 Byte Unstable TYPE R/O R/W DESCRIPTION Transmit Path AIS upon Detection of Unstable C2 Byte: This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it detects an Unstable C2 Byte condition in the "incoming" STS-1 data-stream. 0 - Does not configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable C2 Byte" condition. 1 - Configures the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable C2 Byte" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Downstream) upon UNEQ-P R/W Transmit Path AIS upon Detection of Path-Unequipped Defect (UNEQ-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares an UNEQ-P condition. 0 - Does not configure the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the UNEQ-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the UNEQ-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Downstream) upon PLM-P R/W Transmit Path AIS upon Detection of Path-Payload Label Mismatch Defect (PLM-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS 446 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares an PLM-P condition. 0 - Does not configure the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the PLM-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the PLM-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 Transmit AIS-P (Downstream) upon J1 Message Unstable R/W Transmit Path AIS upon Detection of Unstable 1 Message: This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it detects an Unstable J1 Message condition in the "incoming" STS-1 data-stream. 0 - Does not configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable J1 Message" condition. 1 - Configures the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable J1 Message" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 2 Transmit AIS-P (Downstream) upon TIM-P R/W Transmit Path AIS upon Detection of Path-Trace Identification Message Mismatch Defect (TIM-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares a TIMP condition. 0 - Does not configure the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the TIM-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the TIM-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Downstream) upon LOP-P R/W Transmit Path AIS upon Detection of Loss of Pointer (LOP-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares an LOP-P condition. 0 - Does not configure the Receive STS-1 POH Processor block to 447 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOP-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOP-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 Transmit AIS-P (Downstream) Enable R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-1 POH Processor block to automatically transmit the Path AIS indicator, via the downstream traffic (e.g., towards the Transmit SONET POH Processor blocks), upon detection of an UNEQ-P, PLM-P, LOP-P or LOS conditions. It also permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks) anytime it detects an AIS-P condition in the "incoming " STS-1 data-stream. 0 - Configures the Receive STS-1 POH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" conditions. 1 - Configures the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this register) to "1" in order to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 448 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 377: Receive STS-1 Path - SONET Receive Auto Alarm Register - Byte 0 (Address Location= 0xN1C3) BIT 7 Unused BIT 6 Transmit AIS-P (via Downstream STS-1s) upon LOP-P R/W 0 BIT 5 Transmit AIS-P (via Downstream STS-1s) upon PLM-P R/W 0 BIT 4 Transmit AIS-P (via Downstream STS-1s) upon LCD-P R/W 0 BIT 3 Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P R/W 0 BIT 2 Transmit AIS-P (via Downstream STS-1s) upon TIM-P R/W 0 BIT 1 Transmit AIS-P (via Downstream STS-1s) upon AIS-P R/W 0 BIT 0 Transmit DS3 AIS (via Downstream DS3) upon PDI-P R/W 0 R/O 0 BIT NUMBER 7 6 NAME Unused Transmit AIS-P (via Downstream STS-1s) upon LOP-P TYPE R/O R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon LOP-P This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the LOP-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the LOP-P defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the LOP-P defect. 5 Transmit AIS-P (via Downstream STS-1s) upon PLM-P R/W Transmit AIS-P (via Downstream STS-1s) upon PLM-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive STS-1 POH Processor block declares the PLM-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the PLM-P defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the PLM-P defect. 4 Transmit AIS-P (via Downstream STS-1s) upon LCD-P R/W Transmit AIS-P (via Downstream STS-1s) upon LCD-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive SONET POH 449 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Processor block declares the LCD-P defect. 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive SONET POH Processor block declares the LCD-P defect. 1 - Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive SONET POH Processor block declares the LCD-P defect. 3 Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P R/W Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, (within the outbound STS-3 signal) anytime the Receive STS-1 POH Processor block declares the UNEQP defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the UNEQP defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the UNEQP defect. 2 Transmit AIS-P (via Downstream STS-1s) upon TIM-P R/W Transmit AIS-P (via Downstream STS-1s) upon TIM-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the TIM-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the TIM-P defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the TIM-P defect. 1 Transmit AIS-P (via Downstream STS-1s) upon AIS-P R/W Transmit AIS-P (via Downstream STS-1s) upon AIS-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the AIS-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the AIS-P defect. 20 0 Rev2...0...0 200 450 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal A(within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the AIS-P defect. 0 Unused R/O 451 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 378: Receive STS-1 Path - Receive J1 Byte Capture Register (Address Location= 0xN1D3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 J1_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME J1_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION J1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the J1 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new J1 byte value. Table 379: Receive STS-1 Path - Receive B3 Byte Capture Register (Address Location= 0xN1D7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 B3_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME B3_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION B3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the B3 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new B3 byte value. 452 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 380: Receive STS-1 Path - Receive C2 Byte Capture Register (Address Location= 0xN1DB) BIT 7 R/O 0 BIT NUMBER 7-0 BIT 6 R/O 0 NAME C2_Byte_Captured_Value[7:0] BIT 5 R/O 0 BIT 4 R/O 0 TYPE R/O BIT 3 R/O 0 BIT 2 R/O 0 DESCRIPTION C2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the C2 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new C2 byte value. BIT 1 R/O 0 BIT 0 R/O 0 C2_Byte_Captured_Value[7:0] Table 381: Receive STS-1 Path - Receive G1 Byte Capture Register (Address Location= 0xN1DF) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 G1_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME G1_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION G1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the G1 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new G1 byte value. 453 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 382: Receive STS-1 Path - Receive F2 Byte Capture Register (Address Location=0xN1E3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 F2_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME F2_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION F2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the F2 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new F2 byte value. Table 383: Receive STS-1 Path - Receive H4 Byte Capture Register (Address Location= 0xN1E7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 H4_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME H4_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION H4 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the H4 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new H4 byte value. 454 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 384: Receive STS-1 Path - Receive Z3 Byte Capture Register (Address Location= 0xN1EB) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z3_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z3_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z3 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new Z3 byte value. Table 385: Receive STS-1 Path - Receive Z4 (K3) Byte Capture Register (Address Location= 0xN1EF) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z4(K3)_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z4(K3)_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z4 (K3) Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z4 (K3) byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new Z4 (K3) byte value. 455 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 386: Receive STS-1 Path - Receive Z5 Byte Capture Register (Address Location= 0xN1F3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z5_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z5_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z5 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z5 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new Z5 byte value. 1.10 TRANSMIT ATM CELL PROCESSOR BLOCK 456 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS The register map for the Transmit ATM Cell Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Transmit ATM Cell Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33 device, with the "Transmit ATM Cell Processor Blocks "highlighted" is presented below in Figure 9. Figure 11: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Transmit ATM Cell Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 457 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.10.1 TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 387: Transmit ATM Cell Processor Block Register Address Map TRANSMIT ATM CELL PROCESSOR/ PPP PROCESSOR BLOCK REGISTERS Note: N represents the "Channel Number" and ranges in value from 0x02 to 0x04 Transmit ATM Cell Processor Control Register - Byte 3 Transmit ATM Cell Processor Control Register - Byte 2 Transmit ATM Cell Processor Control Register - Byte 1 Transmit ATM Cell/PPP Processor Control Register - Byte 0 Transmit ATM Status Register Reserved Transmit ATM Cell/PPP Processor Interrupt Status Register Reserved Transmit ATM Cell/PPP Processor Interrupt Enable Register Reserved Transmit ATM Cell Insertion/Extraction Memory Control Register Transmit ATM Cell Insertion/Extraction Memory - Byte 3 Transmit ATM Cell Insertion/Extraction Memory - Byte 2 Transmit ATM Cell Insertion/Extraction Memory - Byte 1 Transmit ATM Cell Insertion/Extraction Memory - Byte 0 Transmit ATM Cell - Idle Cell Header Byte # 1 Register Transmit ATM Cell - Idle Cell Header Byte # 2 Register Transmit ATM Cell - Idle Cell Header Byte # 3 Register Transmit ATM Cell - Idle Cell Header Byte # 4 Register Reserved Transmit ATM Cell - Idle Cell Payload Byte Register Transmit ATM Cell - Test Cell Header Byte # 1 Register Transmit ATM Cell - Test Cell Header Byte # 2 Register Transmit ATM Cell - Test Cell Header Byte # 3 Register Transmit ATM Cell - Test Cell Header Byte # 4 Register Reserved Transmit ATM Cell - Cell Count Register - Byte 3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF00 0xNF01 0xNF02 0xNF03 0xNF04 0xNF05 - 0xNF0A 0xNF0B 0xNF0C - 0xNF0E 0xNF0F 0xNF10 - 0xNF12 0xNF13 0xNF14 0xNF15 0xNF16 0xNF17 0xNF18 0xNF19 0xNF1A 0xNF1B 0xNF1C - 0xNF1E 0xNF1F 0xNF20 0xNF21 0xNF22 0xNF23 0xNF24 - 0xNF27 0xNF28 458 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Transmit ATM Cell - Discard Cell Count Register - Byte 3 Transmit ATM Cell - Discard Cell Count Register - Byte 2 Transmit ATM Cell - Discard Cell Count Register - Byte 1 Transmit ATM Cell - Discard Cell Count Register - Byte 0 Transmit ATM Cell - HEC Byte Error Count Register - Byte 3 Transmit ATM Cell - HEC Byte Error Count Register - Byte 2 Transmit ATM Cell - HEC Byte Error Count Register - Byte 1 Transmit ATM Cell - HEC Byte Error Count Register - Byte 0 Transmit ATM Cell - Parity Error Count Register - Byte 3 Transmit ATM Cell - Parity Error Count Register - Byte 2 Transmit ATM Cell - Parity Error Count Register - Byte 1 Transmit ATM Cell - Parity Error Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 0 Control Register Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 0 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 0 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 1 Control Register Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF29 0xNF2A 0xNF2B 0xNF2C 0xNF2D 0xNF2E 0xNF2F 0xNF30 0xNF31 0xNF32 0xNF33 0xNF34 0xNF35 0xNF36 0xNF37 0xNF38 - 0xNF42 0xNF43 0xNF44 0xNF45 0xNF46 0xNF47 0xNF48 0xNF49 0xNF4A 0xNF4B 0xNF4C 0xNF4D 0xNF4E 0xNF4F 0xNF50 - 0xNF52 0xNF53 0xNF54 459 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0xNF55 0xNF56 0xNF57 0xNF58 0xNF59 0xNF5A 0xNF5B 0xNF5C 0xNF5D 0xNF5E 0xNF5F 0xNF60 - 0xNF62 0xNF63 0xNF64 0xNF65 0xNF66 0xNF67 0xNF68 0xNF69 0xNF6A 0xNF6B 0xNF6C 0xNF6D 0xNF6E 0xNF6F 0xNF70 - 0xNF72 0xNF73 0xNF74 0xNF75 0xNF76 0xNF77 0xNF78 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 1 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 1 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 2 Control Register Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 2 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 2 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved Transmit ATM Controller - Transmit ATM Filter # 3 Control Register Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 1 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Pattern - Header Byte 4 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 1 20 0 Rev2...0...0 200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 460 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 2 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 3 Transmit ATM Controller - Transmit ATM Filter # 3 Check - Header Byte 4 Transmit ATM Cell - Cell Count Register - Byte 3 Transmit ATM Cell - Cell Count Register - Byte 2 Transmit ATM Cell - Cell Count Register - Byte 1 Transmit ATM Cell - Cell Count Register - Byte 0 Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xNF79 0xNF7A 0xNF7B 0xNF7C 0xNF7D 0xNF7E 0xNF7F 0xNF80 - 0xN102 461 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.10.2 TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 388: Transmit ATM Cell Processor Block - Transmit ATM Control Register - Byte 3 (Address = 0xNF00) BIT 7 Unused BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 389: Transmit ATM Cell Processor Block - Transmit ATM Control Register - Byte 2 (Address = 0xNF01) BIT 7 BIT 6 BIT 5 BIT 4 Unused R/O 0 BIT NUMBER 7-1 0 R/O 0 NAME Unused Transmit ATM Cell Processor Enable R/O 0 TYPE R/O R/W Transmit ATM Cell Processor Block Enable: This READ/WRITE bit-field permits the user to either enable or disable the Transmit ATM Cell Processor block. If the user wishes to operate a given Channel in the ATM Mode, then he/she must enable the Transmit ATM Cell Processor Block. 0 - Disables the Transmit ATM Cell Processor Block 1 - Enables the Transmit ATM Cell Processor Block Note: The user must set this bit-field to "1" before he/she begins to write ATM cell data into the Transmit UTOPIA Interface block. R/O 0 R/O 0 R/O 0 R/O 0 DESCRIPTION BIT 3 BIT 2 BIT 1 BIT 0 Transmit ATM Cell Processor Enable R/W 0 462 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 390: Transmit ATM Cell Processor Block - Transmit ATM Control Register - Byte 1 (Address = 0xNF02) BIT 7 Test Cell Transmit Mode Enable R/W 0 BIT NUMBER 7 BIT 6 ONE SHOT MODE BIT 5 GFC Insertion Enable - Bit 3 R/W 0 NAME Test Cell Transmit Mode Enable TYPE R/W BIT 4 GFC Insertion Enable - Bit 2 R/W 0 BIT 3 GFC Insertion Enable - Bit 1 R/W 0 BIT 2 GFC Insertion Enable - Bit 0 R/W 0 DESCRIPTION Test Cell Transmit Mode Enable: This READ/WRITE bit-field permits the user to enable the Test Cell Transmitter (within the Transmit ATM Cell Processor Block). The user must implement this configuration option in order to perform diagnostic operations with Test Cells. 0 - Disables the Test Cell Transmitter. 1 - Enables the Test Cell Transmitter. Notes: 6 One Shot Mode R/W For normal operation, the user should set this bit-field to "1". BIT 1 COSET Polynomial Addition R/W 0 BIT 0 Regenerate HEC Byte Enable R/W 0 R/W 0 One Shot Mode: If the user has enabled the Test Cell Transmitter, then this READ/WRITE bit-field permits the user to either configure the Test Cell Transmitter into the "One-Shot" or in the "Continuous" Mode. If the user configures the Test Cell Transmitter into the "One-Shot" Mode, then (whenever the user implements a "0 to 1" transition within Bit 7 [Test Cell Transmit Mode Enable] of this register) then the Test Cell Transmitter will generate and transmit 1024 test cells. Afterwards, the Test Cell Transmitter will halt its transmission of Test Cells until the user implements another "0 to 1 transition" within Bit 7 (Test Cell Transmit Mode Enable) within this register. If the user configures the Test Cell Transmitter into the "Continuous" Mode, then the Test Cell Transmitter will continuously generate and transmit test cells for the duration that Bit 7(Test Cell Transmit Mode Enable) is set to "1". 0 - Configures the Test Cell Transmitter to operate in the "Continuous" Mode. 1 - Configures the "Test Cell Transmitter" to operate in the "One-Shot" Mode. 5 4 3 2 1 GFC Insertion Enable - Bit 3 GFC Insertion Enable - Bit 2 GFC Insertion Enable - Bit 1 GFC Insertion Enable - Bit 0 COSET Polynomial Addition R/W R/W R/W R/W R/W COSET Polynomial Addition: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to modulo-add the COSET Polynomial (e.g., x^6 + x^4 + x^2 + 1) to the HEC byte value, within each "outbound" 463 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ATM cell. 0 - Configures the Transmit ATM Cell Processor block to NOT modulo-add the COSET Polynomial to the HEC byte within each outbound ATM cell. 1 - Configures the Transmit ATM Cell Processor block to modulo-add the COSET Polynomial to the HEC byte within each outbound ATM cell. 0 Regenerate HEC Byte Enable R/W Regenerate HEC Byte Enable: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to automatically re-compute and insert a new HEC byte into each ATM cell (that it receives from the Transmit UTOPIA Interface block) that contains an uncorrectable HEC byte. 0 - Does not configure the Transmit ATM Cell Processor block to compute and insert a new HEC byte into ATM cells that contains an "uncorrectable" HEC Byte error. 1 - Configures the Transmit ATM Cell Processor block to compute and insert a new HEC byte into ATM cells that contains an "uncorrectable" HEC Byte error. 20 0 Rev2...0...0 200 464 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 391: Transmit ATM Cell Processor Block - Transmit ATM Control - Byte 0 (Address = 0xNF03) BIT 7 HEC Byte Invert BIT 6 HEC Byte Check Enable BIT 5 Transmit UTOPIA Parity Check Enable R/W 0 NAME HEC Byte Invert HEC Byte Check Enable TYPE R/W R/W HEC Byte Invert: HEC Byte Check Enable: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to perform HEC byte checking of all ATM cells that it receives via the Transmit UTOPIA Interface block. 0 - Configures the Transmit ATM Cell Processor block to NOT perform HEC byte checking on all ATM cells that it receives via the Transmit UTOPIA Interface block. 1 - Configures the Transmit ATM Cell Processor block to perform HEC byte checking on all ATM cells that it receives via the Transmit UTOPIA Interface block. 5 Transmit UTOPIA Parity Check Enable R/W Transmit UTOPIA Parity Check Enable: This READ/WRITE bit-field permits the user to either enable or disable "Transmit UTOPIA Interface" Parity checking. If the user enables "Transmit UTOPIA Interface" Parity Checking, then the Transmit ATM Cell Processor block will compute either the EVEN or ODD parity value (depending upon the setting of Bit 3 within this register) of each byte or 16-bit word that is input via the Transmit UTOPIA Data Bus input pins: (TxUData[15:0]). Afterwards, the Transmit ATM Cell Processor block will compare this "locally computed" parity value with that which the ATM Layer Processor has provided to the "TxUPrty" input pin. If the Transmit ATM Cell Processor detects any discrepancies between these two parity values (e.g., any parity errors) then it will take action based upon the user's settings for Bit 4 (Transmit UTOPIA Parity Error - Discard). 0 - Disables "Transmit UTOPIA Interface" Parity Checking. 1 - Enables "Transmit UTOPIA Interface" Parity Checking. 4 Transmit UTOPIA Parity Error - Discard R/W Transmit UTOPIA Parity Error - Discard Cell: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to either discard or retain (for further processing) any ATM cell that contains a "Transmit UTOPIA Interface" parity error. 0 - Configures the Transmit ATM Cell Processor block to retain (for further processing) all cells that contain "Transmit UTOPIA Interface" parity errors. 1 - Configures the Transmit ATM Cell Processor block to discard all cells that contain "Transmit UTOPIA Interface" parity errors. BIT 4 Transmit UTOPIA Parity Error - Discard R/W 0 BIT 3 Transmit UTOPIA - ODD Parity BIT 2 Reserved BIT 1 BIT 0 Scrambler Enable R/W 0 BIT NUMBER 7 6 R/W 0 R/W 0 R/O 0 DESCRIPTION R/O 0 R/W 0 465 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Notes: 3 Transmit UTOPIA - Odd Parity R/W 20 0 Rev2...0...0 200 This bit-field is only valid if "Transmit UTOPIA Interface" Parity Checking has been enabled. Transmit UTOPIA Parity Value - ODD Parity: This READ/WRITE bit-field permits the user to configure the Transmit ATM Cell Processor block to compute either the EVEN or ODD parity value for each byte or 16-bit word within each cell that it processes. Each of these parity values will ultimately be compared with the value that is input via the "TxUPrty" input pin (on the Transmit UTOPIA Interface block) coincident to when ATM cell data is being applied to the "TxUData[15:0]" input pins. 0 - Configures the Transmit ATM Cell Processor block to compute and verify the EVEN Parity value of each byte (or 16-bit word) of ATM cell data that it processes. 1 - Configures the Transmit ATM Cell Processor block to compute and verify the ODD Parity value of each byte (or 16-bit word) of ATM cell data that it processes. Notes: This bit-field is only value if "Transmit UTOPIA Interface" Parity Checking has been enabled. 2-1 0 Reserved Scrambler Enable R/O Cell Payload Scrambler Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Cell Payload Scrambler". If the user enables the "Cell Payload Scrambler" then the Transmit ATM Cell Processor will payload self-synchronous scrambling on all cell payloads bytes (within each outbound ATM cell) with the x^43+1 polynomial. 0 - Disables the Cell Payload Scrambler 1 - Enables the Cell Payload Scrambler 466 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 392: Transmit ATM Cell Processor Block - Transmit ATM Status Register (Address = 0xNF04) BIT 7 R/O 0 BIT NUMBER 7-1 0 BIT 6 R/O 0 NAME Unused One Shot DONE BIT 5 R/O 0 TYPE R/O R/O One Shot DONE: This READ-ONLY bit-field indicates whether or not the Test Cell Transmitter has completed its transmission of 1024 test cells, following the instant that the user has commanded the Test Cell to transmit this burst of 1024 cells. 0 - Indicates that the Test Cell Transmitter has NOT completed its transmission of 1024 test cells. 1 - Indicates that the Test Cell Transmitter has completed its transmission of 1024 test cells since the last "Transmit Test Cell - One Shot" command. Notes: 1. This bit-field is only valid if (1) the Test Cell Transmitter is active and (2) if the Test Cell Transmitter has been configured to operate in the "One-Shot" Mode. 2. Once this bit-field has been set to "1", it will remain at "1" until the user executes another "Transmit Test Cell - One Shot" command. BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 DESCRIPTION BIT 3 BIT 2 BIT 1 BIT 0 One Shot DONE R/O 0 467 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 393: Transmit ATM Cell Processor Block - Transmit ATM Interrupt Status Register (Address = 0xNF0B) BIT 7 Unused BIT 6 BIT 5 Transmit Cell Extraction Interrupt Status BIT 4 Transmit Cell Insertion Interrupt Status BIT 3 Transmit Cell Extraction Memory Overflow Interrupt Status RUR 0 BIT 2 Transmit Cell Insertion Memory Overflow Interrupt Status RUR 0 DESCRIPTION BIT 1 Detection of HEC Byte Error Interrupt Status BIT 0 Detection of Transmit UTOPIA Parity Error Interrupt Status RUR 0 R/O 0 BIT NUMBER 7-6 5 R/O 0 NAME Unused RUR 0 TYPE R/O RUR RUR 0 RUR 0 Transmit Cell Extraction Interrupt Status Transmit Cell Extraction Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit Cell Extraction" interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate the "Transmit Cell Extraction" Interrupt anytime it receives an incoming ATM cell (from the TxFIFO) and loads an ATM cell into the "Extraction Memory" Buffer. 0 - Indicates that the "Transmit Cell Extraction" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Transmit Cell Extraction" Interrupt has occurred since the last read of this register. 4 Transmit Cell Insertion Interrupt Status RUR Transmit Cell Insertion Interrupt This RESET-upon-READ bit-field indicates whether or not the "Transmit Cell Insertion" interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate the "Transmit Cell Insertion" Interrupt anytime a cell (residing in the Transmit Cell Insertion Buffer) is read out of the "Transmit Cell Insertion Buffer" and is loaded into the outbound ATM cell traffic. 0 - Indicates that the "Transmit Cell Insertion" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Transmit Cell Insertion" Interrupt has occurred since the last read of this register. 3 Transmit Cell Extraction Memory Overflow Interrupt Status RUR Transmit Cell Extraction Memory Overflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit Cell Extraction Memory Overflow" Interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime an overflow event has occurred in the "Transmit Cell Extraction Memory" Buffer. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Transmit Cell Extraction Memory Overflow" Interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Transmit Cell Extraction Memory Overflow" interrupt since the last 468 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS read of this register. 2 Transmit Cell Insertion Memory Overflow Interrupt Status RUR Transmit Cell Insertion Memory Overflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the Transmit Cell Insertion Memory Overflow" Interrupt has occurred since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime an overflow event has occurred in the "Transmit Cell Insertion Memory" Buffer. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Transmit Cell Insertion Memory Overflow" interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Transmit Cell Insertion Memory Overflow" interrupt since the last read of this register. 1 Detection of HEC Byte Error Interrupt RUR Detection of HEC Byte Error Interrupt: This RESET-upon-READ bit-field indicates whether or not the "Transmit ATM Cell Processor block" has declared the "Detection of HEC Byte Error" Interrupt since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime it has received an ATM cell (from the TxFIFO) that contains a HEC byte error. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Detection of HEC Byte Error" Interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Detection of HEC Byte Error" Interrupt since the last read of this register. 0 Detection of Transmit UTOPIA Parity Error Interrupt Detection of Transmit UTOPIA Parity Error Interrupt: This RESET-upon-READ bit-field indicates whether or not the "Transmit ATM Cell Processor" block has declared the "Detection of Transmit UTOPIA Parity Error" Interrupt since the last read of this register. The Transmit ATM Cell Processor block will generate this interrupt anytime it has received an ATM cell byte or 16-bit word (from the Transmit UTOPIA Interface block) that contains a parity error. 0 - Indicates that the Transmit ATM Cell Processor block has NOT declared the "Detection of Transmit UTOPIA Parity Error" Interrupt since the last read of this register. 1 - Indicates that the Transmit ATM Cell Processor block has declared the "Detection of Transmit UTOPIA Parity Error" Interrupt since the last read of this register. 469 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 394: Transmit ATM Cell Processor Block - Transmit ATM Interrupt Enable Register (Address = 0xNF0F) BIT 7 Unused BIT 6 BIT 5 Transmit Cell Extraction Interrupt Enable BIT 4 Transmit Cell Insertion Interrupt Enable BIT 3 Transmit Cell Extraction Memory Overflow Interrupt Enable R/W 0 BIT 2 Transmit Cell Insertion Memory Overflow Interrupt Enable R/W 0 DESCRIPTION BIT 1 Detection of HEC Byte Error Interrupt Enable BIT 0 Detection of Transmit UTOPIA Parity Error Interrupt Enable R/W 0 R/O 0 BIT NUMBER 7-6 5 R/O 0 NAME Unused Transmit Cell Extraction Interrupt Enable R/W 0 TYPE R/W 0 R/W 0 R/W Transmit Cell Extraction Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Extraction" Interrupt. If the user enables this feature, then the Transmit ATM Cell Processor block will generate the "Transmit Cell Extraction" Interrupt anytime it receives an incoming ATM cell (from the TxFIFO) and loads this ATM cell into the "Transmit Extraction Memory" Buffer. 0 - Disables the "Transmit Cell Extraction" Interrupt. 1 - Enables the "Transmit Cell Extraction" Interrupt 4 Transmit Cell Insertion Interrupt Enable R/W Transmit Cell Insertion Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Insertion" Interrupt. If the user enables this feature, then the Transmit ATM Cell Processor block will generate the "Transmit Cell Insertion" Interrupt anytime a cell (residing in the "Transmit Cell Insertion" Buffer) is read out of the "Transmit Cell Insertion" Buffer and is loaded into the "outbound" ATM cell traffic. 0 - Disables the Transmit Cell Insertion Interrupt. 1 - Enables the Transmit Cell Insertion Interrupt. 3 Transmit Cell Extraction Memory Overflow Interrupt Enable R/W Transmit Cell Extraction Memory Overflow Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Extraction Memory Overflow" Interrupt. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt any time an overflow event has occurred in the "Transmit Cell Extraction Memory" buffer. 0 - Disables the Transmit Cell Extraction Memory Overflow Interrupt. 1 - Enables the Transmit Cell Extraction Memory Overflow Interrupt. 2 Transmit Cell Insertion Memory Overflow Interrupt Enable R/W Transmit Cell Insertion Memory Overflow Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Cell Insertion Memory Overflow" Interrupt. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt any time an overflow event has occurred in the "Transmit Cell Insertion Memory" buffer. 470 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Disables the Transmit Cell Insertion Memory Overflow Interrupt. 1 - Enables the Transmit Cell Insertion Memory Overflow Interrupt. 1 Detection of HEC Byte Error Interrupt Enable R/W Detection of HEC Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of HEC Byte Error Interrupt" within the Transmit ATM Cell Processor Block. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt each time it receives an ATM cell (from the TxFIFO) that contains a HEC Byte error. 0 - Disables the "Detection of HEC Byte Error" Interrupt. 1 - Enables the "Detection of HEC Byte Error" Interrupt 0 Detection of Transmit UTOPIA Parity Error Interrupt Enable Detection of Transmit UTOPIA Parity Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Transmit UTOPIA Parity Error" Interrupt within the Transmit ATM Cell Processor block. If the user enables this interrupt, then the Transmit ATM Cell Processor block will generate an interrupt each time it receives an ATM cell byte or 16-bit word (from the TxFIFO) that contains a parity error. 0 - Disables the "Detection of Transmit UTOPIA Parity Error" Interrupt. 1 - Enables the "Detection of Transmit UTOPIA Parity Error" Interrupt. 471 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 395: Transmit ATM Cell Processor Block - Transmit ATM Cell Insertion/Extraction Memory Control Register (0xNF13) BIT 7 BIT 6 Unused BIT 5 BIT 4 Transmit Cell Extraction Memory RESET* R/O 0 NAME Unused Transmit Cell Extraction Memory RESET* R/W Transmit Cell Extraction Memory RESET*: This READ/WRITE bit-field permits the user to perform a REST operation to the Transmit Cell Extraction Memory. If the user writes a "1-to-0 transition" into this bit-field, then the following events will occur. * * BIT 3 Transmit Cell Extraction Memory CLAV R/O 0 BIT 2 Transmit Cell Insertion Memory RESET* R/W 1 DESCRIPTION BIT 1 Transmit Cell Insertion Memory ROOM R/O 0 BIT 0 Transmit Cell Insertion Memory WSOC W/O 0 R/O 0 BIT NUMBER 7-5 4 R/O 0 R/W 1 TYPE All of the contents of the Transmit Cell Extraction Memory will be flushed. All READ and WRITE pointers will be reset to their default positions. Following this RESET event, the user must write the value "1" into this bit-field in order to enable normal operation within the Transmit Cell Extraction Memory. Notes: 3 Transmit Cell Extraction Memory CLAV R/O Transmit Cell Extraction Memory - Cell Available Indicator: This READ-ONLY bit-field indicates whether or not there is at least ATM cell of data (residing within the Transmit Cell Extraction Memory) that needs to be read out via the Microprocessor Interface. 0 - Indicates that the Transmit Cell Extraction Memory is empty and contains no ATM cell data. 1 - Indicates that the Transmit Cell Extraction Memory contains at least one ATM cell of data that needs to be read out. Notes: The user should validate each ATM cell that is being read out from the Transmit Cell Extraction memory by checking the state of this bit-field prior to reading out the contents of ATM cell data residing within the Transmit Cell Extraction Memory 2 Transmit Cell Insertion Memory RESET* R/W Transmit Cell Insertion Memory RESET*: This READ/WRITE bit-field permits the user to perform a RESET operation to the Transmit Cell Insertion Memory. If the user writes a "1-to-0 transition" into this bit-field, then the following events will occur. * * All of the contents of the Transmit Cell Insertion Memory will be flushed. All READ and WRITE pointers will be reset to their default positions. Following this RESET event, the user must write the value "1" into this bit-field in order to enable normal Notes: 472 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS operation of the Transmit Cell Insertion Memory. 1 Transmit Cell Insertion Memory ROOM R/O Transmit Cell Insertion Memory - ROOM Indicator: This READ-ONLY bit-field indicates whether or not there is room (e.g., empty space) available for the contents of another ATM cell to be written into the Transmit Cell Insertion Memory. 0 - Indicates that the Transmit Cell Insertion Memory does not contain enough empty space to receive another ATM cell via the Microprocessor Interface. 1 - Indicates that the Transmit Cell Insertion Memory does contain enough empty space to receive another ATM cell via the Microprocessor Interface. Notes: The user should verify that the Transmit Cell Insertion Memory has sufficient empty space to accept another ATM cell of data (via the Microprocessor Interface) by polling the state of this bit-field prior to writing each cell into the Transmit Cell Insertion Memory. 0 Transmit Cell Insertion Memory WSOC W/O Transmit Cell Insertion Memory - Write SOC (Start of Cell): Whenever the user is writing the contents of an ATM cell into the Transmit Cell Insertion Memory, then he/she is suppose to identify/designate the very first byte of this ATM cell by setting this bit-field to "1". Whenever the user does this, then the Transmit Cell Insertion Memory will "know" that the next octet that is written into the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data Register - Byte 3 (Address = 0xNF14) is designated as the first byte of the ATM cell currently being written into the Transmit Cell Insertion Memory. This bit-field must be set to "0" during all other WRITE operations to the Transmit ATM Cell Processor - Transmit Cell Insertion/Extraction Memory Data Register 473 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 396: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 3 (Address = 0xNF14) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[31:24] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[31:24]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 2 through 0" support the following functions. * BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[31:24] They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. * Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from this particular address location. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 2 register. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 1 register. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 0 register. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. 474 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 397: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 2 (Address = 0xNF15) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[23:16] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[23:16]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 3, 1 and 0" support the following functions. They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4-byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 3" register. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to this particular address location. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 1 register. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 0 register. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[23:16] 475 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 398: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 1 (Address = 0xNF16) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[15:8] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[15:8]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 3, 2 and 0" support the following functions. * BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[15:8] They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. * Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4-byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 3 register. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 2 register. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to this particular register location. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 0 register. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. 476 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 399: Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Byte 0 (Address = 0xNF17) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Cell Insertion/Extraction Memory Data[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Cell Insertion/Extraction Memory Data[7:0]: These READ/WRITE bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory Data - Bytes 3, through 1" support the following functions. * BIT 1 R/W 0 BIT 0 R/W 0 Transmit Cell Insertion/Extraction Memory Data[7:0] They function as the address location for the user to write the contents of an "outbound" ATM cell into the Transmit Cell Insertion Memory, via the Microprocessor Interface. They function as the address location, for which the user to read out the contents of an "inbound" ATM cell from the Receive Cell Extraction Memory, via the Microprocessor Interface. * Notes: 1. If the user performs a WRITE operation to this (and the other three address locations), then he/she is writing ATM cell data into the Transmit Cell Insertion Memory. 2. If the user performs a READ operation to this (and the other three address locations), then he/she is reading ATM cell data from the Transmit Cell Extraction Memory. 3. READ and WRITE operations must be performed in a "32-bit" (4byte "word") manner. Hence, whenever the user performs a READ/WRITE operation to these address locations, he/she must start by writing in or reading out the first byte (of this "4-byte" word) of a given ATM cell, into/from the Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 3 register. Next, the user must perform the READ/WRITE operation (with the second of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 2 register. Afterwards, the user must perform a READ/WRITE operation (with the third of this "4-byte" word) to the "Transmit ATM Cell Processor Block - Transmit Cell Insertion/Extraction Memory - Byte 1" register. Finally, the user must perform a READ/WRITE operation (with the fourth of this "4-byte" word) to this particular register location. When reading out (writing in) the next four bytes of a given ATM Cell, the user must repeat this process with a READ or WRITE operation, from/to this register location, and so on. 4. Whenever the user is writing cell data into the Transmit Cell Insertion Memory, the size of the Cell is always 56 bytes. 5. Whenever the user is reading cell data from the Transmit Cell Extraction Memory, the size of the Cell is always 56 bytes. 477 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 400: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 1 (Address = 0xNF18) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 1 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 1[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 2 through Byte 4" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 1 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 1 [7:0] Table 401: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 2 (Address = 0xNF19) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 2 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 2[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Bytes 1, 3 and 4" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 2 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 2 [7:0] 478 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 402: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 3 (Address = 0xNF1A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 3 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 3[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Bytes 1, 2 and 4" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 3 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 3 [7:0] Table 403: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 4 (Address = 0xNF1B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Header Byte - 4 [7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Header Byte - 4[7:0]: These READ/WRITE register bits, along with that in "Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Header Byte 1 through Byte 3" registers permit the user to define the header byte pattern of all Idle Cells that are generated by the Transmit ATM Cell Processor block. This register permits the user to define/specify the value of Header Byte # 4 within each Idle Cell that is generated and transmitted by the Transmit ATM Cell Processor block. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Header Byte 4 [7:0] 479 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 404: Transmit ATM Cell Processor Block - Transmit ATM Idle Cell Payload Register (Address = 0xNF1F) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Idle Cell Payload Byte[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit Idle Cell Payload Byte [7:0]: These READ/WRITE register bits permit the user to define the value of the payload bytes of all Idle Cells that are generated and transmitted by the Transmit ATM Cell Processor block. Notes: Each of the 48 payload bytes (within each outbound Idle Cell) will be assigned the value that is written into this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Idle Cell Payload Byte[7:0] Table 405: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 1 (Address = 0xNF20) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 1[7:0] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 1: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 2 through 4" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 1. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 1 [7:0] 480 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 406: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 2 (Address = 0xNF21) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 2[7:0] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 2: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 1, 3 and 4" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 2. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 2 [7:0] Table 407: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 3 (Address = 0xNF22) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 3[7:0] BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 3: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 1, 2 and 4" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 3. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 3 [7:0] 481 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 408: Transmit ATM Cell Processor Block - Transmit Test Cell Header Byte - Byte 4 (Address = 0xNF23) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit Test Cell Header Byte 4[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Receive Test Cell Header Byte 4: These READ/WRITE register bits along with that in the "Transmit ATM Cell Processor Block - Transmit Cell Header Byte - Bytes 1 through 3" permit the user to define the headers of test cells that the Transmit Test Cell Generator will generate. This particular register byte permits the user to define the contents of Header Byte # 4. Notes: These register bits are only active if the Transmit Test Cell Generator has been enabled. BIT 1 R/W 0 BIT 0 R/W 0 Transmit Test Cell Header Byte 4 [7:0] Table 409: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF28) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 3[31:24]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 2 through 0" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[31:24] 482 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 410: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF29) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 2[23:16]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 3, 1 and 0" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[23:16] Table 411: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF2A) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 1[15:8]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 3, 2 and 0" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[15:8] 483 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 412: Transmit ATM Cell Processor Block - Transmit ATM Cell Counter (Address = 0xNF2B) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit ATM Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit ATM Cell Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Count - Bytes 3 through 1" registers; contain a 32-bit value for the number of User/Valid cells that have been transmitted by the Transmit ATM Cell Processor block. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: 1. The contents within these registers include all of the following: All ATM cells that have been read out from the TxFIFO, or the Transmit Cell Insertion Buffer. 2. The contents of these registers do not include the number of Idle Cells that have been generated by the Transmit ATM Cell Processor block. 3. If the number of Cells reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit ATM Cell Count[7:0] 484 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 413: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 3 (Address = 0xNF2C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 3[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 2 through 0" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. This particular register contains the MSB (Most Significant Byte) value of this 32-bit expression. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[31:24] Table 414: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 2 (Address = 0xNF2D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 2[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 3, 1 and 0" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[23:16] 485 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 415: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 1 (Address = 0xNF2E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 1[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 3, 2 and 0" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[15:8] Table 416: Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Byte 0 (Address = 0xNF2F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - Discard Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - Discard Cell Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM Cell Discard Cell Count - Bytes 3 through 1" registers; contain a 32-bit value for the number of ATM cells that have been discarded by the Transmit ATM Cell Processor block. This particular register contains the LSB (Least Significant Byte) value of this 32-bit expression. Notes: 1. The contents within these register includes all ATM cells that contain either a HEC Byte error or a "Transmit UTOPIA Parity" error. 2. If the number of Cells reaches the value "0xFFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - Discard Cell Count[7:0] 486 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 417: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 3 (Address = 0xNF30) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 3[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 2 through 0" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the MSB (Most Significant Byte) for this 32-bit expression. Notes: 1. This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[31:24] Table 418: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 2 (Address = 0xNF31) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 2[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 3, 1 and 0" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). Notes: 1.This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[23:16] 487 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 419: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 1 (Address = 0xNF32) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 1[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 3, 2 and 0" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). Notes: 1. This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[15:8] Table 420: Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Byte 0 (Address = 0xNF33) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit - HEC Byte Error Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit - HEC Byte Error Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit ATM HEC Byte Error Count Register - Bytes 3 through 1" register; contain a 32-bit value for the number of ATM cells that contain HEC byte errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the LSB (Least Significant Byte) for this 32-bit expression. Notes: 1. This register is valid if the Transmit ATM Cell Processor block has been configured to compute and verify the HEC byte of each ATM cell that it receives from the TxFIFO or the "Transmit Cell Insertion Buffer". 2. If the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit - HEC Byte Error Count[7:0] 488 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 421: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 3 (Address = 0xNF34) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 3[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 2 through 0" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the MSB (Most Significant Byte) for this 32-bit expression. Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[31:24] Table 422: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 2 (Address = 0xNF35) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 2[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 3, 1 and 0" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[23:16] 489 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 423: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 1 (Address = 0xNF36) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 1[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 3, 2 and 0" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[15:8] Table 424: Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Byte 0 (Address = 0xNF37) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit UTOPIA - Parity Error Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit UTOPIA Parity Error Count - Byte 0[7:0]: This RESET-upon-READ register, along with the "Transmit ATM Cell Processor Block - Transmit UTOPIA Parity Error Count Register - Bytes 3 through 1" registers; contains a 32-bit value for the number of ATM cells that contain "Transmit UTOPIA" Parity (byte or word) errors (as detected by the Transmit ATM Cell Processor block). This particular register functions as the LSB (Least Significant Byte) for this 32-bit expression. Notes: if the number of cells reaches the value "0xFFFFFFFF", then these registers will saturate to and remain at this value (e.g., it will NOT overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit UTOPIA - Parity Error Count[7:0] 490 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 425: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 0 (Address = 0xNF43) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 0 Enable R/O 0 NAME Unused Transmit User Cell Filter # 0 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 0 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 0. If the user enables Transmit User Cell Filter # 0, then Transmit User Cell Filter # 0 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 0, then Transmit User Cell Filter # 0 then all cells that are applied to the input of Transmit User Cell Filter # 0 will pass through to the output of Transmit User Cell Filter # 0. 0 - Disables Transmit User Cell Filter # 0. 1 - Enables Transmit User Cell Filter # 0. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 0: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 0 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 0, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 0 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 0 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 0 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 0 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 0" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 0: This READ/WRITE bit-field permits the user to either 491 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 0 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 0, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 0 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 0 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 0 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 0" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 0: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 0 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 0 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 0 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 0" has been enabled. 492 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 426: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1 (Address = 0xNF44) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 1 [7:0] 493 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 427: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2 (Address = 0xNF45) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 2 [7:0] 494 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 428: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3 (Address = 0xNF46) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 3 [7:0] 495 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 429: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4 (Address = 0xNF47) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Pattern Register - Byte 4 [7:0] 496 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 430: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 1 (Address = 0xNF48) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 1 [7:0] 497 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 431: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 2 (Address = 0xNF49) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 2 [7:0] 498 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 432: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 3 (Address = 0xNF4A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 3 [7:0] 499 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 433: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Register - Byte 4 (Address = 0xNF4B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 0 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 0 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 0) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 0 - Check Register - Byte 4 [7:0] 500 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 434: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 3 (Address = 0xNF4C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[31:24] 501 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 435: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 2 (Address = 0xNF4D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[23:16] 502 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 436: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 1 (Address = 0xNF4E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime Transmit User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[15:8] 503 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 437: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Byte 0 (Address = 0xNF4F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 0 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 0 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 0 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 0 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 0" Register (Address = 0xNF43), these register bits will be incremented anytime Transmit User Cell Filter # 0 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 0 - Filtered Cell Count[7:0] 504 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 438: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 1 (Address = 0xNF53) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 1 Enable R/O 0 NAME Unused Transmit User Cell Filter # 1 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 1 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 1. If the user enables Transmit User Cell Filter # 1, then Transmit User Cell Filter # 1 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 1, then Transmit User Cell Filter # 1 then all cells that are applied to the input of Transmit User Cell Filter # 1 will pass through to the output of Transmit User Cell Filter # 1. 0 - Disables Transmit User Cell Filter # 1. 1 - Enables Transmit User Cell Filter # 1. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 1: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 1 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 1, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 1 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 1 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 1 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 1 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 1" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 1: This READ/WRITE bit-field permits the user to either 505 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 1 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 1, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 1 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 1 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 1 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 1" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 1: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 1 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 1 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 1 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 1" has been enabled. 506 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 439: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1 (Address = 0xNF54) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 1 [7:0] 507 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 440: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2 (Address = 0xNF55) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 2 [7:0] 508 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 441: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3 (Address = 0xNF56) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 3 [7:0] 509 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 442: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4 (Address = 0xNF57) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Pattern Register - Byte 4 [7:0] 510 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 443: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 1 (Address = 0xNF58) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 1 [7:0] 511 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 444: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 2 (Address = 0xNF59) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 2 [7:0] 512 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 445: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 3 (Address = 0xNF5A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 3 [7:0] 513 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 446: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Register - Byte 4 (Address = 0xNF5B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 1 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 1 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 1) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 1 - Check Register - Byte 4 [7:0] 514 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 447: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 3 (Address = 0xNF5C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[31:24] 515 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 448: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 2 (Address = 0xNF5D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[23:16] 516 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 449: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 1 (Address = 0xNF5E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime Transmit User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[15:8] 517 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 450: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Byte 0 (Address = 0xNF5F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 1 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 1 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 1 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 1 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 1" Register (Address = 0xNF53), these register bits will be incremented anytime Transmit User Cell Filter # 1 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 1 - Filtered Cell Count[7:0] 518 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 451: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 2 (Address = 0xNF63) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 2 Enable R/O 0 NAME Unused Transmit User Cell Filter # 2 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 2 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 2. If the user enables Transmit User Cell Filter # 2, then Transmit User Cell Filter # 2 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 2, then Transmit User Cell Filter # 2 then all cells that are applied to the input of Transmit User Cell Filter # 2 will pass through to the output of Transmit User Cell Filter # 2. 0 - Disables Transmit User Cell Filter # 2. 1 - Enables Transmit User Cell Filter # 2. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 2: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 2 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 2, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 2 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 2 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 2 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 2 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 2" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 2: This READ/WRITE bit-field permits the user to either 519 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 2 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 2, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 2 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 2 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 2 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 2" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 2: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 2 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 2 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 2 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 2" has been enabled. 520 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 452: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1 (Address = 0xNF64) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 1 [7:0] 521 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 453: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2 (Address = 0XNF65) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 2 [7:0] 522 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 454: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3 (Address = 0xNF66) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 3 [7:0] 523 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 455: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4 (Address = 0xNF67) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Pattern Register - Byte 4 [7:0] 524 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 456: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 1 (Address = 0xNF68) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 1 [7:0] 525 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 457: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 2 (Address = 0xNF69) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 2 [7:0] 526 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 458: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 3 (Address = 0xNF6A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 3 [7:0] 527 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 459: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Register - Byte 4 (Address = 0xNF6B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 2 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 2 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 2) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 2 - Check Register - Byte 4 [7:0] 528 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 460: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 3 (Address = 0xNF6C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[31:24] 529 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 461: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 2 (Address = 0xNF6D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[23:16] 530 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 462: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 1 (Address = 0xNF6E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[15:8] 531 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 463: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Byte 0 (Address = 0xNF6F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 2 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 2 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 2 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 2 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 2" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 2 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 2 - Filtered Cell Count[7:0] 532 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 464: Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Filter 3 (Address = 0xNF63) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Transmit User Cell Filter # 3 Enable R/O 0 NAME Unused Transmit User Cell Filter # 3 Enable R/O 0 TYPE R/O R/W Transmit User Cell Filter # 3 - Enable: This READ/WRITE bit-field permits the user to either enable or disable Transmit User Cell Filter # 3. If the user enables Transmit User Cell Filter # 3, then Transmit User Cell Filter # 3 will function per the configuration settings in Bits 2 through 0, within this register. If the user disables Transmit User Cell Filter # 3, then Transmit User Cell Filter # 3 then all cells that are applied to the input of Transmit User Cell Filter # 3 will pass through to the output of Transmit User Cell Filter # 3. 0 - Disables Transmit User Cell Filter # 3. 1 - Enables Transmit User Cell Filter # 3. 2 Copy Cell Enable R/W Copy Cell Enable - Transmit User Cell Filter # 3: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 3 (within the Transmit ATM Cell Processor Block) to copy all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 3, or to NOT copy any of these cells. If the user configures Transmit User Cell Filter # 3 to copy all cells complying with a certain "header-byte" pattern, then a copy (or replicate) of this "compliant" ATM cell will be routed to the Transmit Cell Extraction Buffer. If the user configures Transmit User Cell Filter # 3 to NOT copy all cells complying with a certain "header-byte" pattern, then NO copies (or replicates) of these "compliant" ATM cells will be made nor will any be routed to the Transmit Cell Extraction Buffer. 0 - Configures Transmit User Cell Filter # 3 to NOT copy any cells that have header byte patterns which are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 3 to copy any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria, and to route these copies (of cells) to the Transmit Cell Extraction Buffer. Notes: 1 Discard Cell Enable R/W This bit-field is only active if "Transmit User Cell Filter # 3" has been enabled. R/W 0 BIT 2 Copy Cell Enable R/W 0 DESCRIPTION BIT 1 Discard Cell Enable R/W 0 BIT 0 Filter if Pattern Match R/W 0 R/O 0 BIT NUMBER 7-4 3 R/O 0 Discard Cell Enable - Transmit User Cell Filter # 3: This READ/WRITE bit-field permits the user to either 533 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 configure Transmit User Cell Filter # 3 (within the Transmit ATM Cell Processor Block) to discard all cells that have header byte patterns that comply with the "user-defined" criteria, per Transmit User Cell Filter # 3, or NOT discard any of these cells. If the user configures Transmit User Cell Filter # 3 to NOT discarded any cells that is compliant with a certain "headerbyte" pattern, then the cell will be retained for further processing. 0 - Configures Transmit User Cell Filter # 3 to NOT discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. 1 - Configures Transmit User Cell Filter # 3 to discard any cells that have header byte patterns that are compliant with the "user-defined" filtering criteria. Notes: 0 Filter if Pattern Match R/W This bit-field is only active if "Transmit User Cell Filter # 3" has been enabled. Filter if Pattern Match - Transmit User Cell Filter # 3: This READ/WRITE bit-field permits the user to either configure Transmit User Cell Filter # 3 to filter (based upon the configuration settings for Bits 1 and 2, in this register) ATM cells with header bytes that match the "user-defined" header byte patterns, or to filter ATM cells with header bytes that do NOT match the "user-defined" header byte patterns. 0 - Configures Transmit User Cell Filter # 3 to filter user cells that do NOT match the header byte patterns (as defined in the " " registers). 1 - Configures Transmit User Cell Filter # 3 to filter user cells that do match the header byte patterns (as defined in the " " registers). Notes: This bit-field is only active if "Transmit User Cell Filter # 3" has been enabled. 534 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 465: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1 (Address = 0xNF64) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" of the incoming User Cell. The user will write the header byte pattern (for Octet 1) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 1" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 1 [7:0] 535 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 466: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2 (Address = 0xNF65) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" of the incoming User Cell. The user will write the header byte pattern (for Octet 2) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 2" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 2 [7:0] 536 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 467: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3 (Address = 0xNF66) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" of the incoming User Cell. The user will write the header byte pattern (for Octet 3) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 3" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 3 [7:0] 537 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 468: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4 (Address = 0xNF67) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" of the incoming User Cell. The user will write the header byte pattern (for Octet 4) that he/she wishes to use as part of the "User Cell Filtering" criteria, into this register. The user will also write in a value into the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Header Byte 4" that indicates which bits within the first octet of the incoming cells are to be compared with the contents of this register. BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Pattern Register - Byte 4 [7:0] 538 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 469: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 1 (Address = 0xNF68) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 1 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 1: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1" permits the user to define the User Cell Filtering criteria for "Octet # 1" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 1" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 1" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 1" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 1" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 1"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 1 [7:0] 539 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 470: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 2 (Address = 0xNF69) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 2 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 2: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2" permits the user to define the User Cell Filtering criteria for "Octet # 2" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 2" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 2" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 2" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 2" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 2"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 2 [7:0] 540 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 471: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 3 (Address = 0xNF6A) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 3 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 3: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3" permits the user to define the User Cell Filtering criteria for "Octet # 3" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 3" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 3" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 3" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 3" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 3"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 3 [7:0] 541 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 472: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Register - Byte 4 (Address = 0xNF6B) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME Transmit User Cell Filter # 3 - Check Register - Header Byte 4 BIT 5 R/W 0 BIT 4 R/W 0 TYPE R/W BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit User Cell Filter # 3 - Check Register - Header Byte 4: The User Cell filtering criteria (for Transmit User Cell Filter # 3) is defined based upon the contents of 9 read/write registers. These registers are the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Registers", the four "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Check Registers" and the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 Control Register. This READ/WRITE register, along with the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4" permits the user to define the User Cell Filtering criteria for "Octet # 4" within the incoming User Cell. More specifically, these READ/WRITE register bits permit the user to specify which bit(s) in "Octet 4" of the incoming user cell (in the Transmit ATM Cell Processor Block) are to be checked against the corresponding bit-fields within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4" by the User Cell Filter, when determine whether to "filter" a given User Cell. Writing a "1" to a particular bit-field in this register, forces the Transmit User Cell Filter to check and compare the corresponding bit in "Octet # 4" (of the incoming user cell) with the corresponding bit in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4". Writing a "0" to a particular bit-field in this register causes the Transmit User Cell Filter to treat the corresponding bit within "Octet # 4" (in the incoming user cell) as a "don't care" (e.g., to forgo the comparison between the corresponding bit in "Octet # 4" of the incoming user cell with the corresponding bit-field in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Pattern Register - Header Byte 4"). BIT 1 R/W 0 BIT 0 R/W 0 Transmit User Cell Filter # 3 - Check Register - Byte 4 [7:0] 542 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 473: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 3 (Address = 0xNF6C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[31:24]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 2" through "0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the MSB (Most Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[31:24] 543 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 474: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 2 (Address = 0xNF6D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[23:16]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 3, 1 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[23:16] 544 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 475: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 1 (Address = 0xNF6E) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[15:8] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[15:8]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 3, 2 and 0" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[15:8] 545 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 476: Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Byte 0 (Address = 0xNF6F) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME Transmit User Cell Filter # 3 - Filtered Cell Count[7:0] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION Transmit User Cell Filter # 3 - Filtered Cell Count[7:0]: These RESET-upon-READ bit-fields, along with that in the "Transmit ATM Cell Processor Block - Transmit User Cell Filter # 3 - Filtered Cell Count - Bytes 3" through "1" register contain a 32-bit expression for the number of User Cells that have been filtered by Transmit User Cell Filter # 3 since the last read of this register. Depending upon the configuration settings within the "Transmit ATM Cell Processor Block - Transmit User Cell Filter Control - Transmit User Cell Filter # 3" Register (Address = 0xNF63), these register bits will be incremented anytime Transmit User Cell Filter # 3 performs any of the following functions. * Discards an incoming "User Cell". * Copies (or Replicates) an incoming "User Cell" and routes the "copy" to the Transmit Cell Extraction Buffer. * Both the above actions. This particular register contains the LSB (Least Significant Byte) value for this 32-bit expression. Notes: If the number of "filtered cells" reaches the value "0xFFFFFFFF" then these registers will saturate to and remain at this value (e.g., it will not overflow to "0x00000000"). BIT 1 RUR 0 BIT 0 RUR 0 Transmit User Cell Filter # 3 - Filtered Cell Count[7:0] 546 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.11 RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK The register map for the Receive STS-1 TOH and POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Receive STS-1 TOH and POH Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33 device, with the "Receive STS-1 TOH and POH Processor Blocks "highlighted" is presented below in Figure 10 Figure 12: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Receive STS1 TOH and POH Processor Blocks "High-lighted". Receive STS-1 Receive STS-1 Telecom Bus Telecom Bus Interface Interface Block Block Receive Receive STS-1 TOH STS-1 TOH Processor Processor Block Block Transmit Transmit STS-1 TOH STS-1 TOH Processor Processor Block Block Transmit STS-1 Transmit STS-1 Telecom Bus Telecom Bus Interface Interface Block Block DS3/E3 DS3/E3 Framer Framer Block Block Receive Receive STS-1 POH STS-1 POH Processor Processor Block Block Transmit Transmit STS-1 POH STS-1 POH Processor Processor Block Block Channel 0 Clock Clock Synthesizer Synthesizer Block Block From Channels 1&2 Transmit Transmit STS-3 TOH STS-3 TOH Processor Processor Block Block Receive Receive STS-3 TOH STS-3 TOH Processor Processor Block Block Transmit Transmit STS-3 PECL STS-3 PECL Interface Interface Block Block Transmit STS-3 Transmit STS-3 Telecom Bus Telecom Bus Interface Interface Block Block Clock & Clock & Data Data Recovery Recovery Block Block Transmit Transmit SONET POH SONET POH Processor Processor Block Block Receive Receive SONET POH SONET POH Processor Processor Block Block Receive STS-3 Receive STS-3 Telecom Bus Telecom Bus Interface Interface Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block To Channels 1 & 2 Receive Receive STS-3 PECL STS-3 PECL Interface Interface Block Block DS3/E3 Jitter DS3/E3 Jitter Attenuator Attenuator Block Block 547 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.11.1 RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 477: Receive STS-1 TOH and POH Processor Block Control Register Address Map INDIVIDUAL REGISTER ADDRESS 0x00 - 0x02 0x03 0x04, 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D, 0x1E 0x1F ADDRESS LOCATION 0xN000 - 0xN102 0xN103 0xN104 - 0xN105 0xN106 0xN107 0xN108 0xN109 0xN10A 0xN10B 0xN10C 0xN10D 0xN10E 0xN10F 0xN110 0xN111 0xN112 0xN113 0xN114 0xN115 0xN116 0xN117 0xN118 0xN119 0xN11A 0xN11B 0xN11C 0xN11D - 0xN11E 0xN11F Reserved Receive STS-1 Transport Control Register - Byte 0 Reserved Receive STS-1 Transport Status Register - Byte 1 Receive STS-1 Transport Status Register - Byte 0 Reserved Receive STS-1 Transport Interrupt Status Register - Byte 2 Receive STS-1 Transport Interrupt Status Register - Byte 1 Receive STS-1 Transport Interrupt Status Register - Byte 0 Reserved Receive STS-1 Transport Interrupt Enable Register - Byte 2 Receive STS-1 Transport Interrupt Enable Register - Byte 1 Receive STS-1 Transport Interrupt Enable Register - Byte 0 Receive STS-1 Transport B1 Byte Error Count - Byte 3 Receive STS-1 Transport B1 Byte Error Count - Byte 2 Receive STS-1 Transport B1 Byte Error Count - Byte 1 Receive STS-1 Transport B1 Byte Error Count - Byte 0 Receive STS-1 Transport B2 Byte Error Count - Byte 3 Receive STS-1 Transport B2 Byte Error Count - Byte 2 Receive STS-1 Transport B2 Byte Error Count - Byte 1 Receive STS-1 Transport B2 Byte Error Count - Byte 0 Receive STS-1 Transport REI-L Error Count - Byte 3 Receive STS-1 Transport REI-L Error Count - Byte 2 Receive STS-1 Transport REI-L Error Count - Byte 1 Receive STS-1 Transport REI-L Error Count - Byte 0 Reserved Reserved Receive STS-1 Transport - Received K1 Byte Value Register REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 548 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0xN120 - 0xN122 0xN123 0xN124 - 0xN126 0xN127 0xN128 - 0xN12D 0xN12E 0xN12F 0xN130 0xN131 0xN132 0xN133 0xN134, 0xN135 0xN136 0xN137 0xN138 - 0xN139 0xN13A 0xN13B 0xN13C 0xN13D 0xN13E 0xN13F 0xN140 - 0xN141 0xN142 0xN143 0xN144, 0xN145 0xN146 Reserved Receive STS-1 Transport - Received K2 Byte Value Register Reserved Receive STS-1 Transport - Received S1 Byte Value Register Reserved Receive STS-1 Transport - LOS Threshold Value - MSB Receive STS-1 Transport - LOS Threshold Value - LSB Reserved Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SF Set Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SF Set Threshold - Byte 1 Receive STS-1 Transport - Receive SF Set Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SF Clear Threshold - Byte 1 Receive STS-1 Transport - Receive SF Clear Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SD Set Threshold - Byte 1 Receive STS-1 Transport - Receive SD Set Threshold - Byte 0 Reserved Receive STS-1 Transport - Receive SD Clear Threshold - Byte 1 REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 INDIVIDUAL REGISTER ADDRESS 0x20 - 0x22 0x23 0x24 - 0x26 0x27 0x28 - 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34, 0x35 0x36 0x37 0x38, 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40, 0x41 0x42 0x43 0x44, 0x45 0x46 549 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x47 0x48 - 0x4A 0x4B 0x4C - 0x4E 0x4F 0x50 - 0x51 0x52 0x53 0x54, 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 - 0x62 0x63 0x64 - 0x6A 0x6B ADDRESS LOCATION 0xN147 0xN14B - 0xN14A 0xN14B 0xN14C - 0xN14E 0xN14F 0xN150 - 0xN151 0xN152 0xN153 0xN154, 0xN155 0xN156 0xN157 0xN158 0xN159 0xN15A 0xN15B 0xN15C 0xN15D 0xN15E 0xN15F 0xN160 - 0xN162 0xN163 0xN164 - 0xN16A 0xN16B REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 Receive STS-1 Transport - Receive SD Clear Threshold - Byte 0 Reserved Receive STS-1 Transport - Force SEF Condition Reserved Receive STS-1 Transport - Receive J0 Byte Trace Buffer Control Register Reserved Receive STS-1 Transport - Receive SD Burst Error Count Tolerance - Byte 1 Receive STS-1 Transport - Receive SD Burst Error Count Tolerance - Byte 0 Reserved Receive STS-1 Transport - Receive SF Burst Error Count Tolerance - Byte 1 Receive STS-1 Transport - Receive SF Burst Error Count Tolerance - Byte 0 Reserved Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 2 Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 1 Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 0 Reserved Receive STS-1 Transport - Auto AIS Control Register Reserved Receive STS-1 Transport - Auto AIS (in Downstream STS-1s) Control Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 550 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0xN16C - 0xN182 0xN183 0xN184 0xN185 0xN186 0xN187 0xN188 0xN189 0xN18A 0xN18B 0xN18C 0xN18D 0xN18E 0xN18F 0xN190 - 0xN192 0xN193 0xN194, 0xN195 0xN196 0xN197 0xN198 0xN199 0xN19A 0xN19B 0xN19C 0xN19D 0xN19E 0xN19F 0xN1A0 - 0xN1A5 0xN1A6 0xN1A7 Reserved Receive STS-1 Path - Control Register - Byte 2 Reserved Receive STS-1 Path - Control Register - Byte 1 Receive STS-1 Path - Status Register - Byte 0 Reserved Receive STS-1 Path - Interrupt Status Register - Byte 2 Receive STS-1 Path - Interrupt Status Register - Byte 1 Receive STS-1 Path - Interrupt Status Register - Byte 0 Reserved Receive STS-1 Path - Interrupt Enable Register - Byte 2 Receive STS-1 Path - Interrupt Enable Register - Byte 1 Receive STS-1 Path - Interrupt Enable Register - Byte 0 Reserved Receive STS-1 Path - SONET Receive RDI-P Register Reserved Receive STS-1 Path - Received Path Label Value (C2 Byte) Register Receive STS-1 Path - Expected Path Label Value (C2 Byte) Register Receive STS-1 Path - B3 Error Count Register - Byte 3 Receive STS-1 Path - B3 Error Count Register - Byte 2 Receive STS-1 Path - B3 Error Count Register - Byte 1 Receive STS-1 Path - B3 Error Count Register - Byte 0 Receive STS-1 Path - REI-P Error Count Register - Byte 3 Receive STS-1 Path - REI-P Error Count Register - Byte 2 Receive STS-1 Path - REI-P Error Count Register - Byte 1 Receive STS-1 Path - REI-P Error Count Register - Byte 0 Reserved Receive STS-1 Path - Pointer Value Register - Byte 1 Receive STS-1 Path - Pointer Value Register - Byte 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 INDIVIDUAL REGISTER ADDRESS 0x6C - 0x82 0x83 0x84, 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 - 0x92 0x93 0x94, 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 - 0xA5 0xA6 0xA7 551 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0xA8 - 0xBA 0xBB 0xBC - 0xBE 0xBF 0xC0 - 0xC2 0xC3 0xC4 - 0xD2 0xD3 0xC4-0xC6 0xD7 0xD8 - 0xDA 0xDB 0xDC - 0xDE 0xDF 0xE0 - 0xE2 0xE3 0xE4 - 0xE6 0xE7 0xE8 - 0xEA 0xEB 0xEC - 0xEE 0xEF 0xF0 - 0xF2 0xF3 0xF6 - 0xFF ADDRESS LOCATION 0xN1A8 - 0xN1BA 0xN1BB 0xN1BC - 0xN1BE 0xN1BF 0xN1C0 - 0xN1C2 0xN1C3 0xN1C4 - 0xN1D2 0xN1D3 0xN1C4 - 0xN1C6 0xN1D7 0xN1D8 - 0xN1DA 0xN1DB 0xN1DC - 0xN1DE 0xN1DF 0xN1E0 - 0xN1E2 0xN1E3 0xN1E4 - 0xN1E6 0xN1E7 0xN1E8 - 0xN1EA 0xN1EB 0xN1EC - 0xN1EE 0xN1EF 0xN1F0 - 0xN1F2 0xN1F3 0xN1F6 - 0xN1FF Reserved Receive STS-1 Path - AUTO AIS Control Register Reserved Receive STS-1 Path - Serial Port Control Register Reserved Receive STS-1 Path - SONET Receive Auto Alarm Register - Byte 0 Reserved Receive STS-1 Path - Receive J1 Byte Capture Register Reserved Receive STS-1 Path - Receive B3 Byte Capture Register Reserved Receive STS-1 Path - Receive C2 Byte Capture Register Reserved Receive STS-1 Path - Receive G1 Byte Capture Register Reserved Receive STS-1 Path - Receive F2 Byte Capture Register Reserved Receive STS-1 Path - Receive H4 Byte Capture Register Reserved Receive STS-1 Path - Receive Z3 Byte Capture Register Reserved Receive STS-1 Path - Receive Z4 (K3) Byte Capture Register Reserved Receive STS-1 Path - Receive Z5 Byte Capture Register Reserved 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 552 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTER DESCRIPTION 1.11.2 Table 478: Receive STS-1 Transport Control Register - Byte 0 (Address Location = 0xN103) BIT 7 Unused R/O 0 BIT 6 SF Detect Enable R/W 0 BIT 5 SD Detect Enable R/W 0 BIT 4 Descramble Disable R/W 0 BIT 3 Unused R/O 0 BIT 2 REI-L Error Type R/W 0 BIT 1 B2 Error Type R/W 0 BIT 0 B1 Error Type R/W 0 BIT NUMBER 7 6 NAME Unused SF Detect Enable TYPE R/O R/W DESCRIPTION Signal Failure (SF) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SF Detection by the Receive STS-1 TOH Processor block. 0 - SF Detection is disabled. 1 - SF Detection is enabled: 5 SD Detect Enable R/W Signal Degrade (SD) Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SD Detection by the Receive STS-1 TOH Processor block. 0 - SD Detection is disabled. 1 - SD Detection is enabled. 4 Descramble Disable R/W De-Scramble Disable: This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Receive STS-1 TOH Processor block, associated with channel N. 0 - De-Scrambling is enabled. 1 - De-Scrambling is disabled. 3 2 Unused REI-L Error Type R/O R/W REI-L Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport REI-L Error Count" register is incremented. 0 - Configures the Receive STS-1 TOH Processor block to count REI-L Bit Errors. In this case the "Receive Transport REI-L Error Count" register will be incremented by the value of the lower nibble within the M0/M1 byte. 1 - Configures the Receive STS-1 TOH Processor block to count REI-L Frame Errors. In this case the "Receive Transport REI-L Error Count" register will be incremented each time the Receive STS-1 TOH Processor block receives a "non-zero" M0/M1 byte. 1 B2 Error Type R/W B2 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive 553 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Transport B2 Error Count" register is incremented. 0 - Configures the Receive STS-1 TOH Processor block to count B2 bit errors. In this case, the "Receive Transport B2 Error Count" register will be incremented by the number of bits, within the B2 value, that is in error. 1 - Configures the Receive STS-1 TOH Processor block to count B2 frame errors. In this case, the "Receive Transport B2 Error Count" register will be incremented by the number of erred STS-1 frames. 0 B1 Error Type R/W B1 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Transport B1 Error Count" register is incremented. 0 - Configures the Receive STS-1 TOH Processor block to count B1 bit errors. In this case, the "Receive Transport B1 Error Count" register will be incremented by the number of bits, within the B1 value, that is in error. 1 - Configures the Receive STS-1 TOH Processor block to count B2 bit errors. In this case, the "Receive Transport B1 Error Count" register will be incremented by the number of erred STS-1 frames. 20 0 Rev2...0...0 200 554 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 479: Receive STS-1 Transport Status Register - Byte 1 (Address Location= 0xN106) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 J0 Message Mismatch R/O 0 BIT 1 J0 Message Unstable R/O 0 BIT 0 AIS_L Detected R/O 0 BIT NUMBER 7-3 2 NAME Unused J0 Message Mismatch TYPE R/O R/O DESCRIPTION J0 - Section Trace Mismatch Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the Section Trace Mismatch condition. The Receive STS-1 TOH Processor block will declare a J0 (Section Trace) Mismatch condition, whenever it accepts a J0 Message that differs from the "Expected J0 Message". 0 - Section Trace Mismatch Condition is NOT declared. 1 - Section Trace Mismatch Condition is currently declared. 1 J0 Message Unstable R/O J0 - Section Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the Section Trace Instability condition. The Receive STS-1 TOH Processor block will declare a J0 (Section Trace) Unstable condition, whenever the "J0 Unstable" counter reaches the value 8. The "J0 Unstable" counter will be incremented for each time that it receives a J0 message that differs from the "Expected J0 Message". The "J0 Unstable" counter is cleared to "0" whenever the Receive STS-3 TOH Processor block has received a given J0 Message 3 (or 5) consecutive times. Note: Receiving a given J0 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Section Trace Instability condition is NOT declared. 1 - Section Trace Instability condition is currently declared. 0 AIS_L Detected R/O AIS-L State: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently detecting an AIS-L (Line AIS) pattern in the incoming STS-1 data stream. AIS-L is declared if bits 6, 7 and 8 (e.g., the Least Significant Bits, within the K2 byte) value the value "1, 1, 1" for five consecutive STS-1 frames. 0 - AIS-L is NOT currently declared. 1 - AIS-L is currently being declared. 555 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 480: Receive STS-1 Transport Status Register - Byte 0 (Address Location = 0xN107) BIT 7 RDI-L Declared R/O 0 BIT 6 S1 Unstable BIT 5 APS Unstable R/O 0 BIT 4 SF Detected R/O 0 BIT 3 SD Detected R/O 0 BIT 2 LOF Defect Detected R/O 0 BIT 1 SEF Defect Declared R/O 0 BIT 0 LOS Defect Declared R/O 0 20 0 Rev2...0...0 200 R/O 0 BIT NUMBER 7 NAME RDI-L Declared TYPE R/O RDI-L Indicator: DESCRIPTION This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is detecting a Line-Remote Defect Indicator, in the incoming STS-1 signal. RDI-L is declared when bits 6, 7 and 8 (e.g., the three least significant bits) of the K2 byte contains the "1, 1, 0" pattern in 5 consecutive STS-1 frames. 0 - RDI-L is NOT being declared. 1 - RDI-L is currently being declared. 6 S1 Unstable R/O S1 Unstable Condition: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the "S1 Byte Instability" condition. The Receive STS-1 TOH Processor block will declare an "S1 Byte Instability" condition whenever the "S1 Byte Unstable Counter" reaches the value 32. The "S1 Byte Unstable Counter" is incremented for each time that the Receive STS-1 TOH Processor block receives an S1 byte that differs from the previously received S1 byte. The "S1 Byte Unstable Counter" is cleared to "0" when the same S1 byte is received for 8 consecutive STS-1 frames. Note: Receiving a given S1 byte, in 8 consecutive STS-1 frames also sets this bit-field to "0". 0 - S1 Instability Condition is NOT declared. 1 - S1 Instability Condition is currently declared. 5 APS Unstable R/O APS (K1, K2 Byte) Instability: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the "K1, K2 Byte Unstable" condition. The Receive STS-1 TOH Processor block will declare a "K1, K2 Byte Unstable" condition whenever the Receive STS-1 TOH Processor block fails to receive the same set of K1, K2 bytes, in 12 consecutive STS-1 frames. The "K1, K2 Byte Instability" condition is cleared whenever the STS-1 Receiver receives a given set of K1, K2 byte values in three consecutive STS-1 frames. 0 - K1, K2 Instability Condition is NOT declared. 1 - K1, K2 Instability Condition is currently declared. 4 SF Detected R/O SF (Signal Failure) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the SF defect. The SF defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SF Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given 556 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS interval of time) does not exceed the "SF Declaration" threshold. 1 - SF Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SF Declaration" threshold. 3 SD Detected R/O SD (Signal Degrade) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the SD defect. The SD defect is declared when the number of B2 errors observed over a given time interval exceeds a certain threshold. 0 - SD Defect is NOT being declared. This bit is set to "0" when the number of B2 errors (accumulated over a given interval of time) does not exceed the "SD Declaration" threshold. 1 - SD Defect is being declared. This bit is set to "1" when the number of B2 errors (accumulated over a given interval of time) does exceed the "SD Declaration" threshold. 2 LOF Defect Declared R/O LOF (Loss of Frame) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring the LOF defect. The Receive STS-1 TOH Processor block will declare the LOF defect if it has been declaring the SEF condition for 24 consecutive STS-1 frame periods. Once the LOF defect is declared, then the Receive STS-1 TOH Processor block will clear the LOF defect if it has not been declaring the SEF condition for 3ms (or 24 consecutive STS-1 frame periods). 0 - The Receive STS-1 TOH Processor block is NOT currently declaring the LOF condition. 1 - The Receive STS-1 TOH Processor block is currently declaring the LOF condition. 1 SEF Defect Declared R/O SEF (Severely Errored Frame): This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring an SEF condition. The Receive STS-1 TOH Processor block will declare an SEF condition if it detects Framing Alignment byte errors in four consecutive STS-1 frames. Once the SEF condition is declared the Receive STS-1 TOH Processor block will clear the SEF condition if it detects two consecutive STS-1 frames with un-erred framing alignment bytes. 0 - Indicates that the Receive STS-1 TOH Processor block is NOT declaring the SEF condition. 1 - Indicates that the Receive STS-1 TOH Processor block is currently declaring the SEF condition. 0 LOS Defect Declared R/O LOS (Loss of Signal) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH Processor block is currently declaring an LOS (Loss of Signal) condition. The Receive STS-1 TOH Processor block will declare an LOS condition if it detects "LOS_THRESHOLD[15:0]" consecutive "All Zero" bytes in the incoming STS-1 data stream. Note: The user can set the "LOS_THRESHOLD[15:0]" value by writing the appropriate data into the "Receive STS-1 Transport - LOS Threshold Value" Register (Address Location= 0xN12E and 0xN12F). 0 - Indicates that the Receive STS-1 TOH Processor block is NOT currently 557 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS declaring an LOS condition. 1 - Indicates that the Receive STS-1 TOH Processor block is currently declaring an LOS condition. 20 0 Rev2...0...0 200 558 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 481: Receive STS-1 Transport Interrupt Status Register - Byte 2 (Address Location= 0xN109) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Interrupt Status RUR 0 BIT 0 Change of RDI-L Interrupt Status RUR 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Interrupt Status TYPE R/O RUR DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of AIS-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of AIS-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of AIS-L by reading the contents of Bit 0 (AIS-L Defect Declared) within the "Receive STS-1 Transport Status Register - Byte 1" (Address Location= 0xN106). 0 Change of RDI-L Interrupt Status RUR Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of RDI-L Condition" interrupt has occurred since the last read of this register. 0 - The "Change of RDI-L Condition" interrupt has not occurred since the last read of this register. 1 - The "Change of RDI-L Condition" interrupt has occurred since the last read of this register. Note: The user can obtain the current state of RDI-L by reading out the state of Bit 7 (RDI-L Declared) within the "Receive STS-1 Transport Status Register - Byte 0" (Address Location= 0xN107). 559 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 482: Receive STS-1 Transport Interrupt Status Register - Byte 1 (Address Location= 0xN10A) BIT 7 New S1 Byte Interrupt Status BIT 6 Change in S1 Unstable State Interrupt Status RUR 0 BIT 5 Change in J0 Unstable State Interrupt Status RUR 0 BIT 4 New J0 Message Interrupt Status BIT 3 J0 Mismatch Interrupt Status BIT 2 Unused BIT 1 Change in APS Unstable State Interrupt Status RUR 0 BIT 0 NEW K1K2 Byte Interrupt Status RUR 0 RUR 0 RUR 0 R/O 0 RUR 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Status TYPE RUR DESCRIPTION New S1 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New S1 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New S1 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New S1 Byte Value" interrupt has occurred since the last read of this register. Note: The user can obtain the value for this most recently accepted value of the S1 byte by reading the "Receive STS-1 Transport S1 Value" register (Address Location= 0xN127). 6 Change in S1 Byte Unstable State Interrupt Status RUR Change in S1 Byte Unstable State - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has occurred since the last read of this register. 1 - Indicates that the "Change in S1 Byte Unstable State" Interrupt has not occurred since the last read of this register. Note: The user can obtain the current "S1 Unstable" state by reading the contents of Bit 6 (S1 Unstable) within the "Receive STS-1 Transport Status Register - Byte 0" (Address Location= 0xN107). 5 Change in J0 Message Unstable State Interrupt Status RUR Change of J0 (Section Trace) Message Unstable condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change of J0 (Section Trace) Message Instability" condition interrupt has occurred since the last read of this register. 4 New J0 Message Interrupt Status RUR New J0 Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the 560 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS "New J0 Trace Message" interrupt has occurred since the last read of this register. 0 - Indicates that the "New J0 Trace Message Interrupt" has not occurred since the last read of this register. 1 - Indicates that the "New J0 Trace Message Interrupt" has occurred since the last read of this register. Note: The user can read out the contents of the "Receive J0 Trace Buffer", which is located at Address Locations 0xN300 through 0xN33F. 3 J0 Mismatch Interrupt Status RUR Change in J0 - Section Trace Mismatch Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in J0 - Section Trace Mismatch Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared" or "declared" by reading the state of Bit 2 (J0_MIS) within the "Receive STS-1 Transport Status Register - Byte 1 (Address Location= 0xN106). 2 1 Unused Change in APS Unstable State Interrupt Status R/O RUR Change of APS (K1, K2 Byte) Instability Condition - Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. 0 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of APS (K1, K2 Byte) Instability Condition" interrupt has occurred since the last read of this register. Note: The user can determine whether the "K1, K2 Instability Condition" is being declared or cleared by reading out the contents of Bit 5 (APS_INV), within the "Receive STS-1 Transport Status Register - Byte 0" (Address Location= 0xN107). 0 New K1K2 Byte Interrupt Status RUR New K1, K2 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. 0 - Indicates that the "New K1, K2 Byte Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New K1, K2 Byte Value" Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the new K1 byte by 561 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 reading out the contents of the "Receive STS-1 Transport K1 Value" Register (Address Location= 0xN11F). Further, the user can also obtain the contents of the new K2 byte by reading out the contents of the "Receive STS-1 Transport K2 Value" Register (Address Location= 0xN123). 562 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 483: Receive STS-1 Transport Interrupt Status Register - Byte 0 (Address Location= 0xN10B) BIT 7 Change of SF Condition Interrupt Status RUR 0 BIT 6 Change of SD Condition Interrupt Status RUR 0 BIT 5 Detection of REI-L Error Interrupt Status RUR 0 BIT 4 Detection of B2 Error Interrupt Status RUR 0 BIT 3 Detection of B1 Error Interrupt Status RUR 0 BIT 2 Change of LOF Condition Interrupt Status RUR 0 BIT 1 Change of SEF Interrupt Status RUR 0 BIT 0 Change of LOS Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Change of SF Condition Interrupt Status TYPE RUR DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of SF Interrupt" has occurred since the last read of this register. 0 - The "Change of SF Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SF Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SF" condition by reading out the state of Bit 4( SF Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 6 Change of SD Condition Interrupt Status RUR Change of Signal Degrade (SD) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SD Condition Interrupt" has occurred since the last read of this register. 0 - The "Change of SD Condition Interrupt" has NOT occurred since the last read of this register. 1 - The "Change of SD Condition Interrupt" has occurred since the last read of this register. Note: The user can determine the current "SD" condition by reading out the state of Bit 3 (SD Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 5 Detection of REI-L Interrupt Status RUR Detection of Line - Remote Error Indicator Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 0 - The "Detection of Line - Remote Error Indicator" Interrupt has NOT occurred since the last read of this register. 1 - The "Detection of Line - Remote Error Indicator" Interrupt has occurred since the last read of this register. 4 Detection of B2 Error Interrupt Status RUR Detection of B2 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B2 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B2 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B2 Error Interrupt" has occurred since the last read of this register. 563 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 3 Detection of B1 Error Interrupt Status RUR Detection of B1 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B1 Error Interrupt" has occurred since the last read of this register. 0 - The "Detection of B1 Error Interrupt" has NOT occurred since the last read of this register. 1 - The "Detection of B1 Error Interrupt" has occurred since the last read of this register 2 Change of LOF Condition Interrupt Status RUR Change of Loss of Frame (LOF) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOF Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOF Condition" interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOF Condition" interrupt has occurred since the last read of this register. Note: The user can determine the current "LOF" condition by reading out the state of Bit 2 (LOF Defect Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 20 0 Rev2...0...0 200 1 Change of SEF Condition Interrupt Status RUR Change of SEF Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of SEF Condition" Interrupt has occurred since the last read of this register. 0 - The "Change of SEF Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of SEF Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "SEF" condition by reading out the state of Bit 1 (SEF Defect Declared) within the "Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 0 Change of LOS Condition Interrupt Status RUR Change of Loss of Signal (LOS) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOS Condition" interrupt has occurred since the last read of this register. 0 - The "Change of LOS Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOS Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current "LOS" status by reading out the contents of Bit 0 (LOS Defect Declared) within the Receive STS-1 Transport Status Register - Byte 0 (Address Location= 0xN107). 564 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 484: Receive STS-1 Transport Interrupt Enable Register - Byte 2 (Address Location= 0xN10D) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 Change of AIS-L Condition Interrupt Enable R/O 0 R/O 0 R/O 0 R/W 0 BIT 0 Change of RDI-L Condition Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused Change of AIS-L Condition Interrupt Enable TYPE R/O R/W DESCRIPTION Change of AIS-L (Line AIS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "AIS-L" condition. * When the STS-1 Receiver clears the "AIS-L" condition. 0 - Disables the "Change of AIS-L Condition" Interrupt. 1 - Enables the "Change of AIS-L Condition" Interrupt. 0 Change of RDI-L Condition Interrupt Enable R/W Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of RDI-L Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "RDI-L" condition. * When the Receive STS-1 TOH Processor clears the "RDI-L" condition. 0 - Disables the "Change of RDI-L Condition" Interrupt. 1 - Enables the "Change of RDI-L Condition" Interrupt. 565 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 485: Receive STS-1 Transport Interrupt Enable Register - Byte 1 (Address Location= 0xN10E) BIT 7 New S1 Byte Interrupt Enable BIT 6 Change in S1 Byte Unstable State Interrupt Enable R/W 0 BIT 5 Change in J0 Message Unstable State Interrupt Enable R/W 0 BIT 4 New J0 Message Interrupt Enable BIT 3 J0 Mismatch Interrupt Enable BIT 2 Unused BIT 1 Change in APS Unstable State Interrupt Enable R/W 0 BIT 0 New K1K2 Byte Interrupt Enable R/W 0 R/W 0 R/W 0 R/O 0 R/W 0 BIT NUMBER 7 NAME New S1 Byte Value Interrupt Enable TYPE R/W DESCRIPTION New S1 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New S1 Byte Value" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate this interrupt anytime it receives and accepts a new S1 byte value. The Receive STS-1 TOH Processor block will accept a new S1 byte after it has received it for 8 consecutive STS-1 frames. 0 - Disables the "New S1 Byte Value" Interrupt. 1 - Enables the "New S1 Byte Value" Interrupt. 6 Change in S1 Unstable State Interrupt Enable R/W Change in S1 Byte Unstable State Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in S1 Byte Unstable State" Interrupt. If the user enables this bit-field, then the Receive STS-1 TOH Processor block will generate an interrupt in response to either of the following conditions. * * When the Receive STS-1 TOH Processor block declares the "S1 Byte Instability" condition. When the Receive STS-1 TOH Processor block clears the "S1 Byte Instability" condition. 0 - Disables the "Change in S1 Byte Unstable State" Interrupt. 1 - Enables the "Change in S1 Byte Unstable State" Interrupt. 5 Change in J0 Message Unstable State Interrupt Enable R/W Change of J0 (Section Trace) Message Instability condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of J0 Message Instability Condition" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an interrupt in response to either of the following conditions. * * Whenever the Receive STS-1 TOH Processor block declares the "J0 Message Instability" condition. Whenever the Receive STS-1 TOH Processor block clears the "J0 Message Instability" condition. 0 - Disable the "Change of J0 Message Instability" Interrupt. 1 - Enables the "Change of J0 Message Instability" Interrupt. 4 New J0 Message Interrupt Enable R/W New J0 Trace Message Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "New J0 Trace Message" interrupt. If the user enables this interrupt, then the 566 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Receive STS-1 TOH Processor block will generate this interrupt anytime it receives and accepts a new J0 Trace Message. The Receive STS-1 TOH Processor block will accept a new J0 Trace Message after it has received it 3 (or 5) consecutive times. 0 - Disables the "New J0 Trace Message" Interrupt. 1 - Enables the "New J0 Trace Message" Interrupt. 3 J0 Mismatch Interrupt Enable R/W Change in "J0 - Section Trace Mismatch Condition" interrupt enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in J0 - Section Trace Mismatch condition" interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an interrupt in response to either of the following events. c. d. Note: The Receive STS-1 TOH Processor block declares a "J0 - Section Trace Mismatch" condition. The Receive STS-1 TOH Processor block clears the "J0 - Section Trace Mismatch" condition. The user can determine whether the "J0 - Section Trace Mismatch" condition is "cleared or "declared" by reading the state of Bit 2 (J0_MIS) within the "Receive STS-1 Transport Status Register - Byte 1 (Address Location= 0xN106). 2 1 Unused Change in APS Unstable State Interrupt Enable R/O R/W Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of APS (K1, K2 Byte) Instability condition" interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an Interrupt in response to either of the following events. c. d. If the Receive STS-1 TOH Processor block declares a "K1, K2 Instability" condition. If the Receive STS-1 TOH Processor block clears the "K1, K2 Instability" condition. 0 New K1K2 Byte Interrupt Enable R/W New K1, K2 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New K1, K2 Byte Value" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate this interrupt anytime it receives and accepts a new K1, K2 byte value. The Receive STS-1 TOH Processor block will accept a new K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-1 frames. 0 - Disables the "New K1, K2 Byte Value" Interrupt. 1 - Enables the "New K1, K2 Byte Value" Interrupt. 567 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 486: Receive STS-1Transport Interrupt Status Register - Byte 0 (Address Location= 0xN10F) BIT 7 Change of SF Condition Interrupt Enable R/W 0 BIT 6 Change of SD Condition Interrupt Enable R/W 0 BIT 5 Detection of REI-L Error Interrupt Enable R/W 0 BIT 4 Detection of B2 Error Interrupt Enable R/W 0 BIT 3 Detection of B1 Error Interrupt Enable R/W 0 BIT 2 Change of LOF Condition Interrupt Enable R/W 0 BIT 1 Change of SEF Condition Interrupt Enable R/W 0 BIT 0 Change of LOS Condition Interrupt Enable R/W 0 BIT NUMBER 7 NAME Change of SF Condition Interrupt Enable TYPE R/W DESCRIPTION Change of Signal Failure (SF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Failure (SF) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects an SF condition. 0 - Disables the "Change of SF Condition Interrupt". 1 - Enables the "Change of SF Condition Interrupt". 6 Change of SD Condition Interrupt Enable R/W Change of Signal Degrade (SD) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Signal Degrade (SD) Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects an SD condition. 0 - Disables the "Change of SD Condition Interrupt". 1 - Enables the "Change of SD Condition Interrupt". 5 Detection of REI-L Interrupt Enable R/W Detection of Line - Remote Error Indicator Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Line - Remote Error Indicator" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects an REI-L condition. 0 - Disables the "Line - Remote Error Indicator" Interrupt. 1 - Enables the "Line - Remote Error Indicator" Interrupt. 4 Detection of B2 Error Interrupt Enable R/W Detection of B2 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B2 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects a B2 error. 0 - Disables the "Detection of B2 Error Interrupt". 1 - Enables the "Detection of B2 Error Interrupt". 3 Detection of B1 Error Interrupt Enable R/W Detection of B1 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B1 Error" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt anytime the Receive STS-1 TOH Processor block detects a B1 error. 0 - Disables the "Detection of B1 Error Interrupt". 1 - Enables the "Detection of B1 Error Interrupt". 568 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Change of LOF Condition Interrupt Enable R/W Change of Loss of Frame (LOF) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "LOF" condition. * When the Receive STS-1 TOH Processor block clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 2 1 Change of SEF Condition Interrupt Enable R/W Change of SEF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of SEF Condition" Interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "SEF" condition. * When the Receive STS-1 TOH Processor block clears the "SEF" condition. 0 - Disables the " Change of SEF Condition Interrupt". 1 - Enables the "Change of SEF Condition Interrupt". 0 Change of LOS Condition Interrupt Enable R/W Change of Loss of Signal (LOS) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" interrupt. If the user enables this interrupt, then the XRT94L33 device will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 TOH Processor block declares the "LOF" condition. * When the Receive STS-1 TOH Processor block clears the "LOF" condition. 0 - Disables the "Change of LOF Condition Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. 569 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 487: Receive STS-1 Transport - B1 Error Count Register - Byte 3 (Address Location= 0xN110) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[31:24] BIT NUMBER 7-0 NAME B1_Error_Count[31:24] TYPE RUR B1 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 488: Receive STS-1 Transport - B1 Error Count Register - Byte 2 (Address Location= 0xN111) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[23:16] BIT NUMBER 7-0 NAME B1_Error_Count[23:16] TYPE RUR DESCRIPTION B1 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 489: Receive STS-1 Transport - B1 Error Count Register - Byte 1 (Address Location= 0xN112) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 570 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS B1_Error_Count[15:8] RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7-0 NAME B1_Error_Count[15:8] TYPE RUR DESCRIPTION B1 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. Table 490: Receive STS-1 Transport - B1 Error Count Register - Byte 0 (Address Location= 0xN113) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B1_Error_Count[7:0] BIT NUMBER 7-0 NAME B1_Error_Count[7:0] TYPE RUR B1 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B1 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B1 byte error. Note: 1. If the B1 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B1 value that are in error. 2. If the B1 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B1 bytes. 571 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 491: Receive STS-1 Transport - B2 Error Count Register - Byte 3 (Address Location= 0xN114) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[31:24] BIT NUMBER 7-0 NAME B2_Error_Count[31:24] TYPE RUR B2 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Transport - B2 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 492: Receive STS-1 Transport - B2 Error Count Register - Byte 2 (Address Location= 0xN115) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[23:16] BIT NUMBER 7-0 NAME B2_Error_Count[23:16] TYPE RUR DESCRIPTION B2 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. 572 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 493: Receive STS-1 Transport - B2 Error Count Register - Byte 1 (Address Location= 0xN116) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[15:8] BIT NUMBER 7-0 NAME B2_Error_Count[15:8] TYPE RUR DESCRIPTION B2 Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. Table 494: Receive STS-1 Transport - B2 Error Count Register - Byte 0 (Address Location= 0xN117) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B2_Error_Count[7:0] BIT NUMBER 7-0 NAME B2_Error_Count[7:0] TYPE RUR B2 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - B2 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a B2 byte error. Note: 1. If the B2 Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of bits, within the B2 value that are in error. 2. If the B2 Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain erred B2 bytes. 573 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 495: Receive STS-1 Transport - REI-L Error Count Register - Byte 3 (Address Location = 0xN118) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[31:24] BIT NUMBER 7-0 NAME REI_L_Error_Count[31:24] TYPE RUR DESCRIPTION REI-L Error Count - MSB: This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 496: Receive STS-1 Transport - REI_L Error Count Register - Byte 2 (Address Location= 0xN119) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[23:16] BIT NUMBER 7-0 NAME REI_L_Error_Count[23:16] TYPE RUR DESCRIPTION REI-L Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 574 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 497: Receive STS-1 Transport - REI_L Error Count Register - Byte 1 (Address Location= 0xN11A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[15:8] BIT NUMBER 7-0 NAME REI_L_Error_Count[15:8] TYPE RUR DESCRIPTION REI-L Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line -Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. Table 498: Receive STS-1 Transport - REI_L Error Count Register - Byte 0 (Address Location= 0xN11B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_L_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_L_Error_Count[7:0] TYPE RUR REI-L Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive Transport - REI-L Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 TOH Processor block detects a Line - Remote Error Indicator. Note: 1. If the REI-L Error Type is configured to be "bit errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the nibble-value within the REI-L field of the M0 byte. 2. If the REI-L Error Type is configured to be "frame errors", then the Receive STS-1 TOH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-L values. 575 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 499: Receive STS-1 Transport - Received K1 Byte Value (Address Location= 0xN11F) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 Filtered_K1_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K1_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K1 value, that the Receive STS-1 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-1 frames. This register should be polled by Software in order to determine various APS codes. Table 500: Receive STS-1Transport - Received K2 Byte Value (Address Location= 0xN123) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Filtered_K2_Value[7:0] BIT NUMBER 7-0 NAME Filtered_K2_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted K2 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" K2 value, that the Receive STS-1 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-1 frames. This register should be polled by Software in order to determine various APS codes. 576 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 501: Receive STS-1 Transport - Received S1 Byte Value (Address Location= 0xN127) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Filtered_S1_Value[7:0] BIT NUMBER 7-0 NAME Filtered_S1_Value[7:0] TYPE R/O DESCRIPTION Filtered/Accepted S1 Value: These READ-ONLY bit-fields contain the value of the most recently "filtered" S1 value that the Receive STS-1 TOH Processor block has received. These bit-fields are valid if it has been received for 8 consecutive STS-1 frames. Table 502: Receive STS-1 Transport - LOS Threshold Value - MSB (Address Location= 0xN12E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 LOS_THRESHOLD[15:8] BIT NUMBER 7-0 NAME LOS_THRESHOLD[15:8] TYPE R/W DESCRIPTION LOS Threshold Value - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - LOS Threshold Value - LSB" register specify the number of consecutive (All Zero) bytes that the Receive STS-1 TOH Processor block must detect before it can declare an LOS condition. 577 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 503: Receive STS-1 Transport - LOS Threshold Value - LSB (Address Location= 0xN12F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 20 0 Rev2...0...0 200 LOS_THRESHOLD[7:0] BIT NUMBER 7-0 NAME LOS_THRESHOLD[7:0] TYPE R/W DESCRIPTION LOS Threshold Value - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1Transport - LOS Threshold Value - MSB" register specify the number of consecutive (All Zero) bytes that the Receive STS-1 TOH Processor block must detect before it can declare an LOS condition. Table 504: Receive STS-1 Transport - Receive SF SET Monitor Interval - Byte 2 (Address Location= 0xN131 ) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[23:1 6] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into the "Receive Transport SF SET Threshold" register, then an SF condition will be declared. 578 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 505: Receive STS-1 Transport - Receive SF SET Monitor Interval - Byte 1 (Address Location= 0xN132) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[15:8] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL (Bits 15 through 8): These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SF SET Threshold" register, then an SF condition will be declared. Table 506: Receive STS-1 Transport - Receive SF SET Monitor Interval - Byte 0 (Address Location= 0xN133) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_SET_MONITOR_WINDOW[7:0 ] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 bit errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SF SET Threshold" register, then an SF condition will be declared. 579 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 507: Receive STS-1 Transport - Receive SF SET Threshold - Byte 1 (Address Location= 0xN136) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SF SET Threshold - Byte 0" register, then an SF condition will be declared. Table 508: Receive STS-1 Transport - Receive SF SET Threshold - Byte 0 (Address Location= 0xN137) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_SET_THRESHOLD[7:0] TYPE R/W DESCRIPTION SF_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SF SET Threshold - Byte 1" register, then an SF condition will be declared. 580 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 509: Receive STS-1 Transport - Receive SF CLEAR Threshold - Byte 1 (Address Location= 0xN13A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [15:8] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SF CLEAR Threshold - Byte 0" register, then an SF condition will be cleared. Table 510: Receive STS-1 Transport - Receive SF CLEAR Threshold - Byte 0 (Address Location= 0xN13B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SF_CLEAR_THRESHOLD [7:0] TYPE R/W DESCRIPTION SF_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SF (Signal Failure) condition. When the Receive STS-1 TOH Processor block is checking for clearing SF, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SF CLEAR Threshold - Byte 1" register, then an SF condition will be cleared. 581 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 511: Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 2 (Address Location= 0xN13D) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SF_SET_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF SET Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SD SET Threshold" register, then an SD condition will be declared. Table 512: Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 1 (Address Location= 0xN13E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SD SET Threshold" register, then an SD condition will be declared. 582 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 513: Receive STS-1 Transport - Receive SD Set Monitor Interval - Byte 0 (Address Location= 0xN13F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 SD_SET_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_SET_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SD_SET_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a SET Sub-Interval for SD (Signal Degrade) declaration. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors exceeds that of programmed into the "Receive STS-1 Transport SD SET Threshold" register, then an SD condition will be declared. Table 514: Receive STS-1 Transport - Receive SD SET Threshold - Byte 1 (Address Location= 0xN142) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[15:8] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Threshold - Byte 0" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SD SET Threshold - Byte 0" register, then an SD condition will be declared. 583 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 515: Receive STS-1 Transport - Receive SD SET Threshold - Byte 0 (Address Location= 0xN143) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_SET_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_SET_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_SET_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD SET Threshold - Byte 1" registers permit the user to specify the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to declare an SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for SD, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors exceeds that of programmed into this and the "Receive STS-1 Transport SD SET Threshold - Byte 1" register, then an SD condition will be declared. Table 516: Receive STS-1 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0xN146) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD [15:8] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD CLEAR Threshold - Byte 0" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SD CLEAR Threshold - Byte 0" register, then an SD condition will be cleared. 584 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 517: Receive STS-1 Transport - Receive SD CLEAR Threshold - Byte 1 (Address Location= 0xN147) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_THRESHOLD[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_THRESHOLD[7:0] TYPE R/W DESCRIPTION SD_CLEAR_THRESHOLD - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD CLEAR Threshold - Byte 1" registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-1 TOH Processor block to clear the SD (Signal Degrade) condition. When the Receive STS-1 TOH Processor block is checking for clearing SD, it will accumulate B2 errors for a total of 8 CLEAR Sub-Interval periods. If the number of accumulated B2 errors is less than that programmed into this and the "Receive STS-1 Transport SD CLEAR Threshold - Byte 1" register, then an SD condition will be cleared. Table 518: Receive STS-1 Transport - Force SEF Condition Register (Address Location= 0xN14B) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 SEF FORCE R/W 0 BIT NUMBER 7-1 0 NAME Unused SEF FORCE TYPE R/O R/W SEF Force: DESCRIPTION This READ/WRITE bit-field permits the user to force the Receive STS-1 TOH Processor block (within Channel N) to declare an SEF defect. The Receive STS-1 TOH Processor block will then attempt to reacquire framing. Writing a "1" into this bit-field configures the Receive STS-1 TOH Processor block to declare the SEF defect. The Receive STS-1 TOH Processor block will automatically set this bit-field to "0" once it has reacquired framing (e.g., has detected two consecutive STS-1 frames with the correct A1 and A2 bytes). 585 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 519: Receive STS-1 Transport - Receive J0 Trace Buffer Control Register (Address Location= 0xN14F) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 READ SEL R/W 0 BIT 3 ACCEPT THRD R/W 0 BIT 2 MSG TYPE R/W 0 R/W 0 BIT 1 MSG LENGTH R/W 0 BIT 0 BIT NUMBER 7-5 4 NAME Unused READ SEL TYPE R/O R/W J0 Buffer Read Selection: DESCRIPTION This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. c. d. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive J0 Trace Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive J0 Trace Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Receive STS-3 TOH Processor block, the "Receive J0 Trace Buffer" is located at Address Location 0xN300 through 0xN33F. 3 ACCEPT THRD R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-1 TOH Processor block must receive a given J0 Trace Message, before it is accepted, as described below. 0 - The Receive STS-1 TOH Processor block accepts the J0 Message after it has received it the third time in succession. 1 - The Receive STS-1 TOH Processor block accepts the J0 Message after it has received in the fifth time in succession. 2 MSG TYPE R/W Message Alignment Type: This READ/WRITE bit-field permits a user to specify have the Receive STS-1 TOH Processor block will locate the boundary of the J0 Trace Message, as indicated below. 0 - Message boundary is indicated by "Line Feed". 1 - Message boundary is indicated by the presence of a "1" in the MSB of the first byte (within the J0 Trace Message). 1-0 MSG LENGTH R/W J0 Message Length: These READ/WRITE bit-fields permit the user to specify the length of the J0 Trace Message, that the Receive STS-1 TOH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J0 Trace Message Length is presented below. MSG LENGTH Resulting J0 Trace Message Length 586 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 00 01 10/11 1 Byte 16 Bytes 64 Bytes Table 520: Receive STS-1 Transport - Receive SD Burst Error Tolerance - Byte 1 (Address Location= 0xN152) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SD_BURST_TOLERANCE [15:8] TYPE R/W DESCRIPTION SD_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SD BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. 587 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 521: Receive STS-1 Transport - Receive SD Burst Error Tolerance - Byte 0 (Address Location= 0xN153) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_BURST_TOLERANCE[7:0] BIT NUMBER 7-0 NAME SD_BURST_TOLERANCE[7:0] TYPE R/W DESCRIPTION SD_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SD BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SD (Signal Degrade) condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SD defect condition. 588 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 522: Receive STS-1 Transport - Receive SF Burst Error Tolerance - Byte 1 (Address Location= 0xN156) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_BURST_TOLERANCE[15:8] BIT NUMBER 7-0 NAME SF_BURST_TOLERANCE[15:8] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - MSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SF BURST Tolerance - Byte 0" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SF (Signal Failure) condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "Sub-Interval" periods before it will declare the SF defect condition. 589 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 523: Receive STS-1 Transport - Receive SF Burst Error Tolerance - Byte 0 (Address Location= 0xN157) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_BURST_TOLERANCE[7:0] BIT NUMBER 7-0 NAME SF_BURST_TOLERANCE[7:0] TYPE R/W DESCRIPTION SF_BURST_TOLERANCE - LSB: These READ/WRITE bits, along with the contents of the "Receive STS-1 Transport - SF BURST Tolerance - Byte 1" registers permit the user to specify the maximum number of B2 bit errors that the corresponding Receive STS-1 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-1 frame period), when determining whether or not to declare an SF (Signal Failure) condition. Note: The purpose of this feature is to permit the user to provide some level of B2 error burst filtering, when the Receive STS-1 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS-1 TOH Processor block to detect B2 bit errors in multiple "SubInterval" periods before it will declare the SF defect condition. Table 524: Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 2 (Address Location= 0xN159) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-1 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SD Clear Threshold" register, then the SD defect will be cleared. 590 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 525: Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 1 (Address Location= 0xN15A) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-1 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SD Clear Threshold" register, then the SD defect will be cleared. Table 526: Receive STS-1 Transport - Receive SD Clear Monitor Interval - Byte 0 (Address Location= 0xN15B) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SD_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SD_CLEAR_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SD Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SD (Signal Degrade). When the Receive STS-1 TOH Processor block is checking for clearing the SD defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SD Clear Threshold" register, then the SD defect will be cleared. 591 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 527: Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 2 (Address Location= 0xN15D) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [23:16] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - MSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF Clear Monitor Interval - Byte 1 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SF Clear Threshold" register, then the SF defect will be cleared. Table 528: Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 1 (Address Location= 0xN15E) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [15:8] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - Bits 15 through 8: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF Clear Monitor Interval - Byte 2 and Byte 0" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SF Clear Threshold" register, then the SF defect will be cleared. 592 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 529: Receive STS-1 Transport - Receive SF Clear Monitor Interval - Byte 0 (Address Location= 0xN15F) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 SF_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER 7-0 NAME SF_CLEAR_MONITOR_WINDOW [7:0] TYPE R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL - LSB: These READ/WRITE bits, along the contents of the "Receive STS-1 Transport - SF Clear Monitor Interval - Byte 2 and Byte 1" registers permit the user to specify the number of STS-1 Frame periods that will constitute a CLEAR Sub-Interval for SF (Signal Failure). When the Receive STS-1 TOH Processor block is checking for clearing the SF defect, it will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If the number of accumulated B2 errors is less than that of programmed into the "Receive STS-1 Transport SF Clear Threshold" register, then the SF defect will be cleared. 593 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 530: Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163) BIT 7 Transmit AIS-P (Downstream) upon J0 Message Unstable BIT 6 Transmit AIS-P (Downstream) Upon Section Trace Message Mismatch R/W 0 BIT 5 Transmit AIS-P (Downstream) upon SF BIT 4 Transmit AIS-P (Downstream) upon SD BIT 3 Unused BIT 2 Transmit AIS-P (Downstream) upon LOF BIT 1 Transmit AIS-P (Downstream) upon LOS BIT 0 Transmit AIS-P (Downstream) Enable 20 0 Rev2...0...0 200 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME Transmit AIS-P (Downstream) upon J0 Message Unstable TYPE R/W DESCRIPTION Transmit Path AIS upon Detection of Unstable Section Trace (J0): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor blocks), anytime it detects an Unstable Section Trace (J0) condition in the "incoming" STS-1 datastream. 0 - Does not configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. 1 - Configures the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable Section Trace" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 6 Transmit AIS-P (Downstream) Upon J0 Message Mismatch R/W Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0) Mismatch: This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor blocks), anytime it detects a Section Trace (J0) Mismatch condition in the "incoming" STS-1 data stream. 0 - Does not configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Mismatch" condition. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects a "Section Trace Mismatch" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Downstream) upon SF R/W Transmit Path AIS upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Receive 594 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block), anytime it declares an SF condition. 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SF detect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Downstream) upon SD R/W Transmit Path AIS upon Signal Degrade (SD): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block) anytime it declares an SD condition. 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the SD defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 2 Unused Transmit AIS-P (Downstream) upon LOF R/O R/W Transmit Path AIS upon Loss of Frame (LOF): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block), anytime it declares an LOF condition. 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOF defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Downstream) upon LOS R/W Transmit Path AIS upon Loss of Signal (LOS): This READ/WRITE bit-field permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-1 POH Processor block), anytime it declares an LOS condition. 595 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 0 - Does not configure the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. 1 - Configures the Receive STS-1 TOH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) anytime it declares the LOS defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 AUTO AIS R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit the Path AIS (AIS-P) indicator, via the down-stream traffic (e.g., towards the Receive STS-1 POH Processor block), upon detection of an SF, SD, Section Trace Mismatch, Section Trace Unstability, LOF or LOS conditions. It also permits the user to configure the Receive STS-1 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS1 POH Processor block) anytime it detects an AIS-L condition in the "incoming" STS-1 datastream. 0 - Configures the Receive STS-1 TOH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of the AIS-L or any of the "above-mentioned" conditions. 1 - Configures the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of the AIS-L or any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this register) to "1" in order to configure the Receive STS-1 TOH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 596 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 531: Receive STS-1 Transport - Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0xN16B) BIT 7 Unused BIT 6 BIT 5 Transmit AISP (via Downstream STS-1s) upon LOS R/O 0 R/W 0 BIT 4 Transmit AISP (via Downstream STS-1s) upon LOF R/W 0 BIT 3 Transmit AISP (via Downstream STS-1s) upon SD R/W 0 BIT 2 Transmit AISP (via Downstream STS-1s) upon SF R/W 0 BIT 1 Unused BIT 0 Transmit AIS-P (via Downstream STS-1s) Enable R/W 0 R/O 0 R/O 0 BIT NUMBER 7-6 5 NAME Unused Transmit AIS-P (via Downstream STS-1s) upon LOS TYPE R/O R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of Signal): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOS defect. 0 - Does not configure the corresponding Transmit SONET POH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOS defect. 1 - Configure the corresponding Transmit SONETPOH Processor blocks to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOS defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 1 (Transmit AIS-P Down-stream - Upon LOS), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor block to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares the LOS defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOS), several SONET frame periods are required (after the Receive STS-1 TOH Processor block has declared the LOS defect), before the corresponding Transmit SONET POH Processor block will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 4 Transmit AIS-P (via Downstream STS-1s) upon LOF R/W Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of Frame): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to 597 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOF defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOF defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the LOF defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 2 (Transmit AIS-P Down-stream - Upon LOF), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares the LOF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOF defect. In the case of Bit 2 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the LOS defect), before the corresponding Transmit SONET POH Processor block will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 3 Transmit AIS-P (via Downstream STS-1s) upon SD R/W Transmit AIS-P (via Downstream STS-1s) upon SD (Signal Degrade): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SD defect. 0 - Does not configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SD defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SD defect. Note: 1. In the "long-run" the function of this bit-field is exactly the same as that of Bit 4 (Transmit AIS-P Down-stream - Upon SD), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares 598 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS the SD defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. In the case of Bit 1 (Transmit AIS-P Downstream - Upon LOF), several SONET frame periods are required (after the Receive STS-1 TOH Processor block has declared the SD defect), before the corresponding Transmit SONET POH Processor block will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 2 Transmit AIS-P (via Downstream STS-1s) upon SF R/W Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF): This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (in the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares an SF condition. 0 - Does not configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SF defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 TOH Processor block declares the SF defect. Note: In the "long-run" the function of this bit-field is exactly the same as that of Bit 5 (Transmit AIS-P Down-stream - Upon SF), within the Receive STS-1 Transport - Auto AIS Control Register (Address Location= 0xN163). The only difference is that this register bit will cause the corresponding "downstream" Transmit SONET POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-1 TOH Processor block declares the SF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the SF defect. In the case of Bit 5 (Transmit AIS-P Downstream - Upon SF), several SONET frame periods are required (after the Receive STS-1 TOH Processor block has declared the SF defect), before the corresponding Transmit SONET POH Processor blocks will begin the process of transmitting the AIS-P indicator. 2. In addition to setting this bit-field to "1", the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. 1 0 Unused Transmit AIS-P (via Downstream STS-1s) Enable R/O R/W Automatic Transmission of AIS-P (via the downstream STS-1s) Enable: This READ/WRITE bit-field permits the user to configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P indicator, via its "outbound" STS-1 signal (within the outbound STS-3 signal), upon detection of an SF, SD, LOS and LOF condition via the Receive STS-1 TOH Processor block. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P indicator, whenever the Receive STS-1 TOH Processor block declares either the LOS, LOF, 599 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS SD or the SF defects. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P indicator, whenever the Receive STS-1 TOH Processor block declares either the LOS, LOF, SD or the SF defects. 20 0 Rev2...0...0 200 600 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 532: Receive STS-1 Path - Control Register - Byte 2 (Address Location= 0xN183) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 Check Stuff R/W 0 BIT 2 RDI-P Type R/W 0 BIT 1 REI-P Error Type R/W 0 BIT 0 B3 Error Type R/W 0 BIT NUMBER 7-4 3 NAME Unused Check Stuff TYPE R/O R/W DESCRIPTION Check (Pointer Adjustment) Stuff Select: This READ/WRITE bit-field permits the user to enable/disable the SONET standard recommendation that a pointer increment or decrement operation, detected within 3 SONET frames of a previous pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. 0 - Disables this SONET standard implementation. In this mode, all pointeradjustment operations that are detected will be accepted. 1 - Enables this "SONET standard" implementation. In this mode, all pointeradjustment operations that are detected within 3 SONET frame periods of a previous pointer-adjustment operation, will be ignored. 2 RDI-P Type R/W Path - Remote Defect Indicator Type Select: This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to support either the "Single-Bit" or the "Enhanced" RDIP, as described below. 0 - Configures the Receive STS-1 POH Processor block to support the Single-Bit RDI-P. In this mode, the Receive STS-1 POH Processor block will only monitor Bit 5, within the G1 byte (of the incoming SPE data), in order to declare and clear the RDI-P indicator. 1 - Configures the Receive STS-1 POH Processor block to support the Enhanced RDI-P (ERDI-P). In this mode, the Receive STS-1 POH Processor block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare and clear the RDI-P indicator. 1 REI-P Error Type R/W REI-P Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Path REI-P Error Count" register is incremented. 0 - Configures the Receive STS-1 POH Processor block to count REI-P Bit Errors. In this case, the "Receive Path REI-P Error Count" register will be incremented by the value of the lower nibble within the G1 byte. 1 - Configures the Receive STS-1 POH Processor block to count REI-P Frame Errors. In this case, the "Receive Path REI-P Error Count" register will be incremented by a single count each time the Receive STS-1 POH Processor block receives a G1 byte, in which bits 1 through 4 are set to a "non-zero" value. 0 B3 Error Type R/W B3 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Path B3 Error Count" register is incremented. 601 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 0 - Configures the Receive STS-1 POH Processor block to count B3 bit errors. In this case, the "Receive Path B3 Error Count" register will be incremented by the number of bits, within the B3 value, that is in error. 1 - Configures the Receive STS-1 POH Processor block to count B3 frame errors. In this case, the "Receive Path B3 Error Count" register will be incremented by the number of erred STS-1 frames. 602 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 533: Receive STS-1 Path - Control Register - Byte 1 (Address Location= 0xN186) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 J1 Unstable Indicator R/O 0 R/O 0 R/O 0 R/W 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-1 0 NAME Unused J1 Unstable Indicator TYPE R/O R/O DESCRIPTION J1 - Path Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the Path Trace Unstable condition. The Receive STS-1 POH Processor block will declare a J1 (Path Trace) Unstable condition, whenever the "J1 Unstable" counter reaches the value "8". The "J0 Unstable" counter will be incremented for each time that it receives a J1 message that differs from the previously received message. The "J1 Unstable" counter is cleared to "0" whenever the Receive STS-1 POH Processor block has received a given J1 Message 3 (or 5) consecutive times. Note: Receiving a given J1 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Path Trace Instability condition is NOT declared. 1 - Path Trace Instability condition is currently declared. 603 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 534: Receive STS-1 Path - SONET Receive POH Status - Byte 0 (Address Location= 0xN187) BIT 7 TIM-P Defect Declared R/O 0 BIT 6 C2 Byte Unstable Condition R/O 0 BIT 5 UNEQ-P Defect Declared R/O 0 BIT 4 PLM-P Defect Declared R/O 0 BIT 3 RDI-P Defect Declared R/O 0 BIT 2 RDI-P Unstable Condition R/O 0 BIT 1 LOP-P Defect Declared R/O 0 BIT 0 AIS-P Defect Declared R/O 0 BIT NUMBER 7 NAME TIM-P Defect Declared TYPE R/O DESCRIPTION Trace Identification Mismatch (TIM-P) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the "Trace Identification Mismatch" condition. The Receive STS-1 POH Processor block will declare the "TIM-P" condition, when none of the received 64 byte string (received via the J1 byte) matches the expected 64 byte message. The Receive STS-1 POH Processor block will clear the "TIM-P" condition, when 80% of the received 64 byte string (received via the J1 byte) matches the expected 64 byte message. 0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the TIM-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the TIM-P condition. 6 C2 Byte Unstable Condition R/O C2 Byte (Path Signal Label Byte) Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the "Path Signal Label Byte" Unstable condition. The Receive STS-1 POH Processor block will declare a C2 (Path Signal Label Byte) Unstable condition, whenever the "C2 Unstable" counter reaches the value "5". The "C2 Unstable" counter will be incremented for each time that it receives an SPE with a C2 byte value that differs from the previously received C2 byte value. The "C2 Unstable" counter is cleared to "0" whenever the Receive STS-1 POH Processor block has received 3 (or 5) consecutive SPEs of the same C2 byte value. Note: Receiving a given C2 byte value in 3 (or 5) consecutive SPEs also sets this bit-field to "0". 0 - C2 (Path Signal Label Byte) Unstable condition is NOT declared. 1 - C2 (Path Signal Label Byte) Unstable condition is currently declared. 5 UNEQ-P R/O Path - Unequipped Indicator (UNEQ-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the UNEQ-P condition. The Receive STS-1 POH Processor block will declare a UNEQ-P condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to 0x00 (which indicates that the SPE is "Unequipped"). The Receive STS-1 POH Processor block will clear the UNEQ-P condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to a value other than 0x00. 0 - Indicates that the Receive STS-1 POH Processor block is NOT declaring the 604 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS UNEQ-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the UNEQ-P condition. Note: The Receive STS-1 POH Processor block will not declare the UNEQ-P condition if it configured to expect to receive STS-1 frames with C2 bytes being set to "0x00" (e.g., if the "Receive STS-1 Path - Expected Path Label Value" Register -Address Location= 0xN197) is set to "0x00". 4 PLM-P Defect Declared R/O Path Payload Mismatch Indicator (PLM-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the PLM-P condition. The Receive STS-1 POH Processor block will declare an PLM-P condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to a value other than that which it is expecting to receive. Whenever the Receive STS-1 POH Processor block is determine whether or not it should declare the PLM-P defect, it checks the contents of the following two registers. * The "Receive STS-1 Path - Received Path Label Value" Register (Address Location= 0xN196). * The "Receive STS-1 Path - Expected Path Label Value" Register (Address Location= 0xN197). The "Receive STS-1 Path - Expected Path Label Value" Register contains the value of the C2 bytes, that the Receive STS-1 POH Processor blocks expects to receive. The "Receive STS-1 Path - Received Path Label Value" Register contains the value of the C2 byte, that the Receive STS-1 POH Processor block has most received "validated" (by receiving this same C2 byte in five consecutive STS-1 frames). The Receive STS-1 POH Processor block will declare a PLM-P condition, if the contents of these two register do not match. The Receive STS-1 POH Processor block will clear the PLM-P condition if whenever the contents of these two registers do match. 0 - PLM-P defect is currently not being declared. 1 - PLM-P defect is currently being declared. Note: The Receive STS-1 POH Processor block will clear the PLM-P defect, upon detecting the UNEQ-P condition. 3 RDI-P R/O Path Remote Defect Indicator (RDI-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the RDI-P condition. If the Receive STS-1 POH Processor block is configured to support the "Single-bit RDI-P" function, then it will declare an RDI-P condition if Bit 5 (within the G1 byte of the incoming STS-1 frame) is set to "1" for "RDI-P_THRD" number of consecutive STS-1 frames. If the Receive STS-1 POH Processor block is configured to support the Enhanced RDI-P" (ERDI-P) function, then it will declare an RDI-P condition if Bits 5, 6 and 7 (within the G1 byte of the incoming STS-1 frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for "RDI-P_THRD" number of consecutive STS-1 frames. 0 - Indicates that the Receive STS-1 POH Processor block is NOT declaring an RDI-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring an RDI-P condition. 605 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Note: 20 0 Rev2...0...0 200 The user can specify the value for "RDI-P_THRD" by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the "Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0xN193). 2 RDI-P Unstable R/O RDI-P (Path - Remote Defect Indicator) Unstable: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the "RDI-P Unstable" condition. The Receive STS-1 POH Processor block will declare a "RDI-P I Unstable" condition whenever the "RDI-P Unstable Counter" reaches the value "RDI-P THRD". The "RDI-P Unstable" counter is incremented for each time that the Receive STS-1 POH Processor block receives an RDI-P value that differs from that of the previous STS-1 frame. The "RDI-P Unstable" counter is cleared to "0" whenever the same RDI-P value is received in "RDI-P_THRD" consecutive STS-1 frames. Note: Receiving a given RDI-P value, in "RDI-P_THRD" consecutive STS-1 frames also clears this bit-field to "0". 0 - RDI-P Unstable condition is NOT declared. 1 - RDI-P Unstable condition is currently declared. Note: The user can specify the value for "RDI-P_THRD" by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the "Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0xN193). 1 LOP-P Defect Declared R/O Loss of Pointer Indicator (LOP-P): This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the LOP (Loss of Pointer) condition. The Receive STS-1 POH Processor block will declare the LOP-P condition, if it cannot detect a valid pointer (H1 and H2 bytes, within the TOH) within 8 to 10 consecutive SONET frames. Further, the Receive STS-1 POH Processor block will declare the LOP-P condition, if it detects 8 to 10 consecutive NDF events. The Receive STS-1 POH Processor block will clear the LOP-P condition, whenever the Receive STS-1 POH Processor detects valid pointer bytes (e.g., the H1 and H2 bytes, within the TOH) and normal NDF value for three consecutive STS-1 frames. 0 - Indicates that the Receive STS-1 POH Processor block is NOT declaring the LOP-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the LOP-P condition. 0 AIS-P R/O Path AIS (AIS-P) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring an AIS-P condition. The Receive STS-1 POH Processor block will declare an AIS-P if it detects all of the following conditions for three consecutive STS-1 frames. * * The H1, H2 and H3 bytes are set to an "All Ones" pattern. The entire SPE is set to an "All Ones" pattern. The Receive STS-1 POH Processor block will clear the AIS-P indicator when it detects a valid STS-1 pointer (H1 and H2 bytes) and a "set" or "normal" NDF for three consecutive STS-1 frames. 0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the AIS-P condition. 1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the AIS-P condition. Note: The Receive STS-1 POH Processor block will NOT declare the LOP-P 606 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS condition if it detects an "All Ones" pattern in the H1, H2 and H3 bytes. It will, instead, declare the AIS-P condition. 607 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 535: Receive STS-1 Path - SONET Receive Path Interrupt Status - Byte 2 (Address Location= 0xN189) BIT 7 BIT 6 Unused BIT 5 BIT 4 Detection of AIS Pointer Interrupt Status R/O 0 RUR 0 BIT 3 Detection of Pointer Change Interrupt Status RUR 0 BIT 2 Unused BIT 1 Change in TIM-P Condition Interrupt Status RUR 0 BIT 0 Change in J1 Unstable Condition Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused Detection of AIS Pointer Interrupt Status TYPE R/O RUR DESCRIPTION Detection of AIS Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of AIS Pointer" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate this interrupt anytime it detects an "AIS Pointer" in the incoming STS-1 data stream. Note: An "AIS Pointer" is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an "All Ones" pattern. 0 - Indicates that the "Detection of AIS Pointer" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of AIS Pointer" interrupt has occurred since the last read of this register. 3 Detection of Pointer Change Interrupt Status RUR Detection of Pointer Change Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Change" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it accepts a new pointer value (e.g., H1 and H2 bytes, in the TOH bytes). 0 - Indicates that the "Detection of Pointer Change" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Change" Interrupt has occurred since the last read of this register. 2 1 Unused Change in TIM-P Condition Interrupt Status R/O RUR Change in TIM-P (Trace Identification Mismatch) Condition Interrupt. This RESET-upon-READ bit-field indicates whether or not the "Change in TIM-P" Condition interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. 608 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS * If the TIM-P condition is declared. * If the TIM-P condition is cleared. 0 - Indicates that the "Change in TIM-P Condition" Interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in TIM-P Condition" Interrupt has occurred since the last read of this register. 0 Change in J1 Unstable Condition Interrupt Status RUR Change in "J1 (Trace Identification Message) Unstable Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J1 Unstable Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declare the "J1 Unstable" Condition. * When the Receive STS-1 POH Processor block clears the "J1 Unstable" condition. 0 - Indicates that the "Change in J1 Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in J1 Unstable Condition" Interrupt has occurred since the last read of this register. 609 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 536: Receive STS-1 Path - SONET Receive Path Interrupt Status - Byte 1 (Address Location= 0xN18A) BIT 7 New J1 Message Interrupt Status BIT 6 Detection of REI-P Event Interrupt Status BIT 5 Change in UNEQ-P Condition Interrupt Status RUR 0 BIT 4 Change in PLM-P Condition Interrupt Status RUR 0 BIT 3 New C2 Byte Interrupt Status BIT 2 Change in C2 Byte Unstable Condition Interrupt Status RUR 0 BIT 1 Change in RDI-P Unstable Condition Interrupt Status RUR 0 BIT 0 New RDI-P Value Interrupt Status RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7 NAME New J1 Message Interrupt Status TYPE RUR DESCRIPTION New J1 (Trace Identification) Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New J1 Message" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted (or validated) and new J1 (Trace Identification) Message. 0 - Indicates that the "New J1 Message" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New J1 Message" Interrupt has occurred since the last read of this register. 6 Detection of REI-P Event Interrupt Status RUR Detection of REI-P Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of REI-P Event" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an REI-P condition in the coming STS-1 data-stream. 0 - Indicates that the "Detection of REI-P Event" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of REI-P Event" Interrupt has occurred since the last read of this register. 5 Change in UNEQ-P Condition Interrupt Status RUR Change in UNEQ-P (Path - Unequipped) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in UNEQ-P Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the UNEQ-P Condition. * When the Receive STS-1 POH Processor block clears the UNEQ-P Condition. 0 - Indicates that the "Change in UNEQ-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in UNEQ-P Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of UNEQ-P by reading 610 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS out the state of Bit 5 (UNEQ-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 4 Change in PLMP Condition Interrupt Status RUR Change in PLM-P (Path - Payload Mismatch) Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the "Change in PLM-P Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the "PLM-P" Condition. * When the Receive STS-1 POH Processor block clears the "PLM-P" Condition. 0 - Indicates that the "Change in PLM-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in PLM-P Condition" Interrupt has occurred since the last read of this register. 3 New C2 Byte Interrupt Status RUR New C2 Byte Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New C2 Byte" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 - Indicates that the "New C2 Byte" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New C2 Byte" Interrupt has occurred since the last read of this register. 2 Change in C2 Byte Unstable Condition Interrupt Status RUR Change in C2 Byte Unstable Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in C2 Byte Unstable Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares the "C2 Byte Unstable" condition. * When the Receive STS-1 POH Processor block clears the "C2 Byte Unstable" condition. 0 - Indicates that the "Change in C2 Byte Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in C2 Byte Unstable Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of "C2 Byte Unstable Condition" by reading out the state of Bit 6 (C2 Byte Unstable Condition) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 1 Change in RDIP Unstable Condition Interrupt Status RUR Change in RDI-P Unstable Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in RDI-P Unstable Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will 611 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares an "RDI-P Unstable" condition. * When the Receive STS-1 POH Processor block clears the "RDI-P Unstable" condition. 0 - Indicates that the "Change in RDI-P Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in RDI-P Unstable Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of "RDI-P Unstable" by reading out the state of Bit 2 (RDI-P Unstable Condition) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 0 New RDI-P Value Interrupt Status RUR New RDI-P Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New RDI-P Value" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate this interrupt anytime it receives and "validates" a new RDI-P value. 0 - Indicates that the "New RDI-P Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New RDI-P Value" Interrupt has occurred since the last read of this register. Note: The user can obtain the "New RDI-P Value" by reading out the contents of the "RDI-P ACCEPT[2:0]" bit-fields. These bit-fields are located in Bits 6 through 4, within the "Receive STS-1 Path - SONET Receive RDI-P Register" (Address Location= 0xN193). 612 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 537: Receive STS-1 Path - SONET Receive Path Interrupt Status - Byte 0 (Address Location= 0xN18B) BIT 7 Detection of B3 Byte Error Interrupt Status RUR 0 BIT 6 Detection of New Pointer Interrupt Status RUR 0 BIT 5 Detection of Unknown Pointer Interrupt Status RUR 0 BIT 4 Detection of Pointer Decrement Interrupt Status RUR 0 BIT 3 Detection of Pointer Increment Interrupt Status RUR 0 BIT 2 Detection of NDF Pointer Interrupt Status RUR 0 BIT 1 Change of LOP-P Condition Interrupt Status RUR 0 BIT 0 Change of AIS-P Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Detection of B3 Byte Error Interrupt Status TYPE RUR DESCRIPTION Detection of B3 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B3 Byte Error" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a B3 byte error in the incoming STS-1 data stream. 0 - Indicates that the "Detection of B3 Byte Error" Interrupt has NOT occurred since the last read of this interrupt. 1 - Indicates that the "Detection of B3 Byte Error" Interrupt has occurred since the last read of this interrupt. 6 Detection of New Pointer Interrupt Status RUR Detection of New Pointer Interrupt Status: This RESET-upon-READ indicates whether the "Detection of New Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-1 frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 - Indicates that the "Detection of New Pointer" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of New Pointer" Interrupt has occurred since the last read of this register. 5 Detection of Unknown Pointer Interrupt Status RUR Detection of Unknown Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Unknown Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime that it detects a "pointer" that does not fit into any of the following categories. * An Increment Pointer * A Decrement Pointer * An NDF Pointer * An AIS (e.g., All Ones) Pointer * New Pointer 0 - Indicates that the "Detection of Unknown Pointer" interrupt has NOT 613 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS occurred since the last read of this register. 1 - Indicates that the "Detection of Unknown Pointer" interrupt has occurred since the last read of this register. 4 Detection of Pointer Decrement Interrupt Status RUR Detection of Pointer Decrement Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Decrement" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Decrement" event. 0 - Indicates that the "Detection of Pointer Decrement" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Decrement" interrupt has occurred since the last read of this register. 3 Detection of Pointer Increment Interrupt Status RUR Detection of Pointer Increment Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Increment" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Increment" event. 0 - Indicates that the "Detection of Pointer Increment" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Increment" interrupt has occurred since the last read of this register. 2 Detection of NDF Pointer Interrupt Status RUR Detection of NDF Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of NDF Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 - Indicates that the "Detection of NDF Pointer" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of NDF Pointer" interrupt has occurred since the last read of this register. 1 Change of LOP-P Condition Interrupt Status RUR Change of LOP-P Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in LOP-P Condition" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * * 20 0 Rev2...0...0 200 When the Receive STS-1 POH Processor block declares an "Loss of Pointer" condition. When the Receive "STS-1 POH Processor" block clears the "Loss of Pointer" condition. 0 - Indicates that the "Change in LOP-P Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in LOP-P Condition" interrupt has 614 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS occurred since the last read of this register. Note: The user can determine the current state of LOP-P by reading out the state of Bit 1 (LOP-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location=0xN187). 0 Change of AIS-P Condition Interrupt Status RUR Change of AIS-P Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-P Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares an AIS-P condition. * When the Receive STS-1 POH Processor block clears the AIS-P condition. 0 - Indicates that the "Change of AIS-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of AIS-P Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of AIS-P by reading out the state of Bit 0 (AIS-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" Register (Address Location= 0xN187). 615 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 538: Receive STS-1 Path - SONET Receive Path Interrupt Enable - Byte 2 (Address Location = 0xN18D) BIT 7 BIT 6 Unused BIT 5 BIT 4 Detection of AIS Pointer Interrupt Enable R/O 0 R/W 0 BIT 3 Detection of Pointer Change Interrupt Enable R/W 0 BIT 2 Unused BIT 1 Change in TIM-P Condition Interrupt Enable R/W 0 BIT 0 Change in J1 Unstable Condition Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused Detection of AIS Pointer Interrupt Enable TYPE R/O R/W DESCRIPTION Detection of AIS Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of AIS Pointer" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an "AIS Pointer", in the incoming STS-1 data stream. Note: An "AIS Pointer" is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an "All Ones" Pattern. 0 - Disables the "Detection of AIS Pointer" Interrupt. 1 - Enables the "Detection of AIS Pointer" Interrupt. 3 Detection of Pointer Change Interrupt Enable R/W Detection of Pointer Change Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Pointer Change" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted a new pointer value. 0 - Disables the "Detection of Pointer Change" Interrupt. 1 - Enables the "Detection of Pointer Change" Interrupt. 2 1 Unused Change in TIM-P Condition Interrupt Enable R/O R/W Change in TIM-P (Trace Identification Mismatch) Condition Interrupt: This READ/WRITE bit-field permits the user to either enable or disable the "Change in TIM-P Condition" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * If the TIM-P condition is declared. * If the TIM-P condition is cleared. 0 - Disables the "Change in TIM-P Condition" Interrupt. 1 - Enables the "Change in TIM-P Condition" Interrupt. 0 Change in J1 Unstable Condition Interrupt R/W Change in "J1 (Trace Identification Condition" Interrupt Status: Message) Unstable 616 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Enable Condition" Interrupt Status: This READ/WRITE bit-field permits the user to either enable or disable the "Change in J1 (Trace Identification) Message Unstable Condition" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares the "J1 Unstable" Condition. * When the Receive STS-1 POH Processor block clears the "J1 Unstable" Condition. 0 - Disables the "Change in J1 Message Unstable Condition" interrupt. 1 - Enables the "Change in J1 Message Unstable Condition" interrupt. 617 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 539: Receive STS-1 Path - SONET Receive Path Interrupt Enable - Byte 1 (Address Location= 0xN18E) BIT 7 New J1 Message Interrupt Enable BIT 6 Detection of REI-P Event Interrupt Enable BIT 5 Change in UNEQ-P Condition Interrupt Enable R/W 0 BIT 4 Change in PLM-P Condition Interrupt Enable R/W 0 BIT 3 New C2 Byte Interrupt Enable BIT 2 Change in C2 Byte Unstable Condition Interrupt Enable R/W 0 BIT 1 Change in RDI-P Unstable Condition Interrupt Enable R/W 0 BIT 0 New RDI-P Value Interrupt Enable R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME New J1 Message Interrupt Enable TYPE R/W DESCRIPTION New J1 (Trace Identification) Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New J1 Message" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted (or validated) and new J1 (Trace Identification) Message. 0 - Disables the "New J1 Message" Interrupt. 1 - Enables the "New J1 Message" Interrupt. 6 Detection of REI-P Event Interrupt Enable R/W Detection of REI-P Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of REI-P Event" Interrupt. If this interrupt is enabled, then he Receive STS-1 POH Processor block will generate an interrupt anytime it detects an REI-P condition in the coming STS-1 data-stream. 0 - Disables the "Detection of REI-P Event" Interrupt. 1 - Enables the "Detection of REI-P Event" Interrupt. 5 Change in UNEQ-P Condition Interrupt Enable R/W Change in UNEQ-P (Path - Unequipped) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in UNEQ-P Condition" interrupt. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the UNEQP Condition. * When the Receive STS-1 POH Processor block clears the UNEQ-P Condition. 0 - Disables the "Change in UNEQ-P Condition" Interrupt. 1 - Enables the "Change in UNEQ-P Condition" Interrupt. 4 Change in PLM-P Condition Interrupt Enable R/W Change in PLM-P (Path - Payload Mismatch) Condition Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the "Change in PLM-P Condition" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor 618 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares the "PLMP" Condition. * When the Receive STS-1 POH Processor block clears the "PLM-P" Condition. 0 - Disables the "Change in PLM-P Condition" Interrupt. 1 - Enables the "Change in PLM-P Condition" Interrupt. 3 New C2 Byte Interrupt Enable R/W New C2 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New C2 Byte" Interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 - Disables the "New C2 Byte" Interrupt. 1 - Enables the "New C2 Byte" Interrupt. Note: The user can obtain the value of this "New C2" byte by reading the contents of the "Receive STS-1 Path - Received Path Label Value" Register (Address Location= 0xN196). 2 Change in C2 Byte Unstable Condition Interrupt Enable R/W Change in C2 Byte Unstable Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in C2 Byte Unstable Condition" Interrupt. If this interrupt is enabled , then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-1 POH Processor block declares the "C2 Byte Unstable" condition. * When the Receive STS-1 POH Processor block clears the "C2 Byte Unstable" condition. 0 - Disables the "Change in C2 Byte Unstable Condition" Interrupt. 1 - Enables the "Change in C2 Byte Unstable Condition" Interrupt. 1 Change in RDI-P Unstable Condition Interrupt Enable R/W Change in RDI-P Unstable Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in RDI-P Unstable Condition" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-1 POH Processor block declares an "RDI-P Unstable" condition. * When the Receive STS-1 POH Processor block clears the "RDI-P Unstable" condition. 0 - Disables the "Change in RDI-P Unstable Condition" Interrupt. 1 - Enables the "Change in RDI-P Unstable Condition" Interrupt. 0 New RDI-P Value Interrupt Enable R/W New RDI-P Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New RDI-P Value" interrupt. If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate this interrupt anytime it receives and "validates" a 619 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS new RDI-P value. 0 - Disables the "New RDI-P Value" Interrupt. 1 - Enable the "New RDI-P Value" Interrupt. 20 0 Rev2...0...0 200 620 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 540: Receive STS-1 Path - SONET Receive Path Interrupt Enable - Byte 0 (Address Location= 0xN18F) BIT 7 Detection of B3 Byte Error Interrupt Enable R/W 0 BIT NUMBER 7 BIT 6 Detection of New Pointer Interrupt Enable R/W 0 NAME Detection of B3 Byte Error Interrupt Enable TYPE R/W BIT 5 Detection of Unknown Pointer Interrupt Enable R/W 0 BIT 4 Detection of Pointer Decrement Interrupt Enable R/W 0 BIT 3 Detection of Pointer Increment Interrupt Enable R/W 0 BIT 2 Detection of NDF Pointer Interrupt Enable R/W 0 DESCRIPTION Detection of B3 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B3 Byte Error" Interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a B3-byte error in the incoming STS-1 data-stream. 0 - Disables the "Detection of B3 Byte Error" interrupt. 1 - Enables the "Detection of B3 Byte Error" interrupt. 6 Detection of New Pointer Interrupt Enable R/W Detection of New Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of New Pointer" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-1 frame. Note: Pointer Adjustments with NDF will not generate this interrupt. BIT 1 Change of LOP-P Condition Interrupt Enable R/W 0 BIT 0 Change of AIS-P Condition Interrupt Enable R/W 0 0 - Disables the "Detection of New Pointer" Interrupt. 1 - Enables the "Detection of New Pointer" Interrupt. 5 Detection of Unknown Pointer Interrupt Enable R/W Detection of Unknown Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Unknown Pointer" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Adjustment" that does not fit into any of the following categories. * An Increment Pointer. * A Decrement Pointer * An NDF Pointer * AIS Pointer * New Pointer. 0 - Disables the "Detection of Unknown Pointer" Interrupt. 1 - Enables the "Detection of Unknown Pointer" Interrupt. 4 Detection of Pointer Decrement Interrupt Enable R/W Detection of Pointer Decrement Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "Detection of Pointer Decrement" Interrupt. If the user enables this interrupt, then the Receive STS-1 TOH Processor block will generate an interrupt anytime it detects a "Pointer-Decrement" event. 0 - Disables the "Detection of Pointer Decrement" Interrupt. 621 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Enables the "Detection of Pointer Decrement" Interrupt. 3 Detection of Pointer Increment Interrupt Enable R/W Detection of Pointer Increment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Pointer Increment" Interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a "Pointer Increment" event. 0 - Disables the "Detection of Pointer Increment" Interrupt. 1 - Enables the "Detection of Pointer Increment" Interrupt. 2 Detection of NDF Pointer Interrupt Enable R/W Detection of NDF Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of NDF Pointer" Interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 - Disables the "Detection of NDF Pointer" interrupt. 1 - Enables the "Detection of NDF Pointer" interrupt. 1 Change of LOP-P Condition Interrupt Enable R/W Change of LOP-P Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOP (Loss of Pointer)" Condition interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * * 20 0 Rev2...0...0 200 When the Receive STS-1 POH Processor block declares a "Loss of Pointer" condition. When the Receive STS-1 POH Processor block clears the "Loss of Pointer" condition. 0 - Disable the "Change of LOP" Interrupt. 1 - Enables the "Change of LOP" Interrupt. Note: The user can determine the current state of "LOP" by reading out the contents of Bit 1 (LOP) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" (Address Location= 0xN187). 0 Change of AIS-P Interrupt Enable R/W Change of AIS-P Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-P (Path AIS)" interrupt. If the user enables this interrupt, then the Receive STS-1 POH Processor block will generate an interrupt in response to either of the following events. * * When the Receive STS-1 POH Processor block declares an "AIS-P" condition. When the Receive STS-1 POH Processor block clears the "AIS-P" condition. 0 - Disables the "Change of AIS-P" Interrupt. 1 - Enables the "Change of AIS-P" Interrupt. Note: The user can determine the current state of "AIS-P" by reading out the contents of Bit 0 (AIS-P Defect Declared) within the "Receive STS-1 Path - SONET Receive POH Status - Byte 0" (Address Location= 0xN187). Table 541: Receive STS-1 Path - SONET Receive RDI-P Register (Address Location= 0xN193) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 622 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RDI-P_ACCEPT[2:0] R/O 0 R/O 0 R/O 0 R/W 0 RDI-P THRESHOLD[3:0] R/W 0 R/W 0 R/W 0 Unused R/O 0 BIT NUMBER 7 6-4 NAME Unused RDI-P_ACCEPT[2:0] TYPE R/O R/O Accepted RDI-P Value: DESCRIPTION These READ-ONLY bit-fields contain the value of the most recently "accepted" RDI-P (e.g., bits 5, 6 and 7 within the G1 byte) value. Note: A given RDI-P value will be "accepted" by the Receive STS-1 POH Processor block, if this RDI-P value has been consistently received in "RDI-P THRESHOLD[3:0]" number of STS-1 frames. 3-0 RDI-P THRESHOLD[3:0] R/W RDI-P Threshold: These READ/WRITE bit-fields permit the user to defined the "RDI-P Acceptance Threshold" for the Receive STS-1 POH Processor Block. The "RDI-P Acceptance Threshold" is the number of consecutive STS-1 frames, in which the Receive STS-1 POH Processor block must receive a given RDI-P value, before it "accepts" or "validates" it. The most recently "accepted" RDI-P value is written into the "RDI-P ACCEPT[2:0]" bit-fields, within this register. 623 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 542: Receive STS-1 Path - Received Path Label Value (Address Location= 0xN196) BIT 7 R/O 1 BIT 6 R/O 1 BIT 5 R/O 1 BIT 4 R/O 1 BIT 3 R/O 1 BIT 2 R/O 1 BIT 1 R/O 1 BIT 0 R/O 1 20 0 Rev2...0...0 200 Received_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Received C2 Byte Value[7:0] TYPE R/O DESCRIPTION Received "Filtered" C2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently "accepted" C2 byte, via the Receive STS-1 POH Processor block. The Receive STS-1 POH Processor block will "accept" a C2 byte value (and load it into these bit-fields) if it has received a consistent C2 byte, in five (5) consecutive STS-1 frames. Note: The Receive STS-1 POH Processor block uses this register, along the "Receive STS-1 Path - Expected Path Label Value" Register (Address Location = 0xN197), when declaring or clearing the UNEQ-P and PLM-P alarm conditions. Table 543: Receive STS-1 Path - Expected Path Label Value (Address Location= 0xN197) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 Expected_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Expected C2 Byte Value[7:0] TYPE R/W DESCRIPTION Expected C2 Byte Value: These READ/WRITE bit-fields permits the user to specify the C2 (Path Label Byte) value, that the Receive STS-1 POH Processor block should expect when declaring or clearing the UNEQ-P and PLM-P alarm conditions. If the contents of the "Received C2 Byte Value[7:0]" (see "Receive STS-1 Path - Received Path Label Value" register) matches the contents in these register, then the Receive STS1 POH will not declare any alarm conditions. 624 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 544: Receive STS-1 Path - B3 Error Count Register - Byte 3 (Address Location= 0xN198) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[31:24] BIT NUMBER 7-0 NAME B3_Error_Count[31:24] TYPE RUR B3 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 545: Receive STS-1 Path - B3 Error Count Register - Byte 2 (Address Location= 0xN199) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[23:16] BIT NUMBER 7-0 NAME B3_Error_Count[23:16] TYPE RUR DESCRIPTION B3 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. 625 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 546: Receive STS-1 Path - B3 Error Count Register - Byte 1 (Address Location= 0xN19A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[15:8] BIT NUMBER 7-0 NAME B3_Error_Count[15:8] TYPE RUR DESCRIPTION B3 Error Count - (Bits 15 through 8): This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 547: Receive STS-1 Path - B3 Error Count Register - Byte 0 (Address Location= 0xN19B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[7:0] BIT NUMBER 7-0 NAME B3_Error_Count[7:0] TYPE RUR B3 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Path - B3 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a B3 byte error. Note: 1. If the B3 Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. 2. If the B3 Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. 626 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 548: Receive STS-1 Path - REI-P Error Count Register - Byte 3 (Address Location= 0xN19C) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[31:24] BIT NUMBER 7-0 NAME REI_P_Error_Count[31:24] TYPE RUR DESCRIPTION REI-P Error Count - MSB: This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. Table 549: Receive STS-1 Path - REI_P Error Count Register - Byte 2 (Address Location= 0xN19D) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[23:16] BIT NUMBER 7-0 NAME REI_P_Error_Count[23:16] TYPE RUR DESCRIPTION REI-P Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS1 POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. 627 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 550: Receive STS-1 Path - REI_P Error Count Register - Byte 1 (Address Location= 0xN19E) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[15:8] BIT NUMBER 7-0 NAME REI_P_Error_Count[15:8] TYPE RUR DESCRIPTION REI-P Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a Path -Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. Table 551: Receive STS-1 Path - REI_P Error Count Register - Byte 0 (Address Location= 0xN19F) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_P_Error_Count[7:0] TYPE RUR REI-P Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-1 Path - REI-P Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-1 POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-1 POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. 628 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 552: Receive STS-1 Path - Receive J1 Control Register (Address Location= 0xN1A3) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 Receive J1 Message Buffer Read Select R/W 0 BIT 3 Accept Threshold R/W 0 BIT 2 Message Type R/W 0 BIT 1 BIT 0 Message Length[1:0] R/W 0 R/W 0 BIT NUMBER 7-5 4 NAME Unused Received J1 Message Buffer Read Select TYPE R/O R/W J1 Buffer Read Selection: DESCRIPTION This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. c. d. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Receive STS-1 POH Processor block, the "Receive J1 Trace Buffer" is located at Address Location 0xN500 through 0xN53F. 3 Accept Threshold R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-1 POH Processor block must receive a given J1 Trace Message, before it is accepted, as described below. 0 - The Receive STS-1 POH Processor block accepts the J1 Message after it has received it the third time in succession. 1 - The Receive SONET POH Processor block accepts the J1 Message after it has received in the fifth time in succession. 2 Message Type R/O Message Alignment Type: This READ/WRITE bit-field permits a user to specify have the Receive STS-1 POH Processor block will locate the boundary of the J1 Trace Message, as indicated below. 0 - Message boundary is indicated by "Line Feed". 1 - Message boundary is indicated by the presence of a "1" in the MSB of a the first byte (within the J1 Trace Message). 1-0 Message Length[1:0] R/W J1 Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the J1 Trace Message, that the Receive STS-1 POH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J1 Trace Message Length is presented below. MSG LENGTH 00 Resulting J1 Trace Message Length 1 Byte 629 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 01 10/11 16 Bytes 64 Bytes 20 0 Rev2...0...0 200 630 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 553: Receive STS-1 Path - Pointer Value - Byte 1 (Address Location= 0xN1A6) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Current_Pointer Value MSB[9:8] R/O 0 R/O 0 BIT NUMBER 7-2 1-0 NAME Unused Current_Pointer_Value_MSB[7:0] TYPE R/O R/O DESCRIPTION Current Pointer Value - MSB: These READ-ONLY bit-fields, along with that from the "Receive STS-1 Path - Pointer Value - Byte 0" Register combine to reflect the current value of the pointer that the "Receive STS-1 POH Processor" block is using to locate the SPE within the incoming STS-1 data stream. Note: These register bits comprise the Upper Byte value of the Pointer Value. Table 554: Receive STS-1 Path - Pointer Value - Byte 0 (Address Location= 0xN1A7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Current_Pointer_Value_LSB[7:0] BIT NUMBER 7-0 NAME Current_Pointer_Value_LSB[7:0] TYPE R/O DESCRIPTION Current Pointer Value - LSB: These READ-ONLY bit-fields, along with that from the "Receive STS-1 Path - Pointer Value - Byte 1" Register combine to reflect the current value of the pointer that the "Receive STS-1 POH Processor" block is using to locate the SPE within the incoming STS-1 data stream. Note: These register bits comprise the Lower Byte value of the Pointer Value. 631 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 555: Receive STS-1 Path - AUTO AIS Control Register (Address Location= 0xN1BB) BIT 7 Unused BIT 6 Transmit AIS-P (Downstream) Upon C2 Byte Unstable R/W 0 BIT 5 Transmit AIS-P (Downstream) Upon UNEQ-P R/W 0 BIT 4 Transmit AIS-P (Downstream) Upon PLMP R/W 0 BIT 3 Transmit AIS-P (Downstream) Upon J1 Message Unstable R/W 0 BIT 2 Transmit AIS-P (Downstream) upon TIM-P R/W 0 BIT 1 Transmit AIS-P (Downstream) upon LOP-P BIT 0 Transmit AIS-P (Downstream) Enable 20 0 Rev2...0...0 200 R/O 0 R/W 0 R/W 0 BIT NUMBER 7 6 NAME Unused Transmit AIS-P (Downstream) upon C2 Byte Unstable TYPE R/O R/W DESCRIPTION Transmit Path AIS upon Detection of Unstable C2 Byte: This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it detects an Unstable C2 Byte condition in the "incoming" STS-1 data-stream. 0 - Does not configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable C2 Byte" condition. 1 - Configures the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable C2 Byte" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Downstream) upon UNEQ-P R/W Transmit Path AIS upon Detection of Path-Unequipped Defect (UNEQ-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares an UNEQ-P condition. 0 - Does not configure the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the UNEQ-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the UNEQ-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Downstream) upon PLM-P R/W Transmit Path AIS upon Detection of Path-Payload Label Mismatch Defect (PLM-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS 632 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares an PLM-P condition. 0 - Does not configure the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the PLM-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the PLM-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 Transmit AIS-P (Downstream) upon J1 Message Unstable R/W Transmit Path AIS upon Detection of Unstable 1 Message: This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it detects an Unstable J1 Message condition in the "incoming" STS-1 data-stream. 0 - Does not configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable J1 Message" condition. 1 - Configures the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable J1 Message" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 2 Transmit AIS-P (Downstream) upon TIM-P R/W Transmit Path AIS upon Detection of Path-Trace Identification Message Mismatch Defect (TIM-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares a TIMP condition. 0 - Does not configure the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the TIM-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the TIM-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Downstream) upon LOP-P R/W Transmit Path AIS upon Detection of Loss of Pointer (LOP-P): This READ/WRITE bit-field permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks), anytime it declares an LOP-P condition. 0 - Does not configure the Receive STS-1 POH Processor block to 633 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOP-P defect. 1 - Configures the Receive STS-1 POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOP-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 Transmit AIS-P (Downstream) Enable R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-1 POH Processor block to automatically transmit the Path AIS indicator, via the downstream traffic (e.g., towards the Transmit SONET POH Processor blocks), upon detection of an UNEQ-P, PLM-P, LOP-P or LOS conditions. It also permits the user to configure the Receive STS-1 POH Processor block to automatically transmit a Path (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Transmit SONET POH Processor blocks) anytime it detects an AIS-P condition in the "incoming " STS-1 data-stream. 0 - Configures the Receive STS-1 POH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" conditions. 1 - Configures the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this register) to "1" in order to configure the Receive STS-1 POH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 634 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 556: Receive STS-1 Path - SONET Receive Auto Alarm Register - Byte 0 (Address Location= 0xN1C3) BIT 7 Unused BIT 6 Transmit AIS-P (via Downstream STS-1s) upon LOP-P R/W 0 BIT 5 Transmit AIS-P (via Downstream STS-1s) upon PLM-P R/W 0 BIT 4 Transmit AIS-P (via Downstream STS-1s) upon LCD-P R/W 0 BIT 3 Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P R/W 0 BIT 2 Transmit AIS-P (via Downstream STS-1s) upon TIM-P R/W 0 BIT 1 Transmit AIS-P (via Downstream STS-1s) upon AIS-P R/W 0 BIT 0 Transmit DS3 AIS (via Downstream DS3) upon PDI-P R/W 0 R/O 0 BIT NUMBER 7 6 NAME Unused Transmit AIS-P (via Downstream STS-1s) upon LOP-P TYPE R/O R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon LOP-P This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the LOP-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the LOP-P defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the LOP-P defect. 5 Transmit AIS-P (via Downstream STS-1s) upon PLM-P R/W Transmit AIS-P (via Downstream STS-1s) upon PLM-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive STS-1 POH Processor block declares the PLM-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the PLM-P defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the PLM-P defect. 4 Transmit AIS-P (via Downstream STS-1s) upon LCD-P R/W Transmit AIS-P (via Downstream STS-1s) upon LCD-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive SONET POH 635 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Processor block declares the LCD-P defect. 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive SONET POH Processor block declares the LCD-P defect. 1 - Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive SONET POH Processor block declares the LCD-P defect. 3 Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P R/W Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, (within the outbound STS-3 signal) anytime the Receive STS-1 POH Processor block declares the UNEQP defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the UNEQP defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the UNEQP defect. 2 Transmit AIS-P (via Downstream STS-1s) upon TIM-P R/W Transmit AIS-P (via Downstream STS-1s) upon TIM-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the TIM-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the TIM-P defect. 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the TIM-P defect. 1 Transmit AIS-P (via Downstream STS-1s) upon AIS-P R/W Transmit AIS-P (via Downstream STS-1s) upon AIS-P: This READ/WRITE bit-field permits the user to configure the Transmit SONET POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the AIS-P defect. 0 - Does not configure the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal (within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the AIS-P defect. 20 0 Rev2...0...0 200 636 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Configures the corresponding Transmit SONET POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal A(within the outbound STS-3 signal), anytime the Receive STS-1 POH Processor block declares the AIS-P defect. 0 Unused R/O 637 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 557: Receive STS-1 Path - Receive J1 Byte Capture Register (Address Location= 0xN1D3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 J1_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME J1_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION J1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the J1 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new J1 byte value. Table 558: Receive STS-1 Path - Receive B3 Byte Capture Register (Address Location= 0xN1D7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 B3_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME B3_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION B3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the B3 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new B3 byte value. 638 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 559: Receive STS-1 Path - Receive C2 Byte Capture Register (Address Location= 0xN1DB) BIT 7 R/O 0 BIT NUMBER 7-0 BIT 6 R/O 0 NAME C2_Byte_Captured_Value[7:0] BIT 5 R/O 0 BIT 4 R/O 0 TYPE R/O BIT 3 R/O 0 BIT 2 R/O 0 DESCRIPTION C2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the C2 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new C2 byte value. BIT 1 R/O 0 BIT 0 R/O 0 C2_Byte_Captured_Value[7:0] Table 560: Receive STS-1 Path - Receive G1 Byte Capture Register (Address Location= 0xN1DF) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 G1_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME G1_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION G1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the G1 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new G1 byte value. 639 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 561: Receive STS-1 Path - Receive F2 Byte Capture Register (Address Location=0xN1E3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 F2_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME F2_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION F2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the F2 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new F2 byte value. Table 562: Receive STS-1 Path - Receive H4 Byte Capture Register (Address Location= 0xN1E7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 H4_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME H4_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION H4 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the H4 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new H4 byte value. 640 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 563: Receive STS-1 Path - Receive Z3 Byte Capture Register (Address Location= 0xN1EB) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z3_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z3_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z3 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new Z3 byte value. Table 564: Receive STS-1 Path - Receive Z4 (K3) Byte Capture Register (Address Location= 0xN1EF) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z4(K3)_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z4(K3)_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z4 (K3) Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z4 (K3) byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new Z4 (K3) byte value. 641 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 565: Receive STS-1 Path - Receive Z5 Byte Capture Register (Address Location= 0xN1F3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z5_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z5_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z5 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z5 byte, within the most recently received STS-1 frame. This particular value is stored in this register for one STS-1 frame period. During the next STS-1 frame period, this value will be overridden with a new Z5 byte value. 1.12 DS3/E3 FRAMER BLOCK 642 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS The register map for the DS3/E3 Framer Block is presented in the Table below. Additionally, a detailed description of each of the "DS3/E3 Framer" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "DS3/E3 Framer Block "highlighted" is presented below in Figure 13. Figure 13: Illustration of the Functional Block Diagram of the XRT94L33, with the DS3/E3 Framer Block "High-lighted From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 643 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.12.1 DS3/E3 FRAMER BLOCK REGISTER 20 0 Rev2...0...0 200 Table 566: DS3/E3 Framer Block Control Register Map INDIVIDUAL REGISTER ADDRESS 0x00 0x01 0x02 - 0x03 0x04 0x05 0x06 - 0x0B 0x0C 0x0D - 0x0F 0x10 ADDRESS LOCATION 0xN300 0xN301 0xN302, 0xN303 0xN304 0xN305 0xN306 - 0xN30B 0xN30C 0xN30D - 0xN30F 0xN310 Operating Mode Register I/O Control Register Reserved Block Interrupt Enable Register Block Interrupt Status Register Reserved Test Register Reserved RxDS3 Configuration and Status Register RxE3 Configuration and Status Register # 1 - G.832 RxE3 Configuration and Status Register # 1 - G.751 0x11 0xN311 RxDS3 Status Register RxE3 Configuration and Status Register # 2 - G.832 RxE3 Configuration and Status Register # 2 - G.751 0x12 0xN312 RxDS3 Interrupt Enable Register RxE3 Interrupt Enable Register # 1 - G.832 RxE3 Interrupt Enable Register # 1 - G.751 0x13 0xN313 RxDS3 Interrupt Status Register RxE3 Interrupt Enable Register # 2 - G.832 RxE3 Interrupt Enable Register # 2 - G.751 0x14 0xN314 RxDS3 Sync Detect Enable Register RxE3 Interrupt Status Register # 1 - G.832 RxE3 Interrupt Status Register # 1 - G.751 0x15 0xN315 RxE3 Interrupt Status Register # 2 - G.832 RxE3 Interrupt Status Register # 2 - G.751 0x16 0x17 0x18 0xN316 0xN317 0xN318 RxDS3 FEAC Register RxDS3 FEAC Interrupt Enable/Status Register RxDS3 LAPD Control Register RxE3 LAPD Control Register 0x19 0xN319 RxDS3 LAPD Status Register 0x00 0x7E 0x00 0x00 0x00 0x00 0x00 0x00 0x67 REGISTER NAME DEFAULT VALUES 0x23 0xA0 0x00 0x00 0x00 0x00 0x00 0x00 0x02 644 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS RxE3 LAPD Status Register 0x1A 0xN31A RxE3 NR Byte Register - G.832 RxE3 Service Bit Register - G.751 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D - 0x2E 0x2F 0x30 0xN31B 0xN31C 0xN31D 0xN31E 0xN31F 0xN320 0xN321 0xN322 0xN323 0xN324 0xN325 0xN326 0xN327 0xN328 0xN329 0xN32A 0xN32B 0xN32C 0xN32D - 0xN32E 0xN32F 0xN330 RxE3 GC Byte Register - G.832 RxE3 TTB-0 Register - G.832 RxE3 TTB-1 Register - G.832 RxE3 TTB-2 Register - G.832 RxE3 TTB-3 Register - G.832 RxE3 TTB-4 Register - G.832 RxE3 TTB-5 Register - G.832 RxE3 TTB-6 Register - G.832 RxE3 TTB-7 Register - G.832 RxE3 TTB-8 Register - G.832 RxE3 TTB-9 Register - G.832 RxE3 TTB-10 Register - G.832 RxE3 TTB-11 Register - G.832 RxE3 TTB-12 Register - G.832 RxE3 TTB-13 Register - G.832 RxE3 TTB-14 Register - G.832 RxE3 TTB-15 Register - G.832 RxE3 SSM Register - G.832 Reserved RxDS3 Pattern Register TxDS3 Configuration Register TxE3 Configuration Register - G.832 TxE3 Configuration Register - G.751 0x31 0x32 0x33 0xN331 0xN332 0xN333 TxDS3 FEAC Configuration and Status Register TxDS3 FEAC Register TxDS3 LAPD Configuration Register TxE3 LAPD Configuration Register 0x34 0xN334 TxDS3 LAPD Status/Interrupt Register TxE3 LAPD Status/Interrupt Register 0x00 0x00 0x7E 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0C 0x00 0x00 645 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x35 ADDRESS LOCATION 0xN335 REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES TxDS3 M-Bit Mask Register TxE3 GC Byte Register - G.832 TxE3 Service Bits Register - G.751 0x00 0x36 0xN336 TxDS3 F-Bit Mask # 1 Register TxE3 MA Byte Register - G.832 0x00 0x37 0xN337 TxDS3 F-Bit Mask # 2 Register TxE3 NR Byte Register - G.832 0x00 0x38 0xN338 TxDS3 F-Bit Mask # 3 Register TxE3 TTB-0 Register - G.832 0x00 0x39 0xN339 TxDS3 F-Bit Mask # 4 Register TxE3 TTB-1 Register - G.832 0x00 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0xN33A 0xN33B 0xN33C 0xN33D 0xN33E 0xN33F 0xN340 0xN341 0xN342 0xN343 0xN344 0xN345 0xN346 0xN347 0xN348 TxE3 TTB-2 Register - G.832 TxE3 TTB-3 Register - G.832 TxE3 TTB-4 Register - G.832 TxE3 TTB-5 Register - G.832 TxE3 TTB-6 Register - G.832 TxE3 TTB-7 Register - G.832 TxE3 TTB-8 Register - G.832 TxE3 TTB-9 Register - G.832 TxE3 TTB-10 Register - G.832 TxE3 TTB-11 Register - G.832 TxE3 TTB-12 Register - G.832 TxE3 TTB-13 Register - G.832 TxE3 TTB-14 Register - G.832 TxE3 TTB-15 Register - G.832 TxE3 FA1 Error Mask Register - G.832 TxE3 FAS Error Mask Upper Register - G.751 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x49 0xN349 TxE3 FA2 Error Mask Register - G.832 TxE3 FAS Error Mask Lower Register - G.751 0x00 0x4A 0xN34A TxE3 BIP-8 Mask Register - G.832 TxE3 BIP-4 Mask Register - G.751 0x00 0x4B 0x4C 0xN34B 0xN34C Tx SSM Register - G.832 TxDS3 Pattern Register 0x00 0x0C 646 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0xN34D 0xN34E 0xN34F 0xN350 0xN351 0xN352 0xN353 0xN354 0xN355 0xN356 0xN357 0xN358 0xN359 0xN35A 0xN35B 0xN35C 0xN35D 0xN35E 0xN35F 0xN360 - 0xN367 0xN368 0xN369 0xN36A - 0xN36B 0xN36C 0xN36D 0xN36E 0xN36F 0xN370 0xN371 0xN372 0xN373 REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 - 0x67 0x68 0x69 0x6A - 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 Receive DS3/E3 AIS/PDI-P Alarm Enable Register PMON Excessive Zero Count Register - MSB PMON Excessive Zero Count Register - LSB PMON LCV Event Count Register - MSB PMON LCV Event Count Register - LSB PMON Framing Bit/Byte Error Count Register - MSB PMON Framing Bit/Byte Error Count Register - LSB PMON Parity Error Event Count Register - MSB PMON Parity Error Event Count Register - LSB PMON FEBE Event Count Register - MSB PMON FEBE Event Count Register - LSB PMON CP-Bit Error Count Register - MSB PMON CP-Bit Error Count Register - LSB PMON PLCP BIP-8 Error Count Register - MSB PMON PLCP BIP-8 Error Count Register - LSB PMON PLCP Framing Byte Error Count Register - MSB PMON PLCP Framing Byte Error Count Register - LSB PMON PLCP FEBE Error Count Register - MSB PMON PLCP FEBE Error Count Register - LSB Reserved PMON PRBS Bit Error Count Register - MSB PMON PRBS Bit Error Count Register - LSB Reserved PMON Holding Register One Second Error Status Register One Second - LCV Count Accumulator Register - MSB One Second - LCV Count Accumulator Register - LSB One Second - Parity Error Accumulator Register - MSB One Second - Parity Error Accumulator Register - LSB One Second - CP Bit Error Accumulator Register - MSB One Second - CP Bit Error Accumulator Register - LSB 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 647 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0x74 - 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 - 0x8F 0x90 0x91 0x92 0x93 - 0x97 0x98 0x99 0x9A 0x9B 0x9C - 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 - 0xEF 0xF0 0xF1 0xF2 0xF3 - 0xF7 0xF8 0xF9 ADDRESS LOCATION 0xN374 - 0xN37F 0xN380 0xN381 0xN382 0xN383 0xN384 0xN385 - 0xN38F 0xN390 0xN391 0xN392 0xN393 - 0xN397 0xN398 0xN399 0xN39A 0xN39B 0xN39C - 0xN3AF 0xN3B0 0xN3B1 0xN3B2 0xN3B3 0xN3B4 - 0xN3EF 0xN3F0 0xN3F1 0xN3F2 0xN3F3 - 0xN3F7 0xN3F8 0xN3F9 Reserved Line Interface Drive Register Reserved Reserved TxLAPD Byte Count Register RxLAPD Byte Count Register Reserved Receive PLCP Configuration and Status Register Receive PLCP Interrupt Enable Register Receive PLCP Interrupt Status Register Reserved Transmit PLCP A1 Byte Error Mask Register Transmit PLCP A2 Byte Error Mask Register Transmit PLCP BIP-8 Error Mask Register Transmit PLCP G1 Byte Register Reserved Transmit LAPD Memory Indirect Address Register Transmit LAPD Memory Indirect Data Register Receive LAPD Memory Indirect Address Register Receive LAPD Memory Indirect Data Register Reserved Receive DS3/E3 Configuration Register - Secondary Frame Synchronizer Block - Byte 1 Receive DS3/E3 Configuration Register - Secondary Frame Synchronizer Block - Byte 0 Receive DS3/E3 AIS/PDI-P Alarm Enable Register - Secondary Frame Synchronizer Block Reserved Receive DS3/E3 Interrupt Enable Register - Secondary Frame Synchronizer Block Receive DS3/E3 Interrupt Status Register - Secondary Frame Synchronizer Block REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x10 0x00 0x00 0x00 0x00 648 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS DS3/E3 FRAMER BLOCK REGISTER DESCRIPTION 1.12.2 Table 567: Operating Mode Register (Address Location= 0xN300) BIT 7 Local Loop Back R/W 0 BIT 6 IsDS3 BIT 5 Internal LOS Enable R/W 1 BIT 4 RESET BIT 3 Direct Map BIT 2 Frame Format R/W 0 BIT 1 BIT 0 TimRefSel[1:0] R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 BIT NUMBER 7 NAME Local Loop Back TYPE R/W DESCRIPTION Framer Block Local Loop-back Mode: This READ/WRITE bit field configures the Frame Generator/Frame Synchronizer blocks to operate in the Local Loop-back Mode. If the Frame Generator/Frame Synchronizer blocks are configured to operate in the Local Loop-back Mode, then the TxPOS_n, TxNEG_n and TxLineClk signal is internally looped back into the RxPOS_n, RxNEG_n and RxLineClk signals. 0 - Normal Operating Mode 1 - Local Loop-back Mode 6 IsDS3 R/W Is DS3 Mode: This READ/WRITE bit-field, along with Bit 2 (Frame Format), permits the user to configure the Frame Generator/Frame Synchronizer block to operate in the appropriate framing format. The relationship between the state of this bit-field, Bit 2 and the resulting framing format is presented below. Bit 6 (IsDS3) 0 0 1 1 5 Internal LOS Enable R/W Bit 2 (Frame Format) 0 1 0 1 Framing Format E3, ITU-T G.751 E3, ITU-T G.832 DS3, C-bit Parity DS3, M13 Internal LOS Enable: This READ/WRITE bit-field permits the user to enable or disable the "Internal LOS Detector", within the Frame Synchronizer block. 0 - Internal LOS Detector is disabled. 1 - Internal LOS Detector is enabled. 4 RESET R/W Software RESET Input: A "0" to "1" transition in this bit-field commands a Software RESET to the Channel. Once the user executes a Software reset to the frame, all of the internal state machines will be reset; and the Frame Synchronizer block will execute a "Reframe" operation. Note: For a Software Reset, the contents of the Command Register will not be reset to their default values. 3 Direct Map R/W Direct Map: The READ/WRITE bit-field permits the user to configure the DS3/E3 framer 649 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS block to bypass the PLCP processor block. 0 - PLCP processor block is bypassed 1 - PLCP processor block is used in the design 2 Frame Format R/W 20 0 Rev2...0...0 200 Frame Format: This READ/WRITE bit-field, along with Bit 6 (IsDS3), permits the user to configure the Frame Generator/Frame Synchronizer block to operate in the appropriate framing format. The relationship between the state of this bit-field, Bit 2 and the resulting framing format is presented below. Bit 6 (IsDS3) 0 0 1 1 1-0 TimRefSel[1:0] R/W Bit 2 (Frame Format) 0 1 0 1 Framing Format E3, ITU-T G.751 E3, ITU-T G.832 DS3, C-bit Parity DS3, M13 Time Reference Select: These two READ/WRITE bit-fields permit the user to define both the timing source and the framing-alignment source for the Frame Generator block, as presented below. TimRefSel[1:0] 00 Timing Reference Loop-Timing (Timing is taken from the Frame Synchronizer block) Transmit Clock Source for the Frame Generator block Transmit Clock Source for the Frame Generator block Transmit Clock Source for the Frame Generator block Framing Reference Asynchronous 01 TxDS3FP Input 10 Asynchronous 11 Asynchronous 650 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 568: I/O Control Register (Address Location= 0xN301) BIT 7 Disable TxLOC R/W 1 BIT NUMBER 7 BIT 6 LOC BIT 5 Disable RxLOC R/W 1 BIT 4 AMI/ZeroSuppression R/W 0 BIT 3 Single Rail/Dual Rail Select R/O 1 BIT 2 DS3/E3 CLK_OUT Invert: R/O 0 DESCRIPTION Disable Transmit Loss of Clock Feature: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit Loss of Clock" feature. If this feature is enabled, then the DS3/E3 Framer block will enable some circuitry that will terminate the current READ or WRITE access (to the Microprocessor Interface), if a "Loss of Transmit (or Frame Generator) Clock Event were to occur. The intent behind this feature is to prevent any READ/WRITE accesses (to the DS3/E3 Framer block) from "hanging" in the event of a "Loss of Clock" event. 0 - Enables the "Transmit Loss of Clock" feature. 1 - Disables the "Transmit Loss of Clock" feature. 6 LOC R/O Loss of Clock Indicator: This READ-ONLY bit-field indicates that the Channel has experiences a Loss of Clock event. 5 Disable RxLOC R/W Disable Receive Loss of Clock Feature This READ/WRITE bit-field permits the user to either enable or disable the "Receive Loss of Clock" feature. If this feature is enabled, then the DS3/E3 Framer block will enable some circuitry that will terminate the current READ or WRITE access (to the Microprocessor Interface), if a "Loss of Receiver (or Frame Synchronizer) Clock Event were to occur. The intent behind this feature is to prevent any READ/WRITE accesses (to the DS3/E3 Framer block) from "hanging" in the event of a "Loss of Clock" event. 0 - Enables the "Receive Loss of Clock" feature. 1 - Disables the "Receive Loss of Clock" feature. 4 AMI/ZeroSuppressi on AMI/Zero-Suppression Line Code Select : This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer Block (associated with channel N) to operate in either the AMI or B3ZS/HDB3 Line Code; as described below. 0 - Configures the DS3/E3 Framer Channel to operate in the B3ZS/HDB3 Line Code. 1- Configures the DS3/E3 Framer Channel to operate in the AMI Line Code. 3 Single Rail/Dual Rail Select Single-Rail/Dual-Rail Select: This READ/WRITE bit-field permits the user to configure the Primary Frame Synchronizer/Frame Generator blocks (within the XRT94L33) to operate in either the "Single-Rail" or "Dual-Rail" Mode. If the user configures the Primary Frame Synchronizer and Frame Generator blocks to operate in the Single-Rail mode, then the following will happen. * The Primary Frame Synchronizer block will accept data (from the LIU IC) in a BIT 1 DS3/E3 CLK_IN Invert: R/O 0 BIT 0 Reframe R/O 0 NAME Disable TxLOC R/W 0 TYPE R/W 651 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Single-Rail Manner. * The Frame Generator block will output data (to the LIU IC) in a Single-Rail Manner. If the user configures the Primary Frame Synchronizer and Frame Generator blocks to operate in the Dual-Rail mode, then the following will happen. * The Primary Frame Synchronizer block will accept data (from the LIU IC) in a DualRail Manner. * The Frame Generator block will output data (to the LIU IC) in a Dual-Rail Manner. 0 - Configures the Primary Frame Synchronizer/Frame Generator to operate in the Dual-Rail Mode. 1 - Configures the Primary Frame Synchronizer/Frame Generator to operate in the Single-Rail Mode. Note: This bit-field is only valid if the Primary Frame Synchronizer block has been configured to operate in the Ingress Direction, and if the Frame Generator block has been configured to operate in the Egress Direction. 20 0 Rev2...0...0 200 2 DS3/E3_ CLK_OUT Invert: DS3/E3_CLK_OUT Invert: This READ/WRITE bit-field permits the user to configure the DS3/E3 Frame Generator block (of Channel n), within the XRT94L33, to update the "TxDS3POS_n" output pins (pin B18, G24, AG9) upon either the rising or falling edge of "TxDS3LineClk_n" (pin C17, E25, AF10) 0 - "TxDS3POS_n" is updated upon the rising edge of "TxDS3LineClk_n". The user should insure that the LIU IC will sample "TxDS3POS_n" upon the falling edge of "TxDS3LineClk_n". 1 - "TxDS3POS_n" is updated upon the falling edge of "TxDS3LineClk_n". The user should insure that the LIU IC will sample "TxDS3POS_n" upon the rising edge of "TxDS3LineClk_n". Note: This bit-field is only active if the Frame Generator block has been configured to operate in the Egress Path. 1 DS3/E3_ CLK_IN Invert: R/O DS3/E3/STS1_CLK_IN Invert: This READ/WRITE bit-field permits the user to configure Channel n, within the XRT94L33; to sample and latch the "RxDS3POS_n" input pins (pin B14. C21. AG15)" upon either the rising or falling edge of "RxDS3LineClk_n" (pin D14, A24, AF14).. 0 - "RxDS3POS_n" is sampled upon the falling edge of "RxDS3LineClk_n" 1 - "RxDS3POS_n" is sampled upon the rising edge of "RxDS3LineClk_n" 0 Reframe R/W DS3/E3 Frame Synchronizer Block - Reframe Command: A "0" to "1" transition, within this bit-field commands the DS3/E3 Frame Synchronizer block (within Channel n) to exit the Frame Maintenance Mode, and go back and enter the Frame Acquisition Mode. Note: The user should go back and set this bit-field to "0" following execution of the "Reframe" Command. 652 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 569: Block Interrupt Enable Register (Address Location= 0xN304) BIT 7 DS3/E3 Frame Synch Block Interrupt Enable R/W 0 R/O 0 R/O 0 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 DS3/E3 Frame Generator Block Interrupt Enable R/O 0 R/O 0 R/W 0 BIT 0 One Second Interrupt R/O 0 R/W 0 BIT NUMBER 7 NAME DS3/E3 Frame Synch Block Interrupt Enable TYPE R/W DESCRIPTION DS3/E3 Frame Synchronizer Block Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the Frame Synchronizer block for Interrupt Generation. If the user enables the Frame Synchronizer block (for Interrupt Generation) at the block level, the user still needs to enable the interrupts at the "Source" level, as well; in order for these interrupts to be enabled. However, if the user disables the Frame Synchronizer block (for Interrupt Generation) at the Block Level, then ALL Frame Synchronizer-related blocks are disabled. 0 - Frame Synchronizer block is Disabled for Interrupt Generation. 1 - Frame Synchronizer block is enabled (at the Block level) for Interrupt Generation. 6-2 1 Unused DS3/E3 Frame Generator Block Interrupt Enable R/O R/W DS3/E3 Frame Generator Block Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the Frame Generator block for Interrupt Generation. If the user enables the Frame Generator block (for Interrupt Generation) at the block level, the user still needs to enable the interrupts at the "Source" level, as well; in order for these interrupts to be enabled. However, if the user disables the Frame Generator block (for Interrupt Generation) at the Block Level, then ALL Frame Generator-related blocks are disabled. 0 - Frame Generator block is Disabled for Interrupt Generation. 1 - Frame Generator block is Enabled (at the Block Level) for Interrupt Generation. 0 One Second Interrupt R/W One Second Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the OneSecond Interrupt, within Channel n. If the user enables this interrupt, then Channel n will generate an interrupt at one second intervals. 0 - One Second Interrupt is disabled. 1 - One Second Interrupt is enabled. 653 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 570: Block Interrupt Status Register (Address Location= 0xN305) BIT 7 DS3/E3 Frame Sync Block Interrupt Status R/O 0 R/O 0 R/O 0 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 DS3/E3 Frame Generator Block Interrupt Status R/O 0 R/O 0 R/O 0 BIT 0 One Second Interrupt 20 0 Rev2...0...0 200 R/O 0 RUR 0 BIT NUMBER 7 NAME DS3/E3 Frame Synch Block Interrupt Status TYPE R/O DESCRIPTION DS3/E3 Frame Synchronizer Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "DS3/E3 Frame Synchronizer Block"-related interrupt (within Channel n) is requesting interrupt service. 0 - The DS3/E3 Frame Synchronizer block (within Channel n) is NOT requesting any interrupt service. 1 - The DS3/E3 Frame Synchronizer block (within Channel n) is requesting interrupt service. 6-2 1 Unused DS3/E3 Frame Generator Block Interrupt Status R/O R/O DS3/E3 Frame Generator Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a "DS3/E3 Frame Generator" -related interrupt (within Channel n) is requesting interrupt service. 0 - The DS3/E3 Frame Generator block (within Channel n) is NOT requesting any interrupt service. 1 - The DS3/E3 Frame Synchronizer block (within Channel n) is requesting interrupt service. 0 One Second Interrupt Status RUR One Second Interrupt Status This RESET-upon-READ bit-field indicates whether or not a "One Second" Interrupt (from Channel n) has occurred since the last read of this register. 0 - The One Second Interrupt has NOT occurred since the last read of this register. 1 - The One Second Interrupt has occurred since the last read of this register. 654 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 571: Test Register (Address Location= 0xN30C) BIT 7 TxOHSrc R/W 0 0 BIT 6 R/O BIT 5 R/O 0 BIT 4 RxPRBS Lock R/O 0 BIT 3 RxPRBS Enable R/W 0 BIT 2 TxPRBS Enable R/W 0 R/O 0 BIT 1 Unused R/O 0 BIT 0 Unused BIT NUMBER 7 NAME TxOHSrc TYPE R/W Transmit Overhead Bit Source: DESCRIPTION This READ/WRITE bit-field permits the user to configure the Frame Generator to accept and insert overhead bits/bytes which are input via the "Payload Data Input Interface" block, as indicated below. 0 - Overhead bits/bytes are internally generated by the Frame Generator block. 1 - Overhead bits/byte data is accepted from the Payload Data Input Interface block. Note: 6-5 4 Unused RxPRBS Lock R/O R/O PRBS Lock Indicator: This READ-ONLY bit-field indicates whether or not the PRBS Receiver (within the Channel) has acquired "PRBS Lock" with the payload data of the incoming DS3 or E3 data stream. 0 - PRBS Receiver does not have PRBS Lock with the incoming data stream. 1 - PRBS Receiver does have PRBS Lock with the incoming data stream. Note: 3 RxPRBS Enable R/W This bit-field is not valid if the PRBS Receiver is disabled, or if the Frame Synchronizer block is bypassed. This register bit applies to all framing formats that are supported by the Frame Generator block. Receive PRBS Enable: This READ/WRITE bit-field permits the user to either enable or disable the PRBS Receiver within the Frame Synchronizer block. Once the user enables the PRBS Receiver, then it will proceed to attempt to acquire and maintain pattern (or PRBS Lock) within the payload bits, within the incoming DS3 or E3 data stream. 0 - Disables the PRBS Receiver. 1 - Enables the PRBS Receiver. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 2 TxPRBS Enable R/W Transmit PRBS Enable: This READ/WRITE bit-field permits the user to either enable or disable the PRBS Generator within the Frame Generator block. Once the user enables the PRBS Generator block, then it will proceed to insert a PRBS pattern into the payload bits, within the outbound DS3 or E3 data stream. 0 - Disables the PRBS Generator. 1 - Enables the PRBS Generator. Note: This bit-field is ignored if the Frame Generator block is by-passed. 1-0 Unused R/O 655 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.12.3 RECEIVE DS3 RELATED REGISTERS 20 0 Rev2...0...0 200 Table 572: RxDS3 Configuration and Status Register (Address Location= 0xN310) BIT 7 RxAIS BIT 6 RxLOS BIT 5 RxIdle BIT 4 RxOOF BIT 3 Unused BIT 2 Framing with Valid PBits R/W 0 BIT 1 F-Sync Algo R/W 1 BIT 0 M-Sync Algo R/W 0 R/O 0 R/O 0 R/O 0 R/O 1 R/O 0 BIT NUMBER 7 NAME RxAIS TYPE R/O Receive AIS Defect Indicator: DESCRIPTION This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently detecting the AIS pattern in its incoming path. 0 - Frame Synchronizer block is NOT currently detecting an AIS pattern in its incoming path. 1 - Frame Synchronizer block is currently detecting an AIS pattern in its incoming path. 6 RxLOS R/O Receive LOS Defect Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently detecting the LOS condition, in its incoming path. 0 - Frame Synchronizer block is NOT currently declaring an LOS condition in its incoming path. 1 - Frame Synchronizer block is currently detecting an LOS condition in its incoming path. 5 RxIdle R/O Receive Idle Signal Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently detecting the DS3 Idle pattern, in its incoming path. 0 - Frame Synchronizer block is NOT currently detecting the DS3 Idle Pattern, in its incoming path. 1 - Frame Synchronizer block is currently detecting the DS3 Idle Pattern in its incoming path. 4 RxOOF R/O Receive OOF Defect Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring an OOF (Out of Frame) condition. 0 - Frame Synchronizer block is NOT currently declaring the OOF condition. 1 - Frame Synchronizer block is currently declaring the OOF condition. 3 2 Unused Framing with Valid P Bits R/O R/W Framing with Valid P-Bit Select: This READ/WRITE bit-field permits the user to choose between two different sets of DS3 Frame Acquisition/Maintenance criteria. 0 - Normal Framing Acquisition/Maintenance Criteria (without P-bit Checking) In this mode, the Frame Synchronizer block will declare the "In-frame" state, one it has successfully completed both the "F-Bit Search" and the "M-Bit Search" states. 656 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Framing Acquisition/Maintenance with P-bit Checking In this mode, the Frame Synchronizer block will (in addition to passing through the "F-Bit Search" and "M-Bit Search" states) also verify valid P-bits, prior to declaring the "In-Frame" state. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 1 F-Sync Algo R/W F-Bit Search State Criteria Select: This READ/WRITE bit-field permits the user to choose between two different sets of DS3 Out of Frame (OOF) Declaration criteria. 0 - OOF is declared when 6 out of 15 F-bits are erred. 1 - OOF is declared when 3 out of 15 F-bits are erred. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 0 M-Sync Algo R/W M-Bit Search State Criteria Select: This READ/WRITE bit-field permits the user to choose between two different sets of DS3 Out of Frame (OOF) Declaration criteria. 0 - M-bit Errors do not result in the Frame Synchronizer declaring OOF. 1 - OOF is declared when M-bits, within 3 out of 4 DS3 frames are in error. 657 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 8: RxDS3 Status Register (Address Location= 0xN311) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 BIT 5 BIT 4 RxFERF R/O 0 BIT 3 RxAIC R/O 0 R/O 0 BIT 2 BIT 1 RxFEBE[2:0] R/O 0 R/O 0 BIT 0 20 0 Rev2...0...0 200 BIT NUMBER 7-5 4 NAME Unused RxFERF TYPE R/O R/O DESCRIPTION Receive FERF (Far-End Receive Failure) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring a FERF condition. 0 - The Frame Synchronizer block is NOT currently declaring the FERF condition. 1 - The Frame Synchronizer block is currently declaring the FERF condition. Note: This bit-field is not valid if the Frame Synchronizer block has been bypassed. 3 RxAIC R/O Receive AIC State: This READ-ONLY bit-field indicates the current state of the AIC bit-field within the incoming DS3 data-stream. 0 - Indicates that the Frame Synchronizer block has received at least 2 consecutive M-frames that have the AIC bit-field set to "0". 1 - Indicates that the Frame Synchronizer block has received at least 63 consecutive M-frames that have the AIC bit-field set to "1". 2-0 RxFEBE[2:0] R/O Receive FEBE (Far-End Block Error) Value: These READ-ONLY bit-fields reflect the FEBE value within the most recently received DS3 frame. RxFEBE[2:0] = [1, 1, 1] indicates a normal condition. All other values for RxFEBE[2:0] indicates an erred condition at the remote terminal equipment. Note: 1. This bit-field is not valid if the Frame Synchronizer block has been bypassed. 2. This bit-field is not valid if the Frame Synchronizer block has been configured to operate in the M13 Framing format. 658 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 574: RxDS3 Interrupt Enable Register (Address Location= 0xN312) BIT 7 Detection of CP Bit Error Interrupt Enable R/W 0 BIT 6 Change of LOS Condition Interrupt Enable R/W 0 BIT 5 Change of AIS Condition Interrupt Enable R/W 0 BIT 4 Change of Idle Condition Interrupt Enable R/W 0 BIT 3 Change of FERF Condition Interrupt Enable R/W 0 BIT 2 Change of AIC State Interrupt Enable R/W 0 BIT 1 Change of OOF Condition Interrupt Enable R/W 0 BIT 0 Detection of P-Bit Error Interrupt Enable R/W 0 BIT NUMBER 7 NAME Detection of CP Bit Error Interrupt Enable TYPE R/W DESCRIPTION Detection of CP-Bit Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of CP-Bit Error" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime it detects CP bit errors. 0 - Disables the "Detection of CP Bit Error" Interrupt. 1 - Enables the "Detection of CP-Bit Error" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 6 Change of LOS Condition Interrupt Enable R/W Change in LOS Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOS (Loss of Signal) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an LOS condition. * The instant that the channel clears the LOS condition. 0 - Disables the "Change in LOS Condition" Interrupt. 1 - Enables the "Change in LOS Condition" Interrupt. 5 Change of AIS Condition Interrupt Enable R/W Change in AIS Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in AIS (Alarm Indication Signal) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an AIS condition. * The instant that the channel clears the AIS condition. 0 - Disables the "Change in AIS Condition" Interrupt. 1 - Enables the "Change in AIS Condition" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 4 Change of Idle Condition Interrupt Enable R/W Change in Idle Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in Idle Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel detects the Idle condition. * The instant that the channel ceases to detect the Idle condition. 659 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Disables the "Change in Idle Condition" Interrupt. 1 - Enables the "Change in Idle Condition" Interrupt. Note: 3 Change of FERF Condition Interrupt Enable R/W This bit-field is ignored if the Frame Synchronizer block is by-passed. 20 0 Rev2...0...0 200 Change in FERF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in FERF (Far-End Receive Failure) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an FERF condition. * The instant that the channel clears the FERF condition. 0 - Disables the "Change in FERF Condition" Interrupt. 1 - Enables the "Change in FERF Condition" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 2 Change of AIC State Interrupt Enable R/W Change in AIC State Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in AIC State" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to it detecting a change in the AIC bit-field, within the incoming DS3 data stream. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 1 Change of OOF Condition Interrupt Enable R/W Change in OOF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in OOF (Out of Frame) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an OOF condition. * The instant that the channel clears the OOF condition. 0 - Disables the "Change in OOF Condition" Interrupt. 1 - Enables the "Change in OOF Condition" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 0 Detection of PBit Error Interrupt Enable R/W Detection of P-Bit Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of CP-Bit Error" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime it detects CP bit errors. 0 - Disables the "Detection of CP Bit Error" Interrupt. 1 - Enables the "Detection of CP-Bit Error" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 660 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 575: RxDS3 Interrupt Status Register (Address Location= 0xN313) BIT 7 Detection of CP Bit Error Interrupt Status RUR 0 BIT 6 Change of LOS Condition Interrupt Status RUR 0 BIT 5 Change of AIS Condition Interrupt Status RUR 0 BIT 4 Change of Idle Condition Interrupt Status RUR 0 BIT 3 Change of FERF Condition Interrupt Status RUR 0 BIT 2 Change of AIC State Interrupt Status RUR 0 BIT 1 Change of OOF Condition Interrupt Status RUR 0 BIT 0 Detection of P-Bit Error Interrupt Status RUR 0 BIT NUMBER 7 NAME Detection of CP Bit Error Interrupt Status TYPE RUR DESCRIPTION Detection of CP-Bit Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of CP-Bit Error" Interrupt has occurred since the last read of this register. 0 - The "Detection of CP-Bit Error" Interrupt has not occurred since the last read of this register. 1 - The "Detection of CP-Bit Error" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is bypassed. 6 Change of LOS Condition Interrupt Status RUR Change in LOS Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the "Change in LOS Condition" Interrupt has occurred since the last read of this register. 0 - The "Change in LOS Condition" Interrupt has not occurred since the last read of this register. 1 - The "Change in LOS Condition" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is bypassed. 5 Change of AIS Condition Interrupt Status RUR Change in AIS Condition Interrupt Status This RESET-upon-READ register indicates whether or not the "Change in LOS Condition" Interrupt has occurred since the last read of this register. 0 - The "Change in LOS Condition" Interrupt has not occurred since the last read of this register. 1 - The "Change in LOS Condition" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is bypassed. 4 Change of Idle Condition Interrupt Status RUR Change in Idle Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the "Change in Idle Condition" interrupt has occurred since the last read of this register. 0 - The "Change in Idle Condition" Interrupt has not occurred since the last read of this register. 1 - The "Change in Idle Condition" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is by- 661 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS passed. 3 Change of FERF Condition Interrupt Status RUR Change in FERF Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the "Change in FERF Condition" Interrupt has occurred since the last read of this register. 0 - The "Change in FERF Condition" Interrupt has not occurred since the last read of this register. 1 - The "Change in FERF Condition" Interrupt has occurred since the last read of this register. Note: 2 Change of AIC State Interrupt Status RUR This bit-field is ignored if the Frame Synchronizer block is bypassed. 20 0 Rev2...0...0 200 Change in AIC State Interrupt Status: This RESET-upon-READ register bit indicates whether or not the "Change in AIC State" interrupt has occurred since the last read of this register. 0 - The "Change in AIC State" Interrupt has not occurred since the last read of this register. 1 - The "Change in AIC State" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is bypassed. 1 Change of OOF Condition Interrupt Status RUR Change in OOF Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the "Change in OOF Condition" Interrupt has occurred since the last read of this register. 0 - The "Change in OOF Condition" Interrupt has not occurred since the last read of this register. 1 - The "Change in OOF Condition" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is bypassed. 0 Detection of P-Bit Error Interrupt Status RUR Detection of P-Bit Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of CP-Bit Error" Interrupt has occurred since the last read of this register. 0 - The "Detection of CP-Bit Error" Interrupt has not occurred since the last read of this register. 1 - The "Detection of CP-Bit Error" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is bypassed. 662 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 576: RxDS3 Sync Detect Register (Address Location= 0xN314) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 Unused R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 P-Bit Correct R/W 0 BIT 1 F Algorithm R/W 0 BIT 0 One and Only R/W 0 BIT NUMBER 2 NAME P-Bit Correct TYPE R/W P-Bit Correct: DESCRIPTION This READ/WRITE bit-field permits the user to enable or disable the "P-Bit Correct" feature within the DS3 Frame Synchronizer block. If the user enables this feature, then the DS3 Frame Synchronizer will automatically invert the state of any P-bits, whenever it detects "P-bit errors". 0 - Disables the "P-Bit Correct" feature. 1 - Enables the "P-Bit Correct" feature 1 F Algorithm R/W F-Bit Search Algorithm Select: This READ/WRITE bit-field permits the user to select the "F-bit acquisition" criteria, when the Frame Synchronizer block is operating in the "F-Bit Search" state. 0 - Frame Synchronizer will move on to the "M-Bit Search" state, when it has properly located 10 consecutive F-bits. 1 - Frame Synchronizer will move on to the "M-Bit Search" state, when it has properly located 16 consecutive F-bits. 0 One and Only R/W F-Bit Search/Mimic-Handling Algorithm Select: This READ/WRITE bit-field permits the user to select the "F-bit acquisition" criteria, when the Frame Synchronizer block is operating in the "F-Bit Search" state. 0 - Frame Synchronizer will move on to the "M-Bit Search" state, when it has properly located 10 (or 16) consecutive F-bits (as configured in Bit 1 of this register). 1 - Frame Synchronizer will move on to the "M-Bit Search" state, when (1) it has properly located 10 (or 16) consecutive F-bits; and (2) when it has located and identified only one viable "F-Bit Alignment" candidate. Note: If this bit is set to "1", then the Frame Synchronizer block will NOT transition into the "M-Bit Search" state, as long as at least two viable candidate set of bits appear to function as the F-bits. 663 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 577: RxDS3 FEAC Register (Address Location= 0xN316) BIT 7 Unused R/O 0 R/O 1 R/O 1 BIT 6 BIT 5 BIT 4 R/O 1 BIT 3 R/O 1 BIT 2 R/O 1 BIT 1 R/O 1 BIT 0 Unused R/O 0 20 0 Rev2...0...0 200 RxFEACCode[5:0] BIT NUMBER 7 6-1 NAME Unused RxFEAC_Code[5:0] TYPE R/O R/O Receive FEAC Code Word: DESCRIPTION These READ-ONLY bit-fields contain the value of the most recently "validated" FEAC Code word. 0 Unused R/O 664 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 578: RxDS3 FEAC Interrupt Enable/Status Register (Address Location= 0xN317) BIT 7 BIT 6 Unused BIT 5 BIT 4 FEAC Valid BIT 3 RxFEAC Remove Interrupt Enable R/W 0 BIT 2 RxFEAC Remove Interrupt Status RUR 0 BIT 1 RxFEAC Valid Interrupt Enable R/W 0 BIT 0 RxFEAC Valid Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused FEAC Valid TYPE R/O R/O DESCRIPTION Please set to "0" (the default value) for normal operation. FEAC Message Validation Indicator: This READ-ONLY bit-field indicates that the FEAC Code (which resides within the "RxDS3 FEAC" Register) has been validated by the Receive FEAC Controller. The Receive FEAC Controller will validate a FEAC codeword if it has received this codeword in 8 out of the last 10 FEAC Messages. Polled systems can monitor this bit-field, when checking for a newly validated FEAC codeword. 0 - FEAC Message is not (or no longer) validated. 1 - FEAC Message has been validated. 3 RxFEAC Remove Interrupt Enable R/W FEAC Message Remove Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive FEAC Remove Interrupt". If the user enables this interrupt, then the Framer Synchronizer will generate an interrupt anytime the most recently validated FEAC Message has been removed. The Receive FEAC Controller will remove a validated FEAC codeword, if it has received a different codeword in 3 out of the last 10 FEAC Messages. 0 - Receive FEAC Remove Interrupt is disabled. 1 - Receive FEAC Remove Interrupt is enabled. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 2 RxFEAC Remove Interrupt Status RUR FEAC Message Remove Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "FEAC Message Remove Interrupt" has occurred since the last read of this register. 0 - FEAC Message Remove Interrupt has NOT occurred since the last read of this register. 1 - FEAC Message Remove Interrupt has occurred since the last read of this register. 1 RxFEAC Valid Interrupt Enable R/W FEAC Message Validation Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the FEAC Message Validation Interrupt. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime a new FEAC Codeword has been validated by the Receive FEAC Controller. 0 - FEAC Message Validation Interrupt is NOT enabled. 1 - FEAC Message Validation Interrupt is enabled. 0 RxFEAC Valid Interrupt RUR FEAC Message Validation Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "FEAC Message V lid ti " I t th di th l t d f thi it 665 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Status Validation" Interrupt has occurred since the last read of this register. 0 - FEAC Message Validation Interrupt has not occurred since the last read of this register. 1 - FEAC Message Validation Interrupt has occurred since the last read of this register. 20 0 Rev2...0...0 200 666 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 579: RxDS3 LAPD Control Register (Address Location= 0xN318) BIT 7 RxLAPD Any R/W 0 R/O 0 R/O 0 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 RxLAPD Enable R/O 0 R/O 0 R/W 0 BIT 1 RxLAPD Interrupt Enable R/W 0 BIT 0 RxLAPD Interrupt Status RUR 0 BIT NUMBER 7 NAME RxLAPD Any TYPE R/W Receive LAPD - Any kind: DESCRIPTION This READ/WRITE bit-field permits the user to configure the LAPD Receiver to receive any kind of LAPD Message (or HDLC Message) with a size of 82 bytes or less. If the user implements this option, then the LAPD Receiver will be capable of receiving any kind of HDLC Message (with any value of header bytes). The only restriction is that the size of the HDLC Message must not exceed 82 bytes. 0 - Does not invoke this "Any Kind of HDLC Message" feature. In this case, the LAPD Receiver will only receive HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. Invokes this "Any Kind of HDLC Message" feature. In this case, the LAPD Receiver will be able to receive HDLC Messages that contain any header byte values. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. The user can determine the size (or byte-count) of the most recently received LAPD/PMDL Message, by reading the contents of the "RxLAPD Byte Count" Register (Address Location= 0xN284) 6-3 2 Unused RxLAPD Enable R/O R/W LAPD Receiver Enable: This READ/WRITE bit-field permits the user to either enable or disable the LAPD Receiver within the channel. If the user enables the LAPD Receiver, then it will immediately begin extracting out and monitoring the data (being carried via the "DL" bits) within the incoming DS3 data stream. 0 - Enables the LAPD Receiver. 1 - Disables the LAPD Receiver. Note: 1 RxLAPD Interrupt Enable R/W This bit-field is ignored if the Frame Synchronizer block is by-passed. Receive LAPD Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive LAPD Message" Interrupt. If the user enables this interrupt, then the channel will generate an interrupt, anytime the LAPD Receiver receives a new PMDL Message. 0 - Disables the "Receive LAPD Message" Interrupt. 1 - Enables the "Receive LAPD Message" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 0 RxLAPD Interrupt Status RUR Receive LAPD Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Receive LAPD 667 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Status Message" Interrupt has occurred since the last read of this register. 0 - "Receive LAPD Message" Interrupt has NOT occurred since the last read of this register. 1 - "Receive LAPD Message" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 20 0 Rev2...0...0 200 668 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 580: RxDS3 LAPD Status Register (Address Location= 0xN319) BIT 7 Unused R/O 0 BIT 6 RxABORT R/O 0 BIT 5 BIT 4 BIT 3 RxCR Type R/O 0 BIT 2 RxFCS Error R/O 0 BIT 1 End of Message R/O 0 BIT 0 Flag Present R/O 0 RxLAPDType[1:0] R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused RxABORT TYPE R/O R/O DESCRIPTION Receive ABORT Sequence Indicator: This READ-ONLY bit-field indicates that the LAPD Receiver has received an ABORT sequence (e.g., a string of seven consecutive "0s"). 0 - LAPD Receiver has NOT received an ABORT sequence. 1 - LAPD Receiver has received an ABORT sequence. Note: Once the LAPD Receiver receives an ABORT sequence, it will set this bit-field "high", until it receives another LAPD Messages. 5-4 RxLAPDType[1:0] R/O Receive LAPD Message Type Indicator: These two READ-ONLY bits indicate the type of LAPD Message that is residing within the Receive LAPD Message buffer. The relationship between the content of these two bit-fields and the corresponding message type is presented below. RxLAPDType[1:0] 0 0 1 1 3 RxCR Type R/O 0 1 0 1 Message Type CL Path Identification Idle Signal Identification Test Signal Identification ITU-T Path Identification Received C/R Value: This READ-ONLY bit-field indicates the value of the C/R bit (within one of the header bytes) of the most recently received LAPD Message. 2 RxFCS Error R/O Receive Frame Check Sequence (FCS) Error Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD Message frame contained an FCS error. 0 - The most recently received LAPD Message frame does not contain an FCS error. 1 - The most recently received LAPD Message frame does contain an FCS error. 1 End of Message R/O End of Message Indicator This READ-ONLY bit-field indicates whether or not the LAPD Receiver has received a complete LAPD Message. 0 - LAPD Receiver is currently receiving a LAPD Message, but has not 669 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS received the complete message. 1 - LAPD Receiver has received a completed LAPD Message. Note: Once the LAPD Receiver sets this bit-field "high", this bit-field will remain high, until the LAPD Receiver begins to receive a new LAPD Message. 20 0 Rev2...0...0 200 0 Flag Present R/O Receive Flag Sequence Indicator: This READ-ONLY bit-field indicates whether or not the LAPD Receiver is currently receiving the Flag Sequence (e.g., a continuous stream of 0x7E octets within the Data Link channel). 0 - LAPD Receiver is NOT currently receiving the Flag Sequence octet. 1 - LAPD Receiver is currently receiving the Flag Sequence octet. 670 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 581: RxDS3 Pattern Register (Address Location= 0xN32F) BIT 7 DS3 AIS Unframed All Ones R/W 0 BIT 6 DS3 AIS Non Stuck Stuff R/W 0 BIT 5 Unused BIT 4 Receive LOS Pattern R/W 0 R/W 1 BIT 3 BIT 2 BIT 1 BIT 0 Receive DS3 Idle Pattern[3:0] R/O 0 R/W 1 R/W 0 R/W 0 BIT NUMBER 7 NAME DS3 AIS Unframed All Ones TYPE R/W DESCRIPTION DS3 AIS - Unframed All Ones - AIS Pattern This READ/WRITE bit-field, (along with the "Non-Stuck-Stuff" bit) permits the user specify the "AIS Declaration" criteria for the DS3 Frame Synchronizer block, as described below. 0 - Configures the DS3 Frame Synchronizer block to declare an AIS condition, when receiving a DS3 signal carrying a "framed 1010.." pattern. 1 - Configures the DS3 Frame Synchronizer block to declare an AIS condition, when receiving either an unframed, All Ones pattern or a "framed 1010.." pattern. 6 DS3 AIS Non-Stuck Stuff R/W DS3 AIS - Non-Stuck-Stuff Option - AIS Pattern This READ/WRITE bit-field (along with the "Unframed All Ones - AIS Pattern bit-field) permits the user to define the "AIS Declaration" criteria for the DS3 Frame Synchronizer block, as described below. 0 - Configures the DS3 Frame Synchronizer block to require that all "C" bits are set to "0" before it will declare an AIS condition. 1 - Configures the DS3 Frame Synchronizer block to NOT require that all "C" bits are set to "0" before it will declare an AIS condition. In this mode, no attention will be paid to the state of the "C" bits within the incoming DS3 data-stream. 5 4 Unused Receive LOS Pattern R/O R/W Receive LOS Pattern: This READ/WRITE bit-field permits the user to define the "LOS Declaration" criteria for the DS3 Frame Synchronizer block, as described below. 0 - Configures the DS3 Frame Synchronizer to declare an LOS condition if it receives a string of a specific length of consecutive zeros. 1 - Configures the DS3 Frame Synchronizer to declare an LOS condition if it receives a string (of a specific length) of consecutive ones. 3-0 Receive DS3 Idle Pattern[3:0] R/W Receive DS3 Idle Pattern: These READ/WRITE bit-fields permit the user to specify the pattern in which the DS3 Frame Synchronizer will recognize as the "DS3 Idle Pattern". Note: The Bellcore GR-499-CORE specified value for the Idle Pattern is a framed repeating "1, 1, 0, 0..." pattern. Therefore, if the user wishes to configure the "DS3 Frame Synchronizer" to declare an "Idle Pattern" when it receives this pattern, then he/she write the value [1100] into these bit-fields. 1.12.4 RECEIVE E3, ITU-T G.751 RELATED REGISTERS 671 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 582: RxE3 Configuration and Status Register # 1 - G.751 (Address Location= 0xN310) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 RxFERF Algo R/W 0 R/O 0 BIT 3 BIT 2 Unused R/O 0 R/O 0 BIT 1 BIT 0 RxBIP-4 Enable R/W 0 20 0 Rev2...0...0 200 BIT NUMBER 7-5 4 NAME Unused RxFERF Algo TYPE R/O R/W DESCRIPTION Receive FERF Algorithm Select: This READ/WRITE bit-field permits the user to select the "Receive FERF Declaration" and "Clearance" criteria. 0 - Receive FERF is declared if the "A" bit-field (within the incoming E3 datastream) is set to "1" for 3 consecutive frames. Receive FERF is cleared if the "A" bit-field is set to "0" for 3 consecutive frames. 1 - Receive FERF is declared if the "A" bit-field is set to "1" for 5 consecutive frames. Receive FERF is cleared if the "A" bit-field is set to "0" for 5 consecutive frames. 3-1 0 Unused RxBIP4 Enable R/O R/W Enable BIP-4 Verification: This READ/WRITE bit-field permits the user to configure the Frame Synchronizer block to verify the BIP-4 value, within the incoming E3 datastream. 0 - BIP-4 Verification is NOT performed. 1 - BIP-4 Verification is performed. 672 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 583: RxE3 Configuration and Status Register # 2 - G.751 (Address Location= 0xN311) BIT 7 RxLOF Algo R/W 0 BIT 6 RxLOF R/O 1 BIT 5 RxOOF R/O 1 BIT 4 RxLOS R/O 0 BIT 3 RxAIS R/O 0 R/O 0 BIT 2 Unused R/O 0 BIT 1 BIT 0 RxFERF R/O 1 BIT NUMBER 7 NAME RxLOF Algo TYPE R/W DESCRIPTION Receive Loss of Frame Declaration/Clearance Criteria Select: This READ/WRITE bit-field permits the user to select the Loss of Frame (LOF) Declaration and Clearance Criteria. 0 - LOF will be declared if the Frame Synchronizer block resides within the OOF (Out-of-Frame) state for 24 E3 frame periods. LOF will also be cleared once the Frame Synchronizer resides within the "In-Frame" state for 24 E3 frame period. 1 - LOF will be declared if the Frame Synchronizer block resides within the OOF state for 8 E3 frame periods. LOF will also be cleared once the Frame Synchronizer block resides within the "In-Frame" state for 8 E3 frame periods. 6 RxLOF R/O Receive Loss of Frame Defect Indicator This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring the LOF condition. 0 - Frame Synchronizer is NOT declaring an LOF condition with the incoming data stream. 1 - Frame Synchronizer is currently declaring an LOF condition with the incoming data stream. Note: This bit-field is not valid if the Frame Synchronizer block is bypassed. 5 RxOOF R/O Receive Out of Frame Defect Indicator This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring the OOF condition. 0 - Frame Synchronizer is NOT declaring an OOF condition with the incoming data stream. 1 - Frame Synchronizer is currently declaring an OOF condition with the incoming data stream. Note: This bit-field is not valid if the Frame Synchronizer block is bypassed. 4 RxLOS R/O Receive Loss of Signal Defect Indicator This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring the LOS condition. 0 - Frame Synchronizer/Channel is NOT declaring an LOS condition in the incoming data stream. 1 - Frame Synchronizer/Channel is currently declaring an LOS condition in the incoming data stream. 3 RxAIS R/O Receive AIS Defect Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently receiving an AIS signal within the incoming E3 data-stream 673 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS or not. 0 - Frame Synchronizer block is NOT detecting an AIS pattern in the incoming data stream. 1 - Frame Synchronizer block is currently detecting an AIS pattern in the incoming data stream. Note: 2-1 0 Unused RxFERF R/O R/O Receive FERF (Far-End-Receive Failure) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring a FERF condition or not. 0 - Frame Synchronizer block is NOT declaring the FERF condition. 1 - Frame Synchronizer block is declaring the FERF condition. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. This bit-field is not valid if the Frame Synchronizer block is bypassed. 20 0 Rev2...0...0 200 674 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 584: RxE3 Interrupt Enable Register # 1 - G.751 (Address Location= 0xN312) BIT 7 BIT 6 Unused BIT 5 BIT 4 COFA Interrupt Enable R/O 0 R/W 0 BIT 3 Change in OOF State Interrupt Enable R/W 0 BIT 2 Change in LOF State Interrupt Enable R/W 0 BIT 1 Change in LOS State Interrupt Enable R/W 0 BIT 0 Change in AIS State Interrupt Enable R/W 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused COFA Interrupt Enable TYPE R/O R/W DESCRIPTION Change of Framing Alignment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Framing Alignment" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime it detects a Change in Frame Alignment (e.g., the FAS bits have appeared to move to a different location in the E3 data stream). Change in OOF Condition Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the "Change in OOF (Out of Frame) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an OOF condition. * The instant that the channel clears the OOF condition. 0 - Disables the "Change in OOF Condition" Interrupt. 1 - Enables the "Change in OOF Condition" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 3 Change in OOF State Interrupt Enable R/W 2 Change in LOF State Interrupt Enable R/W Change in LOF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOF (Loss of Frame) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an LOF condition. * The instant that the channel clears the LOF condition. 0 - Disables the "Change in LOF Condition" Interrupt. 1 - Enables the "Change in LOF Condition" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 1 Change in LOS State Interrupt Enable R/W Change in LOS Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOS (Loss of Signal) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an LOS condition. * The instant that the channel clears the LOS condition. 0 - Disables the "Change in LOS Condition" Interrupt. 675 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 - Enables the "Change in LOS Condition" Interrupt. 0 Change in AIS State Interrupt Enable R/W Change in AIS Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in AIS (Alarm Indication Signal) Condition" Interrupt, within the Channel. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * The instant that the channel declares an AIS condition. * The instant that the channel clears the AIS condition. 0 - Disables the "Change in AIS Condition" Interrupt. 1 - Enables the "Change in AIS Condition" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 20 0 Rev2...0...0 200 676 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 585: RxE3 Interrupt Enable Register # 2 - G.751 (Address Location= 0xN313) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Change in FERF State Interrupt Enable R/O 0 R/O 0 R/W 0 BIT 2 Detection of BIP-4 Error Interrupt Enable R/W 0 BIT 1 Detection of FAS Bit Error Interrupt Enable R/W 0 BIT 0 Reserved R/O 0 R/O 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused Change in FERF State Interrupt Enable TYPE R/O R/W DESCRIPTION Please set to "0" (the default value) for normal operation Change in FERF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in FERF Condition" Interrupt. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime the state of the FERF condition changes. 0 - Disables the "Change in FERF Condition" Interrupt. 1 - Enables the "Change in FERF Condition" Interrupt. Note: This bit-field is ignored anytime the Frame Synchronizer block is bypassed. 2 Detection of BIP-4 Error Interrupt Enable R/W Detection of BIP-4 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of BIP-4 Error" Interrupt. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime it detects a BIP-4 error, within the incoming E3 data stream. 0 - Disables the "Detection of BIP-4 Error" Interrupt. 1 - Enables the "Detection of BIP-4 Error" Interrupt. Note: This bit-field is ignored anytime the Frame Synchronizer block is bypassed. 1 Detection of FAS Bit Error Interrupt Enable R/W Detection of FAS (Framing Alignment Signal) Bit Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "FAS Bit Error" Interrupt. If the user enables this interrupt, then the Frame Synchronizer block will generate an interrupt anytime it detects an FAS error within the incoming E3 data stream. 0 - Disables the "Detection of FAS Bit Error" Interrupt. 1 - Enables the "Detection of FAS Bit Error" Interrrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 0 Unused R/O Please set to "0" (the default value) for normal operation. 677 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 586: RxE3 Interrupt Status Register # 1 - G.751 (Address Location= 0xN314) BIT 7 BIT 6 Unused BIT 5 BIT 4 COFA Interrupt Status R/O 0 RUR 0 BIT 3 Change in OOF State Interrupt Status RUR 0 BIT 2 Change in LOF State Interrupt Status RUR 0 BIT 1 Change in LOS State Interrupt Status RUR 0 BIT 0 Change in AIS State Interrupt Status RUR 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused COFA Interrupt Status TYPE R/O RUR DESCRIPTION Change of Framing Alignment (COFA) Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of Framing Alignment (COFA) interrupt has occurred since the last read of this register. 0 - The "COFA" Interrupt has NOT occurred since the last read of this register. 1 - The "COFA" Interrupt has occurred since the last read of this register. 3 Change in OOF State Interrupt Status RUR Change of OOF (Out of Frame) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of OOF Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. * Whenever the Frame Synchronizer block declares the OOF Condition. * Whenever the Frame Synchronizer block clears the OOF Condition. 0 - The "Change in OOF Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change in OOF Condition" Interrupt has occurred since the last read of this register. Note: The user can obtain the current OOF state of the DS3/E3 Framer block by reading out the state of Bit 5 (RxOOF) within the "RxE3 Configuration and Status # 2 - G.751" (Address Location= 0xN311). 2 Change in LOF State Interrupt Status RUR Change of LOF (Loss of Frame) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOF Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. * Whenever the Frame Synchronizer block declares the LOF Condition. * Whenever the Frame Synchronizer block clears the LOF Condition. 0 - The "Change in LOF Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change in LOF Condition" Interrupt has occurred since the last read of this register. Note: The user can obtain the current LOF state of the DS3/E3 Framer block by reading out the state of Bit 6 (RxLOF) within the "RxE3 Configuration and Status # 2 - G.751" (Address Location= 0xN311). 678 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Change in LOS State Interrupt Status RUR Change of LOS (Loss of Signal) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOS Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. * Whenever the Frame Synchronizer block declares the LOS Condition. * Whenever the Frame Synchronizer block clears the LOS Condition. 0 - The "Change of LOS Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of LOS Condition" Interrupt has occurred since the last read of this register. Note: The user can obtain the current LOS state of the DS3/E3 Framer block by reading out the state of Bit 4 (RxLOS) within the "RxE3 Configuration and Status # 2 - G.751" (Address Location= 0xN311). 1 0 Change in AIS State Interrupt Status RUR Change of AIS Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. * Whenever the Frame Synchronizer block declares the AIS Condition. * Whenever the Frame Synchronizer block clears the AIS Condition. 0 - The "Change of AIS Condition" Interrupt has NOT occurred since the last read of this register. 1 - The "Change of AIS Condition" Interrupt has occurred since the last read of this register. Note: The user can obtain the current AIS state of the DS3/E3 Framer block by reading out the state of Bit 3 (RxAIS) within the "RxE3 Configuration and Status # 2 - G.751" (Address Location= 0xN311). 679 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 587: RxE3 Interrupt Status Register # 2 - G.751 (Address Location= 0xN315) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Change of FERF Condition Interrupt Status R/O 0 R/O 0 RUR 0 BIT 2 Detection of BIP-4 Error Interrupt Status RUR 0 BIT 1 Detection of FAS Bit Error Interrupt Status RUR 0 BIT 0 Reserved 20 0 Rev2...0...0 200 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused Change of FERF Condition Interrupt Status TYPE R/O RUR DESCRIPTION Change of FERF Condition Interrupt: This RESET-upon-READ bit-field indicates whether or not the "Change in FERF Condition" interrupt has occurred since the last read of this register. 0 - The "Change in FERF Condition" interrupt has NOT occurred since the last read of this register. 1 - The "Change in FERF Condition" interrupt has occurred since the last read of this register. 2 Detection of BIP-4 Error Interrupt Status RUR Detection of BIP-4 Error Interrupt: This "RESET-upon-READ" bit-field indicates whether or not the "Detection of BIP-4 Error" interrupt has occurred since the last read of this register. 0 - The "Detection of BIP-4 Error" Interrupt has NOT occurred since the last read of this register. 1 - The "Detection of BIP-4 Error" Interrupt has occurred since the last read of this register. 1 Detection of FAS Bit Error Interrupt Status RUR Detection of FAS Bit Error Interrupt: This "RESET-upon-READ" bit-field indicates whether or not the "Detection of FAS Bit Error" interrupt has occurred since the last read of this register. 0 - The "Detection of FAS Bit Error" Interrupt has NOT occurred since the last read of this register. 1 - The "Detection of FAS Bit Error" Interrupt has occurred since the last read of this register. 0 Unused R/O 680 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 588: RxE3 LAPD Control Register - G.751 (Address Location= 0xN318) BIT 7 RxLAPD Any R/W 0 BIT 6 Message Check Disable R/W 0 R/O 0 BIT 5 BIT 4 Unused BIT 3 BIT 2 RxLAPD Enable R/O 0 R/W 0 BIT 1 RxLAPD Interrupt Enable R/W 0 BIT 0 RxLAPD Interrupt Status RUR 0 R/O 0 BIT NUMBER 7 NAME RxLAPD Any TYPE R/W Receive LAPD - Any kind: DESCRIPTION This READ/WRITE bit-field permits the user to configure the LAPD Receiver to receive any kind of LAPD Message (or HDLC Message) with a size of 82 bytes or less. If the user implements this option, then the LAPD Receiver will be capable of receiving any kind of HDLC Message (with any value of header bytes). The only restriction is that the size of the HDLC Message must not exceed 82 bytes. 0 - Does not invoke this "Any Kind of HDLC Message" feature. In this case, the LAPD Receiver will only receive HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. 1 - Invokes this "Any Kind of HDLC Message" feature. In this case, the LAPD Receiver will be able to receive HDLC Messages that contain any header byte values. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. The user can determine the size (or byte count) of the most recently received LAPD/PMDL Message, by reading the contents of the "RxLAPD Byte Count" Register (Address Location= 0xN384). 6 Message Check Disable R/W Message Check Disable: This READ/WRITE bit-field permits the user to either enable or disable the new message comparison logic. If the user disables the new message comparison logic, then every message received would generate an interrupt. 0 - Enables the new message comparison logic 1 - Disables the new message comparison logic 5-3 2 Unused RxLAPD Enable R/O R/W LAPD Receiver Enable: This READ/WRITE bit-field permits the user to either enable or disable the LAPD Receiver within the channel. If the user enables the LAPD Receiver, then it will immediately begin extracting out and monitoring the data (being carried via the "DL" bits) within the incoming DS3 data stream. 0 - Enables the LAPD Receiver. 1 - Disables the LAPD Receiver. Note: 1 RxLAPD Interrupt Enable R/W This bit-field is ignored if the Frame Synchronizer block is by-passed. Receive LAPD Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive LAPD Message" Interrupt. If the user enables this interrupt, then the channel will generate an interrupt, anytime the LAPD Receiver receives a new PMDL Message. 681 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Disables the "Receive LAPD Message" Interrupt. 1 - Enables the "Receive LAPD Message" Interrupt. Note: 0 RxLAPD Interrupt Status RUR This bit-field is ignored if the Frame Synchronizer block is by-passed. 20 0 Rev2...0...0 200 Receive LAPD Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Receive LAPD Message" Interrupt has occurred since the last read of this register. 0 - "Receive LAPD Message" Interrupt has NOT occurred since the last read of this register. 1 - "Receive LAPD Message" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 682 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 589: RxE3 LAPD Status Register - G.751 (Address Location= 0xN319) BIT 7 Unused R/O 0 BIT 6 RxABORT R/O 0 BIT 5 BIT 4 BIT 3 RxCR Type R/O 0 BIT 2 RxFCS Error R/O 0 BIT 1 End of Message R/O 0 BIT 0 Flag Present R/O 0 RxLAPDType[1:0] R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused RxABORT TYPE R/O R/O DESCRIPTION Receive ABORT Sequence Indicator: This READ-ONLY bit-field indicates that the LAPD Receiver has received an ABORT sequence (e.g., a string of seven consecutive "0s"). 0 - LAPD Receiver has NOT received an ABORT sequence. 1 - LAPD Receiver has received an ABORT sequence. Note: Once the LAPD Receiver receives an ABORT sequence, it will set this bit-field "high", until it receives another LAPD Messages. 5-4 RxLAPDType[1:0] R/O Receive LAPD Message Type Indicator: These two READ-ONLY bits indicate the type of LAPD Message that is residing within the Receive LAPD Message buffer. The relationship between the content of these two bit-fields and the corresponding message type is presented below. RxLAPDType[1:0] 0 0 1 1 3 RxCR Type R/O 0 1 0 1 Message Type CL Path Identification Idle Signal Identification Test Signal Identification ITU-T Path Identification Received C/R Value: This READ-ONLY bit-field indicates the value of the C/R bit (within one of the header bytes) of the most recently received LAPD Message. 2 RxFCS Error R/O Receive Frame Check Sequence (FCS) Error Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD Message frame contained an FCS error. 0 - The most recently received LAPD Message frame does not contain an FCS error. 1 - The most recently received LAPD Message frame does contain an FCS error. 1 End of Message R/O End of Message Indicator This READ-ONLY bit-field indicates whether or not the LAPD Receiver has received a complete LAPD Message. 0 - LAPD Receiver is currently receiving a LAPD Message, but has not 683 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS received the complete message. 1 - LAPD Receiver has received a completed LAPD Message. Note: Once the LAPD Receiver sets this bit-field "high", this bit-field will remain high, until the LAPD Receiver begins to receive a new LAPD Message. 20 0 Rev2...0...0 200 0 Flag Present R/O Receive Flag Sequence Indicator: This READ-ONLY bit-field indicates whether or not the LAPD Receiver is currently receiving the Flag Sequence (e.g., a continuous stream of 0x7E octets within the Data Link channel). 0 - LAPD Receiver is NOT currently receiving the Flag Sequence octet. 1 - LAPD Receiver is currently receiving the Flag Sequence octet. Table 590: RxE3 Service Bits Register - G.751 (Address Location= 0xN31A) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 RxA R/O 0 BIT 0 RxN R/O 0 BIT NUMBER 7-2 1 NAME Unused RxA TYPE R/O R/O Received A Bit Value: DESCRIPTION This READ-ONLY bit-field reflects the value of the "A" bit, within the most recently received E3 frame. 0 RxN R/O Received N Bit Value: This READ-ONLY bit-field reflects the value of the "N" bit, within the most recently received E3 frames. 684 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RECEIVE E3, ITU-T G.832 RELATED REGISTERS 1.12.5 Table 591: RxE3 Configuration and Status Register # 1 - G.832 (Address Location= 0xN310) BIT 7 BIT 6 RxPLDType[2:0] R/O 0 R/O 1 R/O 0 BIT 5 BIT 4 RxFERF Algo. R/W 0 BIT 3 RxTMark Algo R/W 0 R/W 0 BIT 2 BIT 1 RxPLDTypeExp[2:0] R/W 1 R/W 0 BIT 0 BIT NUMBER 7-5 NAME RxPLDType[2:0] TYPE R/O DESCRIPTION Received PLD (Payload) Type[2:0]: These three READ-ONLY bit-fields reflect the value of the Payload Type bits, within the MA byte of the most recently received E3 frame. 4 RxFERF Algo R/W Receive FERF Declaration/Clearance Algorithm: This READ/WRITE bit-field permits the user to select a "Receive FERF Declaration and Clearance" Algorithm, as indicated below. 0 - The Frame Synchronizer block will declare a FERF condition if it receives the FERF indicator in 3 consecutive E3 frames. Additionally, the Frame Synchronizer block will also clear the FERF condition if it no longer receives the FERF indicator for 3 consecutive E3 frames. 1 - The Frame Synchronizer block will declare a FERF condition if it receives the FERF indicator in 5 consecutive E3 frames. Additionally, the Frame Synchronizer block will also clear the FERF condition if it no longer receives the FERF indicator for 5 consecutive E3 frames. 3 RxTMark Algo R/W Receive Timing Marker Validation Algorithm: This READ/WRITE bit-field permits the user to select the "Receive Timing Marker Validation" algorithm, as indicated below. 0 - The Timing Marker will be validated if it is of the same state for three (3) consecutive E3 frames. 1 - The Timing Marker will be validated if it is of the same state for five (5) consecutive E3 frames. 2-0 RxPLDTypExp[2:0] R/W Receive PLD (Payload) Type - Expected: This READ/WRITE bit-field permits the user to specify the "expected value" for the Payload Type, within the MA bytes of each incoming E3 frame. If the Frame Synchronizer block receives a Payload Type that differs then what has been written into these register bits, then it will generate the "Payload Type Mismatch" Interrupt. 685 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 592: RxE3 Configuration and Status Register # 2 - G.832 (Address Location= 0xN311) BIT 7 RxLOF Algo R/W 0 BIT 6 RxLOF R/O 1 BIT 5 RxOOF R/O 1 BIT 4 RxLOS R/O 0 BIT 3 RxAIS R/O 0 BIT 2 RxPLD Unstab R/O 1 BIT 1 RxTMark R/O 1 BIT 0 RxFERF R/O 1 20 0 Rev2...0...0 200 BIT NUMBER 7 NAME RxLOF Algo TYPE R/W DESCRIPTION Receive LOF (Loss of Frame) Declaration Algorithm: This READ/WRITE bit-field permits the user to select a "Receive LOF Declaration" Algorithm, as indicated below. 0 - The Frame Synchronizer will declare a Loss of Frame condition after it has resided within the "OOF" (Out of Frame) condition for 24 E3 frame periods. 1 - The Frame Synchronizer will declare a Loss of Frame condition after it has resided within the "OOF" condition for 8 E3 frame periods. 6 RxLOF R/O Receive Loss of Frame Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer is currently declaring a Loss of Frame condition, as indicated below. 0 - The Frame Synchronizer block is NOT currently declaring a Loss of Frame condition. 1 - The Frame Synchronizer block is currently declaring a Loss of Frame condition. 5 RxOOF R/O Receive Out of Frame Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer is currently declaring an Out of Frame (OOF) condition, as indicated below. 0 - The Frame Synchronizer block is NOT currently declaring an Out of Frame condition. 1 - The Frame Synchronizer block is currently declaring an Out of Frame condition. Note: The Frame Synchronizer block will declare an "OOF" condition if it detects FA1 or FA2 byte errors in four (4) consecutive "incoming" E3 frames. 4 RxLOS R/O Receive Loss of Signal Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently declaring an LOS (Loss of Signal) condition, as indicated below. 0 - The Frame Synchronizer block is NOT currently declaring an LOS condition. 1 - The Frame Synchronizer block is currently declaring an LOS condition. 3 RxAIS R/O Receive AIS Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer block is currently detecting an AIS pattern, in the incoming E3 data stream; as indicated below. 0 - The Frame Synchronizer block is NOT currently detecting an AIS pattern in the incoming E3 data stream. 1 - The Frame Synchronizer block is currently detecting an AIS pattern in the 686 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS incoming E3 data stream. Note: The Frame Synchronizer block will declare an "AIS" condition if it detects 7 or less "0s" within two consecutive "incoming" E3 frames. 2 RxPLD Unstab R/O Receive Payload-Type Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Payload Type (within the MA bytes of each incoming E3 frame) has been consistent in the last 5 frames, as indicated below. 0 - The Payload Type value has been consistent for at least 5 consecutive E3 frames. 1 - The Payload Type value has NOT been consistence for the last 5 E3 frames. 1 RxTMark R/O Received (Validated) Timing Marker: This READ-ONLY bit-field indicates the value of the most recently validated "Timing Marker". 0 RxFERF R/O Receive FERF (Far-End-Receive Failure) Indicator: This READ-ONLY bit-field indicates whether or not the Frame Synchronizer is currently declaring a FERF condition, as indicated below. 0 - The Frame Synchronizer block is NOT currently declaring a FERF condition. 1 - The Frame Synchronizer block is currently declaring a FERF condition. 687 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 593: RxE3 Interrupt Enable Register # 1 - G.832 (Address Location= 0xN312) BIT 7 Unused BIT 6 Change in SSM MSG Interrupt Enable R/W 0 BIT 5 Change in SSM OOS Interrupt Enable R/W 0 BIT 4 COFA Interrupt Enable R/W 0 BIT 3 Change in OOF State Interrupt Enable R/W 0 BIT 2 Change in LOF State Interrupt Enable R/W 0 BIT 1 Change in LOS State Interrupt Enable R/W 0 BIT 0 Change in AIS State Interrupt Enable R/W 0 20 0 Rev2...0...0 200 R/O 0 BIT NUMBER 7 6 NAME Unused Change in SSM MSG Interrupt Enable TYPE R/O R/W DESCRIPTION Change of Synchronization Status Message (SSM) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in SSM Message" Interrupt, as indicated below. 0 - Disables the "Change in SSM Message" Interrupt. 1 - Enables the "Change of SSM Message" Interrupt. In this configuration, the Frame Synchronizer block will generate an interrupt anytime it receives a new (or different) SSM Message in the incoming E3 data-stream. 5 Change in SSM OOS State Interrupt Enable R/W Change of SSM OOS (Out of Sequence) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of SSM OOS Condition" Interrupt, as indicated below. 0 - Disables the "Change of SSM OOS Condition" Interrupt. 1 - Enables the "Change of SSM OOS Condition" Interrupt. In this configuration, the Frame Synchronizer block will generate an interrupt under the following conditions. * * When the Frame Synchronizer block declares an SSM OOS condition. When the Frame Synchronizer block clears the SSM OOS condition. 4 COFA Interrupt Enable R/W Change of Framing Alignment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of Framing Alignment" condition interrupt, as indicated below. 0 - Disables the "Change of Framing Alignment" Interrupt. 1 - Enables the "Change of Framing Alignment" Interrupt. 3 Change in OOF State Interrupt Enable R/W Change of OOF (Out of Frame) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of OOF Condition" Interrupt, as indicated below. 0 - Disables the "Change of OOF Condition" Interrupt. 1 - Enables the "Change of OOF Condition" Interrupt. In this configuration, the Frame Synchronizer block will generate an 688 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS interrupt under the following conditions. * * When the Frame Synchronizer block declares an OOF condition. When the Frame Synchronizer block clears the OOF condition. 2 Change in LOF State Interrupt Enable R/W Change of LOF (Loss of Frame) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOF Condition" Interrupt, as indicated below. 0 - Disables the "Change of LOF Condition" Interrupt. 1 - Enables the "Change of LOF Condition" Interrupt. In this configuration, the Frame Synchronizer block will generate an interrupt under the following conditions. * * When the Frame Synchronizer block declares an LOF condition. When the Frame Synchronizer block clears the LOF condition. 1 Change in LOS State Interrupt Enable R/W Change of LOS (Loss of Signal) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOS Condition" Interrupt, as indicated below. 0 - Disables the "Change of LOS Condition" Interrupt. 1 - Enables the "Change of LOS Condition" Interrupt. In this configuration, the Frame Synchronizer block will generate an interrupt under the following conditions. * * When the Frame Synchronizer block declares an LOS condition. When the Frame Synchronizer block clears the LOS condition. 0 AIS Interrupt Enable R/W Change of AIS (Alarm Indication Signal) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS Condition" Interrupt, as indicated below. 0 - Disables the "Change of AIS Condition" Interrupt. 1 - Enables the "Change of AIS Condition" Interrupt. In this configuration, the Frame Synchronizer block will generate an interrupt under the following conditions. * * When the Frame Synchronizer block declares an AIS condition. When the Frame Synchronizer block clears the AIS condition. 689 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 594: RxE3 Interrupt Enable Register # 2 - G.832 (Address Location= 0xN313) BIT 7 Unused BIT 6 Change in RxTTB Message Interrupt Enable R/W 0 BIT 5 Reserved BIT 4 Detection of FEBE Event Interrupt Enable R/W 0 BIT 3 Change in FERF State Interrupt Enable R/W 0 BIT 2 Detection of BIP-8 Error Interrupt Enable R/W 0 BIT 1 Detection of Framing Byte Error Interrupt Enable R/W 0 BIT 0 RxPLD Mis Interrupt Enable R/W 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused Change in RxTTB Message Interrupt Enable TYPE R/O R/W DESCRIPTION Change in Receive Trail-Trace Buffer Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in RxTTB Message" Interrupt, as indicated below. 0 - Disables the "Change in RxTTB Message" Interrupt. 1 - Enables the "Change in RxTTB Message" Interrupt. In this mode, the Frame Synchronizer block will generate an interrupt anytime it receives a different TTB message, then what it had been receiving. 5 4 Unused Detection of FEBE Event Interrupt Enable R/W R/W Detection of FEBE Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of FEBE" Interrupt, as indicated below. 0 - Disables the "Detection of FEBE" Interrupt. 1 - Enables the "Detection of FEBE" Interrupt. In this mode, the Frame Synchronizer block will generate an interrupt anytime it detects a FEBE (Far-End Block Error) indicator in the incoming E3 data-stream. 3 Change in FERF State Interrupt Enable R/W Change of FERF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the Change of FERF Condition Interrupt, as indicated below. 0 - Disables the "Change in FERF Condition" Interrupt. 1 - Enables the "Change in FERF Condition" Interrupt. In this mode, the Frame Synchronizer block will generate an interrupt, in response to either of the following conditions. * * When the Frame Synchronizer declares a FERF condition. When the Frame Synchronizer clears the FERF condition. 2 Detection of BIP-8 Error Interrupt Enable R/W Detection of BIP-8 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of BIP-8 Error" Interrupt, as indicated below. 0 - Disables the "Detection of BIP-8 Error" Interrupt. 1 - Enables the "Detection of BIP-8 Error" Interrupt. In this mode, the Frame Synchronizer block will generate an interrupt anytime it detects a BIP-8 error in the incoming E3 data-stream. 1 Detection of Framing Byte Error Interrupt R/W Detection of Framing Byte Interrupt Enable: 690 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Enable This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Framing Byte Error" Interrupt, as indicated below. 0 - Disables the "Detection of Framing Byte Error" Interrupt. 1 - Enables the "Detection of Framing Byte Error" Interrupt. In this mode, the Frame Synchronizer block will generate an interrupt anytime it detects a FA1 or FA2 byte error in the incoming E3 data stream. 0 RxPLD Mis Interrupt Enable Received Payload Type Mismatch Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive Payload Type Mismatch" interrupt, as indicated below. 0 - Disables the "Received Payload Type Mismatch" Interrupt. 1 - Enables the "Received Payload Type Mismatch" Interrupt. In this mode, the Frame Synchronizer block will generate an interrupt anytime it receives a "Payload Type" value (within the MA byte) that differs from that written into the "RxPLDExp[2:0]" bit-fields. 691 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 595: RxE3 Interrupt Status Register # 1 - G.832 (Address Location= 0xN314) BIT 7 Unused BIT 6 Change in SSM MSG Interrupt Status RUR 0 BIT 5 Change in SSM OOS Interrupt Status RUR 0 BIT 4 COFA Interrupt Status RUR 0 BIT 3 Change in OOF State Interrupt Status RUR 0 BIT 2 Change in LOF State Interrupt Status RUR 0 BIT 1 Change in LOS State Interrupt Status RUR 0 BIT 0 Change in AIS State Interrupt Status RUR 0 20 0 Rev2...0...0 200 R/O 0 BIT NUMBER 7 6 NAME Unused Change in SSM MSG Interrupt Status TYPE R/O RUR DESCRIPTION Change in SSM (Synchronization Status Message) Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in SSM Message" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt, anytime it detects a change in the "SSM[3:0]" value that it has received via the incoming E3 datastream. 0 - Indicates that the "Change in SSM Message" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in SSM Message" Interrupt has occurred since the last read of this register. Note: The user can obtain the newly received value for "SSM" by reading out the contents of Bits 3 through 1 (RxSSM[3:0]) within the "RxE3 SSM Register - G.832" (Address Location= 0xN32C). 5 Change in SSM OOS State Interrupt Status RUR Change in SSM OOS (Out of Sequence) State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in SSM OOS State" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate the "Change in SSM OOS State" Interrupt will response to the following events. * When the DS3/E3 Frame Synchronizer block declares the SSM OOS Condition. * When the DS3/E3 Frame Synchronizer block clears the SSM OOS condition. 0 - Indicates that the "Change in SSM OOS Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in SSM OOS Condition" Interrupt has occurred since the last read of this register. 4 COFA Interrupt Status RUR COFA Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "COFA" (Change of Framing Alignment) Interrupt has occurred since the last read of this register. 692 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt anytime it detects a new "Framing Alignment" with the incoming E3 data-stream. 0 - Indicates that the "COFA Interrupt" has not occurred since the last of this register. 1 - Indicates that the "COFA Interrupt" has occurred since the last read of this register. 3 Change in OOF State Interrupt Status RUR Change in OOF (Out of Frame) State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in OOF State" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate the "Change in OOF State" Interrupt in response to the following events. * When the DS3/E3 Frame Synchronizer block declares the "OOF Condition". * When the DS3/E3 Frame Synchronizer block clears the "OOF Condition". 0 - Indicates that the "Change in OOF State Interrupt" has not occurred since the last of this register. 1 - Indicates that the "Change in OOF State Interrupt" has occurred since the last read of this register. Note: The user can determine the current state of the "AIS Condition" by reading out the contents of Bit 5 (RxOOF) within the "RxE3 Configuration and Status Register # 2 - G.832" (Address Location= 0xN311). 2 Change in LOF State Interrupt Status RUR Change in LOF (Loss of Frame) State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in LOF State" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate the "Change in LOF State" Interrupt will occur in response to the following events. * When the DS3/E3 Frame Synchronizer block declares the "LOF Condition". * When the DS3/E3 Frame Synchronizer block clears the "LOF Condition". 0 - Indicates that the "Change in LOF State Interrupt" has not occurred since the last of this register. 1 - Indicates that the "Change in LOF State Interrupt" has occurred since the last read of this register. Note: The user can determine the current state of the "AIS Condition" by reading out the contents of Bit 6 (RxLOF) within the "RxE3 Configuration and Status Register # 2 - G.832" (Address Location= 0xN311). 1 Change in LOS State Interrupt Status RUR Change in LOS (Loss of Signal) State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in LOS State" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will 693 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 generate the "Change in LOS State" Interrupt will occur in response to the following events. * When the DS3/E3 Frame Synchronizer block declares the "LOS Condition". * When the DS3/E3 Frame Synchronizer block clears the "LOS Condition". 0 - Indicates that the "Change in LOS State Interrupt" has not occurred since the last of this register. 1 - Indicates that the "Change in LOS State Interrupt" has occurred since the last read of this register. Note: The user can determine the current state of the "AIS Condition" by reading out the contents of Bit 4 (RxLOS) within the "RxE3 Configuration and Status Register # 2 - G.832" (Address Location= 0xN311). 0 Change in AIS State Interrupt Status RUR Change in AIS State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in AIS State" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate the "Change in AIS State" Interrupt will occur in response to the following events. * When the DS3/E3 Frame Synchronizer block declares the "AIS Condition". * When the DS3/E3 Frame Synchronizer block clears the "AIS Condition". 0 - Indicates that the "Change in AIS State Interrupt" has not occurred since the last of this register. 1 - Indicates that the "Change in AIS State Interrupt" has occurred since the last read of this register. Note: The user can determine the current state of the "AIS Condition" by reading out the contents of Bit 3 (RxAIS) within the "RxE3 Configuration and Status Register # 2 - G.832" (Address Location= 0xN311). 694 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 596: RxE3 Interrupt Status Register # 2 - G.832 (Address Location= 0xN315) BIT 7 Unused BIT 6 Change in RxTTB Message Interrupt Status RUR 0 BIT 5 Reserved BIT 4 Detection of FEBE Event Interrupt Status RUR 0 BIT 3 Change in FERF State Interrupt Status RUR 0 BIT 2 Detection of BIP-8 Error Interrupt Status RUR 0 BIT 1 Detection of Framing Byte Error Interrupt Status RUR 0 BIT 0 RxPLD Mis Interrupt Status RUR 0 R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused Change in RxTTB Message Interrupt Status TYPE R/O RUR DESCRIPTION Change in Receive Trail-Trace Buffer Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in RxTTB Message" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt anytime it receives a Trail-Trace Buffer Message, that is different from that of the previously received message. 0 - Indicates that the "Change in Receive TTB Message" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in Receive TTB Message" Interrupt has occurred since the last read of this register. Note: The user can obtain the value of the most recently received TTB Message by reading out the contents of the "RxE3 TTB0" through "RxE3 TTB-15" registers (Address Location= 0xN31C through 0xN32B). 5 4 Unused Detection of FEBE Event Interrupt Status R/O RUR Detection of FEBE Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of FEBE Event" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt anytime is detects a FEBE event in the incoming E3 datastream. 0 - Indicates that the "Detection of FEBE Event" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of FEBE Event" Interrupt has occurred since the last read of this register. 3 Change in FERF State Interrupt Status RUR Change in FERF (Far-End Receive Failure) State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in FERF State" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to the following events. * When the Frame Synchronizer block declares the FERF condition. * When the Frame Synchronizer block clears the FERF condition. 0 - Indicates that the "Change in FERF State" Interrupt has NOT 695 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS occurred since the last read of this register. 1 - Indicates that the "Change in FERF State" Interrupt has occurred since the last read of the register. Note: The user can obtain the state of the FERF condition, by reading out the contents of Bit 0 (RxFERF) within the "RxE3 Configuration and Status Register # 2 - G.832" (Address Location= 0xN311). 20 0 Rev2...0...0 200 2 Detection of BIP-8 Error Interrupt Status RUR Detection of BIP-8 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of BIP-8 Error" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt anytime is detects a BIP-8 Error in the incoming E3 datastream. 0 - Indicates that the "Detection of BIP-8 Error" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of BIP-8 Error" Interrupt has occurred since the last read of this register. 1 Detection of Framing Byte Error Interrupt Status RUR Detection of Framing Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Framing Byte Error" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt anytime is detects an error in either the FA1 or FA2 byte, within the incoming E3 data-stream. 0 - Indicates that the "Detection of Framing Byte Error" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Framing Byte Error" Interrupt has occurred since the last read of this register. 0 Detection of PLD Type Mismatch Interrupt Status RUR Detection of Payload Type Mismatch Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Payload Type Mismatch" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt anytime it receives an E3 data-stream that contains a "RxPLDType[2:0]" that is different from the "RxPLDTypeExp[2:0]" value. 0 - Indicates that the "Detection of Payload Type Mismatch" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Payload Type Mismatch" Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the most recently received Payload Type by reading out the contents of Bits 7 through 5 (RxPLDType[2:0]) within the "RxE3 Configuration and Status Register # 1 - G.832" (Address Location= 0xN310). 696 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 597: RxE3 LAPD Control Register - G.832 (Address Location= 0xN318) BIT 7 RxLAPD Any R/W 0 BIT 6 Message Check Disable R/W 0 R/O 0 BIT 5 Unused BIT 4 BIT 3 DL from NR Byte R/O 0 R/W 0 BIT 2 RxLAPD Enable R/W 0 BIT 1 RxLAPD Interrupt Enable R/W 0 BIT 0 RxLAPD Interrupt Status RUR 0 BIT NUMBER 7 NAME RxLAPD Any TYPE R/W Receive LAPD - Any kind: DESCRIPTION This READ/WRITE bit-field permits the user to configure the LAPD Receiver to receive any kind of LAPD Message (or HDLC Message) with a size of 82 bytes or less. If the user implements this option, then the LAPD Receiver will be capable of receiving any kind of HDLC Message (with any value of header bytes). The only restriction is that the size of the HDLC Message must not exceed 82 bytes. 0 - Does not invoke this "Any Kind of HDLC Message" feature. In this case, the LAPD Receiver will only receive HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. 1-Invokes this "Any Kind of HDLC Message" feature. In this case, the LAPD Receiver will be able to receive HDLC Messages that contain any header byte values. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. The user can determine the size (or byte count) fo the most recently received LAPD/PMDL Message, by reading the contents of the "RxLAPD Byte Count" Register (Address Location= 0xN384). 6 Message Check Disable R/W Message Check Disable: This READ/WRITE bit-field permits the user to either enable or disable the new message comparison logic. If the user disables the new message comparison logic, then every message received would generate an interrupt. 0 - Enables the new message comparison logic 1 - Disables the new message comparison logic 6-4 3 Unused DL from NR Byte R/O R/W PMDL in NR Byte Select: This READ/WRITE bit-field permits the user to configure the LAPD Receiver to extract out the PMDL data from the NR or GC byte, within the incoming E3 data stream. 0 - The LAPD Receiver will extract PMDL information from the GC byte, within the incoming E3 data stream. 1 - The LAPD Receiver will extract PMDL information from the NR byte, within the incoming E3 data stream. Note: 2 RxLAPD Enable R/W This bit-field is ignored if the Frame Synchronizer block is by-passed. LAPD Receiver Enable: This READ/WRITE bit-field permits the user to either enable or disable the LAPD Receiver within the channel. If the user enables the LAPD Receiver, then it will immediately begin extracting out and monitoring the data (being carried via the "DL" bits) within the incoming DS3 data stream. 697 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Enables the LAPD Receiver. 1 - Disables the LAPD Receiver. Note: 1 RxLAPD Interrupt Enable R/W This bit-field is ignored if the Frame Synchronizer block is by-passed. 20 0 Rev2...0...0 200 Receive LAPD Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Receive LAPD Message" Interrupt. If the user enables this interrupt, then the channel will generate an interrupt, anytime the LAPD Receiver receives a new PMDL Message. 0 - Disables the "Receive LAPD Message" Interrupt. 1 - Enables the "Receive LAPD Message" Interrupt. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 0 RxLAPD Interrupt Status RUR Receive LAPD Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Receive LAPD Message" Interrupt has occurred since the last read of this register. 0 - "Receive LAPD Message" Interrupt has NOT occurred since the last read of this register. 1 - "Receive LAPD Message" Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Frame Synchronizer block is by-passed. 698 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 598: RxE3 LAPD Status Register - G.832 (Address Location= 0xN319) BIT 7 Unused R/O 0 BIT 6 RxABORT R/O 0 BIT 5 BIT 4 BIT 3 RxCR Type R/O 0 BIT 2 RxFCS Error R/O 0 BIT 1 End of Message R/O 0 BIT 0 Flag Present R/O 0 RxLAPDType[1:0] R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused RxABORT TYPE R/O R/O DESCRIPTION Receive ABORT Sequence Indicator: This READ-ONLY bit-field indicates that the LAPD Receiver has received an ABORT sequence (e.g., a string of seven consecutive "0s"). 0 - LAPD Receiver has NOT received an ABORT sequence. 1 - LAPD Receiver has received an ABORT sequence. Note: Once the LAPD Receiver receives an ABORT sequence, it will set this bit-field "high", until it receives another LAPD Messages. 5-4 RxLAPDType[1:0] R/O Receive LAPD Message Type Indicator: These two READ-ONLY bits indicate the type of LAPD Message that is residing within the Receive LAPD Message buffer. The relationship between the content of these two bit-fields and the corresponding message type is presented below. RxLAPDType[1:0] 0 0 1 1 3 RxCR Type R/O 0 1 0 1 Message Type CL Path Identification Idle Signal Identification Test Signal Identification ITU-T Path Identification Received C/R Value: This READ-ONLY bit-field indicates the value of the C/R bit (within one of the header bytes) of the most recently received LAPD Message. 2 RxFCS Error R/O Receive Frame Check Sequence (FCS) Error Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD Message frame contained an FCS error. 0 - The most recently received LAPD Message frame does not contain an FCS error. 1 - The most recently received LAPD Message frame does contain an FCS error. 1 End of Message R/O End of Message Indicator This READ-ONLY bit-field indicates whether or not the LAPD Receiver has received a complete LAPD Message. 0 - LAPD Receiver is currently receiving a LAPD Message, but has not 699 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS received the complete message. 1 - LAPD Receiver has received a completed LAPD Message. Note: Once the LAPD Receiver sets this bit-field "high", this bit-field will remain high, until the LAPD Receiver begins to receive a new LAPD Message. 20 0 Rev2...0...0 200 0 Flag Present R/O Receive Flag Sequence Indicator: This READ-ONLY bit-field indicates whether or not the LAPD Receiver is currently receiving the Flag Sequence (e.g., a continuous stream of 0x7E octets within the Data Link channel). 0 - LAPD Receiver is NOT currently receiving the Flag Sequence octet. 1 - LAPD Receiver is currently receiving the Flag Sequence octet. 700 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 599: RxE3 NR Byte Register - G.832 (Address Location= 0xN31A) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxNR_Byte[7:0] BIT NUMBER 7-0 NAME RxNR_Byte[7:0] TYPE R/O Receive NR Byte Value: DESCRIPTION These READ-ONLY bit-fields contain the value of the NR byte, within the most recently received E3 frame. Table 600: RxE3 GC Byte Register - G.832 (Address Location= 0xN31B) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxGC_Byte[7:0] BIT NUMBER 7-0 NAME RxGC_Byte[7:0] TYPE R/O Receive GC Byte Value: DESCRIPTION These READ-ONLY bit-fields contain the value of the GC byte, within the most recently received E3 frame. Table 601: RxE3 TTB-0 Register - G.832 (Address Location= 0xN31C) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_0[7:0] BIT NUMBER 7-0 NAME RxTTB_0[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 0: These READ-ONLY bit-fields contain the contents of Byte 0 (e.g., the "Marker" Byte), within the most recently received Trail-Trace Buffer" Message. 701 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 602: RxE3 TTB-1 Register - G.832 (Address Location= 0xN31D) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 RxTTB_1[7:0] BIT NUMBER 7-0 NAME RxTTB_1[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 1: These READ-ONLY bit-fields contain the contents of Byte 1, within the most recently received Trail-Trace Buffer" Message. Table 603: RxE3 TTB-2 Register - G.832 (Address Location= 0xN31E) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_2[7:0] BIT NUMBER 7-0 NAME RxTTB_2[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 2: These READ-ONLY bit-fields contain the contents of Byte 2, within the most recently received Trail-Trace Buffer" Message. Table 604: RxE3 TTB-3 Register - G.832 (Address Location= 0xN31F) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_3[7:0] BIT NUMBER 7-0 NAME RxTTB_3[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 3: These READ-ONLY bit-fields contain the contents of Byte 3, within the most recently received Trail-Trace Buffer" Message. 702 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 605: RxE3 TTB-4 Register - G.832 (Address Location= 0xN320) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_4[7:0] BIT NUMBER 7-0 NAME RxTTB_4[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 4: These READ-ONLY bit-fields contain the contents of Byte 4, within the most recently received Trail-Trace Buffer" Message. Table 606: RxE3 TTB-5 Register - G.832 (Address Location= 0xN321) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_5[7:0] BIT NUMBER 7-0 NAME RxTTB_5[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 5: These READ-ONLY bit-fields contain the contents of Byte 5, within the most recently received Trail-Trace Buffer" Message. Table 607: RxE3 TTB-6 Register - G.832 (Address Location= 0xN322) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_6[7:0] BIT NUMBER 7-0 NAME RxTTB_6[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 6: These READ-ONLY bit-fields contain the contents of Byte 6, within the most recently received Trail-Trace Buffer" Message. 703 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 608: RxE3 TTB-7 Register - G.832 (Address Location= 0xN323) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 RxTTB_7[7:0] BIT NUMBER 7-0 NAME RxTTB_7[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 7: These READ-ONLY bit-fields contain the contents of Byte 7, within the most recently received Trail-Trace Buffer" Message. Table 609: RxE3 TTB-8 Register - G.832 (Address Location= 0xN324) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 RxTTB_8[7:0] R/O 0 R/O 0 R/O 0 R/O 0 BIT 2 BIT 1 BIT 0 BIT NUMBER 7-0 NAME RxTTB_8[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 8: These READ-ONLY bit-fields contain the contents of Byte 8, within the most recently received Trail-Trace Buffer" Message. Table 610: RxE3 TTB-9 Register - G.832 (Address Location= 0xN325) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_9[7:0] BIT NUMBER 7-0 NAME RxTTB_9[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 9: These READ-ONLY bit-fields contain the contents of Byte 9, within the most recently received Trail-Trace Buffer" Message. 704 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 611: RxE3 TTB-10 Register - G.832 (Address Location= 0xN326) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_10[7:0] BIT NUMBER 7-0 NAME RxTTB_10[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 10: These READ-ONLY bit-fields contain the contents of Byte 10, within the most recently received Trail-Trace Buffer" Message. Table 612: RxE3 TTB-11 Register - G.832 (Address Location= 0xN327) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_11[7:0] BIT NUMBER 7-0 NAME RxTTB_11[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 11: These READ-ONLY bit-fields contain the contents of Byte 11, within the most recently received Trail-Trace Buffer" Message. Table 613: RxE3 TTB-12 Register - G.832 (Address Location= 0xN328) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 RxTTB_12[7:0] R/O 0 R/O 0 R/O 0 R/O 0 BIT 2 BIT 1 BIT 0 BIT NUMBER 7-0 NAME RxTTB_12[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 12: These READ-ONLY bit-fields contain the contents of Byte 12, within the most recently received Trail-Trace Buffer" Message. 705 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 614: RxE3 TTB-13 Register - G.832 (Address Location= 0xN329) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 RxTTB_13[7:0] BIT NUMBER 7-0 NAME RxTTB_13[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 13: These READ-ONLY bit-fields contain the contents of Byte 13, within the most recently received Trail-Trace Buffer" Message. Table 615: RxE3 TTB-14 Register - G.832 (Address Location= 0xN32A) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_14[7:0] BIT NUMBER 7-0 NAME RxTTB_14[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 14: These READ-ONLY bit-fields contain the contents of Byte 14, within the most recently received Trail-Trace Buffer" Message. Table 616: RxE3 TTB-15 Register - G.832 (Address Location= 0xN32B) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxTTB_15[7:0] BIT NUMBER 7-0 NAME RxTTB_15[7:0] TYPE R/O DESCRIPTION Receive Trail-Trace Buffer Message - Byte 15: These READ-ONLY bit-fields contain the contents of Byte 15, within the most recently received Trail-Trace Buffer" Message. 706 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 617: RxE3 SSM Register - G.832 (Address Location= 0xN32C) BIT 7 RxSSM Enable R/W 0 R/O 0 BIT 6 MF[1:0] R/O 0 BIT 5 BIT 4 Reserved R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 RxSSM[3:0] R/O 0 R/O 0 BIT 0 BIT NUMBER 7 NAME RxSSM Enable TYPE R/W Receive SSM Enable: DESCRIPTION This READ/WRITE bit-field permits the user to configure the Frame Synchronizer block to operate in either the "Old ITU-T G.832 Framing" format or in the "New ITU-T G.832 Framing" format. 0 - Configures the Frame Synchronizer block to support the "Pre October 1998" version of the E3, ITU-T G.832 Framing format. 1 - Configures the Frame Synchronizer block to support the "October 1998" version of the E3, ITU-T G.832 framing format. 6-5 MF[1:0] R/O Multi-Frame Identification: These READ-ONLY bit-fields reflect the current frame number, within the Received Multi-Frame. Note: These bit-fields are only active if the DS3/E3 Frame Synchronizer block is active, and if Bit 7 (RxSSM Enable) of this register is set to "1". 4 3-0 Unused RxSSM[3:0] R/O R/O Receive Synchronization Status Message[3:0]: These READ-ONLY bit-fields reflect the content of the "SSM" bits, within the most recently received SSM Multiframe. Note: These bit-fields are only active if the DS3/E3 Frame Synchronizer block is active, and if Bit 7 (RxSSM Enable) of this register is set to "1". 707 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.12.6 TRANSMIT DS3 RELATED REGISTERS 20 0 Rev2...0...0 200 Table 618: TxDS3 Configuration Register (Address Location= 0xN330) BIT 7 Tx Yellow Alarm R/W 0 BIT 6 Tx X-Bits R/W 0 BIT 5 TxIdle R/W 0 BIT 4 TxAIS R/W 0 BIT 3 TxLOS R/W 0 BIT 2 TxFERF upon LOS R/W 0 BIT 1 TxFERF upon OOF R/W 0 BIT 0 TxFERF upon AIS R/W 0 BIT NUMBER 7 NAME Tx Yellow Alarm TYPE R/W DESCRIPTION Transmit Yellow Alarm (FERF) indicator: This READ/WRITE bit-field permits the user to force the Frame Generator block to transmit the FERF condition by setting both of the X-bits (within each outbound DS3 frame) to "0". 0 - "X" bits are set to the appropriate value, depending upon receive conditions (as detected by the Frame Synchronizer block). 1 - "X" bits are forced to "0" and the FERF indicator is transmitted to the remote terminal equipment. 6 Tx X-Bits R/W Force X bits to "1": This READ/WRITE bit-field permits the user to force the Frame Generator block to set the X-bits (within each outbound DS3 frame) to "1". 0 - "X" bits are set to the appropriate value, depending upon receive conditions (as detected by the Frame Synchronizer block). 1 - "X" bits are forced to "1". 5 TxIdle R/W Transmit DS3 Idle Signal: This READ/WRITE bit-field permits the user to force the Frame Generator block to transmit an Idle signal condition to the remote terminal equipment. 0 - Normal traffic is generated and transmitted by the Frame Generator block. 1 - Frame Generator block transmits the DS3 Idle Pattern. Note: This bit-field is ignored if "TxAIS" or "TxLOS" bit-fields are set to "1". The exact pattern that the Frame Generator transmits (whenever this bit-field is set to "1") depends upon the contents within Bits 3 through 0 (Tx_Idle_Pattern[3:0]) within the "Transmit DS3 Pattern" Register (Address Location= 0xN34C). 4 TxAIS R/W Transmit AIS Pattern: This READ/WRITE bit-field permits the user to force the Frame Generator block to transmit an AIS signal condition to the remote terminal equipment. 0 - Normal traffic is generated and transmitted by the Frame Generator block. 1 - Frame Generator block transmits the DS3 AIS Pattern. Note: This bit-field is ignored if the "TxLOS" bit-field is set to "1". When this bit-field is set to "1", it will transmit either a "Framed, repeating 1, 0, 1, 0, ..." pattern, or an "Unframed, All-Ones" pattern, depending upon the state of Bit 7 (TxAIS Unframed All Ones), within the "Transmit DS3 Pattern Register (Address Location= 0xN34C). 708 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TxLOS R/W Transmit LOS Pattern: This READ/WRITE bit-field permits the user to force the Frame Generator block to transmit an LOS signal condition to the remote terminal equipment. 0 - Normal traffic is generated and transmitted by the Frame Generator block. 1 - Frame Generator block transmits the LOS (e.g., All Zeros) Pattern. Note: This bit-field is ignored if "TxAIS" or "TxLOS" are set to "1". 3 When this bit-field is set to "1", it will transmit either an "All Zeros" pattern, or an "All Ones" pattern; depending upon the state of Bit 4 (TxLOS Pattern) within the "Transmit DS3 Pattern Register (Address Location=0xN34C). 2 TxFERF upon LOS R/W Transmit FERF upon Detection of LOS: This READ/WRITE bit-field permits the user to configure the Frame Generator block to automatically transmit the FERF indicator, anytime the Frame Synchronizer block declares an LOS condition. 0 - Frame Generator block will NOT automatically transmit the FERF indicator, upon the Frame Synchronizer detecting an LOS condition. 1 - Frame Generator block will automatically transmit the FERF indicator upon the Frame Synchronizer detecting an LOS condition. 1 TxFERF upon OOF R/W Transmit FERF upon Detection of OOF: This READ/WRITE bit-field permits the user to configure the Frame Generator block to automatically transmit the FERF indicator, anytime the Frame Synchronizer block declares an OOF condition. 0 - Frame Generator block will NOT automatically transmit the FERF indicator, upon the Frame Synchronizer detecting an OOF condition. 1 - Frame Generator block will automatically transmit the FERF indicator upon the Frame Synchronizer detecting an OOF condition. 0 TxFERF upon AIS R/W Transmit FERF upon Detection of AIS: This READ/WRITE bit-field permits the user to configure the Frame Generator block to automatically transmit the FERF indicator, anytime the Frame Synchronizer block declares an AIS condition. 0 - Frame Generator block will NOT automatically transmit the FERF indicator, upon the Frame Synchronizer detecting an AIS condition. 1 - Frame Generator block will automatically transmit the FERF indicator upon the Frame Synchronizer detecting an AIS condition. 709 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 619: TxDS3 FEAC Configuration and Status Register (Address Location= 0xN331) BIT 7 BIT 6 Unused BIT 5 BIT 4 TxFEAC Interrupt Enable R/O 0 R/W 0 BIT 3 TxFEAC Interrupt Status RUR 0 BIT 2 TxFEAC Enable R/W 0 BIT 1 TxFEAC Go BIT 0 TxFEAC Busy R/O 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 R/W 0 BIT NUMBER 7-5 4 NAME Unused TxFEAC Interrupt Enable TYPE R/O R/W DESCRIPTION Please set to "0" for normal operation. Transmit FEAC Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit FEAC" Interrupt. If the user enables this interrupt, then the Frame th Generator will generate an interrupt, once it has completed its 10 transmission of a given FEAC Message to the remote terminal equipment. 0 - Transmit FEAC Interrupt is disabled. The Frame Generator block will NOT generate an interrupt after it has completed its 10th transmission of a given FEAC Message. 1 - Transmit FEAC Interrupt is enabled. The Frame Generator block will generate an interrupt after it has completed its 10th transmission of a given FEAC Message. 3 TxFEAC Interrupt Status RUR Transmit FEAC Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit FEAC Interrupt" has occurred since the last read of this register. 0 - The Transmit FEAC Interrupt has NOT occurred since the last read of this register. 1 - The Transmit FEAC Interrupt has occurred since the last read of this register. 2 TxFEAC Enable R/W Transmit FEAC Controller Enable: This READ/WRITE bit-field permits the user to either enable or disable the Transmit FEAC Controller, within the Frame Generator block. 0 - Disables the Transmit FEAC Controller. 1 - Enables the Transmit FEAC Controller. 1 TxFEAC Go R/W Transmit FEAC Message Command: A "0" to "1" transition, within this bit-field configures the Transmit FEAC Controller to begin its transmission of the FEAC Message (which consists of the FEAC code, as specified within the "TxDS3 FEAC" Register). Note: The user is advised to perform a write operation that resets this bit-field back to "0", following execution of the command to transmit a FEAC Message. 0 TxFEAC Busy R/O Transmit FEAC Controller BUSY Indicator: This READ-ONLY bit-field indicates whether or not the Transmit FEAC Controller is currently busy transmitting a FEAC Message to the remote terminal. 0 - Transmit FEAC Controller is NOT busy. 1 - Transmit FEAC Controller is currently transmitting the FEAC Message to the 710 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS remote terminal. Table 620: TxDS3 FEAC Register (Address Location= 0xN332) BIT 7 Unused R/O 0 R/W 1 R/W 1 BIT 6 BIT 5 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 Unused R/O 0 TxFEACCode[5:0] BIT NUMBER 7 6-1 NAME Unused TxFEACCode[5:0] TYPE R/O R/W DESCRIPTION Transmit FEAC Code Word[5:0] These six (6) READ/WRITE bit-fields permit the user to specify the FEAC Code word that the Transmit FEAC Processor (within the Frame Generator block) should transmit to the remote terminal equipment. Once the user enables the "Transmit FEAC Controller" and commands it to begin its transmission, the Transmit FEAC Controller will then (1) encapsulate this six-bit code word into a 16-bit structure, (2) proceed to transmit this 16-bit structure 10 times, repeatedly, and then halt. Note: These bit-fields are ignored if the user does not enable and use the Transmit FEAC Controller. 0 Unused R/O 711 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 621: TxDS3 LAPD Configuration Register (Address Location= 0xN333) BIT 7 TxLAPD Any R/W 0 R/O 0 BIT 6 BIT 5 Unused BIT 4 BIT 3 Auto Retransmit R/O 0 R/W 1 BIT 2 Reserved BIT 1 TxLAPD Message Length R/W 0 BIT 0 TxLAPD Enable R/W 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 BIT NUMBER 7 NAME TxLAPD Any TYPE R/W Transmit LAPD - Any kind: DESCRIPTION This READ/WRITE bit-field permits the user to configure the LAPD Transmitter to transmit any kind of LAPD Message (or HDLC Message) with a size of 82 byte or less. If the user implements this option, then the LAPD Transmitter will be capable of transmitting any kind of HDLC frame (with any value of header bytes). The only restriction is that the size of the HDLC frame must not exceed 82 bytes. 0 - Does not invoke this "Any Kind of HDLC Message" feature. In this case, the LAPD Transmitter will only transmit HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. 1- Invokes this "Any Kind of HDLC Message" feature. In this case, the LAPD Transmitter will be able to transmit HDLC Messages that contain any header byte values. Note: If the user invokes the "Any Kind of HDLC Message" feature, then he/she must indicate the size of the information payload (in terms of bytes) within the "Transmit LAPD Byte Count" Register (Address Location=0xN383). 6-4 3 Unused Auto Retransmit R/O R/W Auto-Retransmit of LAPD Message: This READ/WRITE bit-field permits the user to configure the LAPD Transmitter to transmit PMDL messages, repeatedly at one-second intervals. Once the user enables this feature, and then commands the LAPD Transmitter to transmit a given PMDL Message; the LAPD Transmitter will then proceed to transmit this PMDL Message (based upon the contents within the Transmit LAPD Message Buffer) repeatedly at one second intervals. 0 - Disables the Auto-Retransmit Feature. In this case, the PMDL Message will only be transmitted once, afterwards the LAPD Transmitter will proceed to transmit a continuous stream of Flag Sequence octets (0x7E) via the DL bits, within each output DS3 frame. No more PMDL Messages will be transmitted until the user commands another transmission. 1 - Enables the Auto-Retransmit Feature. In this case, the LAPD Transmitter will transmit PMDL messages (based upon the contents within the Transmit LAPD Buffer) repeatedly at one-second intervals. Note: This bit-field is ignored if the LAPD Transmitter is disabled. 2 1 Reserved TxLAPD Message Length R/O R/W Transmit LAPD Message Length Select: This READ/WRITE bit-field permits the user to specify the length of the payload data within the outbound LAPD/PMDL Message as indicated below 712 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS data within the outbound LAPD/PMDL Message, as indicated below. 0 - Configures the LAPD Transmitter to transmit a LAPD/PMDL message that has a payload data size of 76 bytes. 1 - Configures the LAPD Transmitter to transmit a LAPD/PMDL message that has a payload data size of 82 bytes. 0 TxLAPD Enable R/W LAPD Transmitter Enable: This READ/WRITE bit-field permits the user to enable the LAPD Transmitter, within the channel. Once the user enables the LAPD Transmitter, it will immediately begin transmitting the Flag Sequence octet (0x7E) to the remote terminal via the outbound "DL" bits, within each DS3 data stream. The LAPD Transmitter will continue to do this until the user commands the LAPD Transmitter to transmit a PMDL Message. 0 - Disables the LAPD Transmitter. 1 - Enables the LAPD Transmitter. 713 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 622: TxDS3 LAPD Status/Interrupt Register (Address Location= 0xN334) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 TxDL Start R/O 0 R/O 0 R/W 0 BIT 2 TxDL Busy R/O 0 BIT 1 TxLAPD Interrupt Enable R/W 0 BIT 0 TxLAPD Interrupt Status RUR 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused TxDL Start TYPE R/O R/W DESCRIPTION Transmit LAPD Message Command: A "0" to "1" transition, within this bit-field commands the LAPD Transmitter to begin the following activities: * Reading out the contents of the Transmit LAPD Message Buffer. * Zero-Stuffing of this data * FCS Calculation and Insertion * Fragmentation of this composite PMDL Message, and insertion into the "DL" bit-fields, within each outbound DS3 frame. 2 TxDL Busy R/O Transmit LAPD Controller Busy Indicator: This "READ-ONLY" bit-field indicates whether or not the Transmit LAPD Controller is currently busy transmitting a PMDL Message to the remote terminal equipment. The user can continuously poll this bit-field in order to check for completion of transmission of the LAPD/PMDL Message. 0 - LAPD Transmitter is NOT busy transmitting a PMDL Message. 1 - LAPD Transmitter is currently busy transmitting a PMDL Message. 1 TxLAPD Interrupt Enable R/W Transmit LAPD Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit LAPD Interrupt". If the user enables this interrupt, then the channel will generate an interrupt anytime the LAPD Transmitter has completed its transmission of a given LAPD/PMDL Message to the remote terminal. 0 - Disables Transmit LAPD Interrupt. 1 - Enables Transmit LAPD Interrupt. 0 TxLAPD Interrupt Status RUR Transmit LAPD Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit LAPD Interrupt" has occurred since the last read of this register. 0 - Transmit LAPD Interrupt has NOT occurred since the last read of this register. 1 - Transmit LAPD Interrupt has occurred since the last read of this register. 714 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 623: TxDS3 M-Bit Mask Register (Address Location= 0xN335) BIT 7 BIT 6 TxFEBEDat[2:0] BIT 5 BIT 4 FEBE Register Enable R/W 0 R/W 0 BIT 3 Tx P-Bit Error R/W 0 R/W 0 BIT 2 BIT 1 TxM_Bit_Mask[2:0] BIT 0 R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7-5 NAME TxFEBEDat [2:0] TYPE R/W Transmit FEBE Value: DECRIPTION These READ/WRITE bit-fields, along with "FEBE Register Enable" permit the user to configure the Frame Generator block to transmit FEBE values (to the remote terminal) based upon the contents of these bit-fields. If the user sets the "FEBE Register Enable" bit-field to "1", then the Frame Generator block will write the contents of these bit-fields into the FEBE bits, within each outbound DS3 frame. If the user sets the "FEBE Register Enable" bit-field to "0" then these register bits will be ignored. 4 FEBE Register Enable R/W Transmit FEBE (by Software) Enable: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit FEBE values (to the remote terminal) per register setting via the "TxFEBEDat[2:0]" bit-field. This option provides the user with software control over the "outbound" FEBE values, within the DS3 data stream. 0 - Configures the Frame Generator block to transmit FEBE values based upon receive conditions, as determined by the companion Frame Synchronizer block. 1 - Configures the Frame Generator block to write the contents of the "TxFEBEDat[2:0]" bit-fields into the FEBE bits, within each "outbound" DS3 frame. 3 Tx P-Bit Error R/W Transmit P-Bit Error: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with erred P-bits, as indicated below. 0 - DS3 frames with correct P-bits are generated and transmitted to the remote terminal equipment. 1 - DS3 frames with erred P-bits are generated and transmitted to the remote terminal equipment. 2-0 TxM_Bit_ Mask[2:0] R/W Transmit M-Bit Error: These READ/WRITE bit-fields permit the user to configure the Frame Generator block to transmit DS3 frames with erred M-bits. These three (3) bit-fields correspond to the three M-bits, within each outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of these bit-fields and the value of the three M-bits. The results of this calculation will be written back into the M-bit positions within each outbound DS3 frame. The user should set these bit-fields to "0, 0, 0" for normal (e.g., un-erred) operation. 715 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 624: TxDS3 F-Bit Mask # 1 Register (; Address Location= 0xN336) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 F_Bit Mask[27]/ UDL Bit # 9 (C73) R/O 0 R/O 0 R/W 0 BIT 2 F_Bit Mask [26]/ UDL Bit # 8 (C72) R/W 0 BIT 1 F_Bit Mask [25]/ UDL Bit # 7 (C71) R/W 0 BIT 0 F_Bit Mask [24]/ 20 0 Rev2...0...0 200 Unused R/O 0 R/O 0 R/W 0 BIT NUMBER 7-4 3 NAME Unused F Bit Mask[27]/ UDL Bit # 9 (C73) TYPE R/O R/W DESCRIPTION Transmit F-Bit Error - Bit 28/UDL Bit # 9 (C73): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 28: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 28th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 28th F-bit. The results of this calculation will be written back into the 28th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 9 or C73 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit #9 (or C73)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1 - Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 2 F Bit Mask [26]/ UDL Bit #8 (C72) R/W Transmit F-Bit Error - Bit 27/UDL Bit # 8 (C72): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 27 This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 27th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 27th F-bit. The results of this calculation will be written back into the 27th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 8 or C72 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit #8 (or C72)" bit-fields, within the outbound DS3 data-stream. 716 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1 - Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 1 F Bit Mask [25]/ UDL Bit # 7 (C71) R/W Transmit F-Bit Error - Bit 26/UDL Bit # 7 (C71): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 26: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 26th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 26th F-bit. The results of this calculation will be written back into the 26th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 7 or C71 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit #7 (or C71)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1 - Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 0 F Bit Mask [24] R/W Transmit F-Bit Error - Bit 25: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. th This F-bit corresponds with the 25 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 25th F-bit. The results of this th calculation will be written back into the 25 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. Note: This bit-field is ignored if Bit 7 (TxOHSrc), within the "Test Register (Address Location= 0xN30C) is set to the "1". 717 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 625: TxDS3 F-Bit Mask # 2 Register (Address Location= 0xN337) BIT 7 F_Bit Mask [23]/ UDL Bit # 6 (C63) R/W 0 BIT 6 F_Bit Mask [22]/ UDL Bit # 5 (C62) R/W 0 BIT 5 F_Bit Mask [21]/ UDL Bit # 4 (C61) R/W 0 BIT 4 F_Bit Mask [20] BIT 3 F_Bit Mask [19]/ DL Bit # 3 (C53) R/W 0 BIT 2 F_Bit Mask [18]/ DL Bit # 2 (C52) R/W 0 BIT 1 F_Bit Mask [17]/ DL Bit # 1 (C51) R/W 0 BIT 0 F_Bit Mask [16] 20 0 Rev2...0...0 200 R/W 0 R/W 0 BIT NUMBER 7 NAME F Bit Mask[23]/ UDL Bit # 6 (C63) TYPE R/W DESCRIPTION Transmit F-Bit Error - Bit 24/UDL Bit # 6 (C63): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Indirect Address = 0xNE, 0x0C; Direct Address Address Location= 0xNFN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 24: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 24th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 24th F-bit. The results of this calculation will be written back into the 24th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 6 or C63 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit # 6 (or C63)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 6 F Bit Mask [22]/ UDL Bit # 5 (C62) R/W Transmit F-Bit Error - Bit 23/UDL Bit # 5 (C62): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 23: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. rd This F-bit corresponds with the 23 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the rd contents of this bit-field and value of the 23 F-bit. The results of this calculation will be written back into the 23rd F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 5 or C62 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit # 5 (or C62)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into 718 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 5 F Bit Mask [21]/ UDL Bit # 4 (C61) R/W Transmit F-Bit Error - Bit 22/UDL Bit # 4 (C61): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 22: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 22nd F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 22nd F-bit. The results of this nd calculation will be written back into the 22 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 4 or C61 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit # 4 (or C61)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 4 F Bit Mask [20] R/W Transmit F-Bit Error - Bit 21: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 21st F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 21st F-bit. The results of this calculation will be written back into the 21st F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. 3 F Bit Mask [19]/ DL Bit # 3 (C53) R/W Transmit F-Bit Error - Bit 20/DL Bit # 3 (C53): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 20: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 20th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the th contents of this bit-field and value of the 20 F-bit. The results of this calculation will be written back into the 20th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for DL Bit # 3 or C53 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "DL Bit # 3 (or C53)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into 719 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 2 F Bit Mask [18]/ DL Bit # 2 (C52) R/W Transmit F-Bit Error - Bit 19/DL Bit # 2 (C52): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 19: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 19th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 19th F-bit. The results of this th calculation will be written back into the 19 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for DL Bit # 2 or C52 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "DL Bit # 2 (or C52)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 1 F Bit Mask [17]/ DL Bit # 1 (C51) R/W Transmit F-Bit Error - Bit 18/DL Bit # 1 (C51): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 18: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 18th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the th contents of this bit-field and value of the 18 F-bit. The results of this th calculation will be written back into the 18 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for DL Bit # 1 or C51 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "DL Bit # 1 (or C51)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 0 F Bit Mask [16] R/W Transmit F-Bit Error - Bit 17: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 17th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 17th F-bit. The results of this 20 0 Rev2...0...0 200 720 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS calculation will be written back into the 17th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. 721 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 626: TxDS3 F-Bit Mask # 3 Register (Address Location= 0xN338) BIT 7 F_Bit Mask [15]/ FEBE Bit 3 (C43) R/W 0 BIT 6 F_Bit Mask [14]/ FEBE Bit 2 (C42) R/W 0 BIT 5 F_Bit Mask [13]/ FEBE Bit 1 (C41) R/W 0 BIT 4 F_Bit Mask [12] BIT 3 F_Bit Mask [11]/ CP Bit # 3 (C33) R/W 0 BIT 2 F_Bit Mask [10]/ CP Bit # 2 (C32) R/W 0 BIT 1 F_Bit Mask [9]/ CP Bit # 1 (C31) R/W 0 BIT 0 F_Bit Mask [8] 20 0 Rev2...0...0 200 R/W 0 R/W 0 BIT NUMBER 7 NAME F Bit Mask[15]/ FEBE Bit # 3 (C43) TYPE R/W DESCRIPTION Transmit F-Bit Error - Bit 16/FEBE Bit # 3 (C43): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 16: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. th This F-bit corresponds with the 16 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 16th F-bit. The results of this calculation will be written back into the 16th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for FEBE Bit # 3 or C43 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "FEBE Bit # 3 (or C43)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 6 F Bit Mask [14]/ FEBE Bit # 2 (C42) R/W Transmit F-Bit Error - Bit 15/FEBE Bit # 2 (C42): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 15: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. th This F-bit corresponds with the 15 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 15th F-bit. The results of this calculation will be th written back into the 15 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for FEBE Bit # 2 or C42 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "FEBE Bit # 2 (or C42)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data 722 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS into this overhead bit-field. 5 F Bit Mask [13]/ FEBE Bit 1 (C41) R/W Transmit F-Bit Error - Bit 14/FEBE Bit # 1 C41): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 14: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. th This F-bit corresponds with the 14 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 14th F-bit. The results of this calculation will be th written back into the 14 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for FEBE Bit # 1 or C41 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "FEBE Bit # 1 (or C41)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 4 F Bit Mask [12] R/W Transmit F-Bit Error - Bit 13: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. th This F-bit corresponds with the 13 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 13th F-bit. The results of this calculation will be th written back into the 13 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. 3 F Bit Mask [11]/ CP Bit # 3 (C33) R/W Transmit F-Bit Error - Bit 12/CP Bit # 3 (C33): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 12: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 12th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 12th F-bit. The results of this calculation will be written back into the 12th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for CP Bit # 3 or C33 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "CP Bit # 3 (or C33)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 723 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 2 F Bit Mask [10]/ CP Bit # 2 (C32) R/W Transmit F-Bit Error - Bit 11/CP Bit # 2 (C32): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 11: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 11th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 11th F-bit. The results of this calculation will be written back into the 11th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for CP Bit # 2 or C32 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "CP Bit # 2 (or C32)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 1 F Bit Mask [9]/ CP Bit # 1 (C31) R/W Transmit F-Bit Error - Bit 10/CP Bit # 1 (C31): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 10: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 10th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 10th F-bit. The results of this calculation will be written back into the 10th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for CP Bit # 1 or C31 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "CP Bit # 1 (or C31)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 0 F Bit Mask [8] R/W Transmit F-Bit Error - Bit 9: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 9th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 9th F-bit. The results of this calculation will be written back into the 9th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. 20 0 Rev2...0...0 200 724 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 62: TxDS3 F-Bit Mask # 4 Register (Address Location= 0xN339) BIT 7 F_Bit Mask [7]/ UDL Bit # 3 (C23) R/W 0 BIT 6 F_Bit Mask [6]/ UDL Bit # 2 (C22) R/W 0 BIT 5 F_Bit Mask [5]/ UDL Bit # 1 (C21) R/W 0 BIT 4 F_Bit Mask [4]/ X Bit # 2 R/W 0 BIT 3 F_Bit Mask [3]/ FEAC Bit (C13) R/W 0 BIT 2 F_Bit Mask [2]/ NA Bit (C12) R/W 0 BIT 1 F_Bit Mask [1]/ AIC Bit (C11) R/W 0 BIT 0 F_Bit Mask [0]/ X Bit # 1 R/W 0 BIT NUMBER 7 NAME F Bit Mask[7]/ UDL Bit # 3 (C23) TYPE R/W DESCRIPTION Transmit F-Bit Error - Bit 8/UDL Bit # 3 (C23): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 8: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 8th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 8th F-bit. The results of this calculation will be written back into the 8th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 3 or C23 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit # 3 (or C23)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 6 F Bit Mask [6]/ UDL Bit # 2 (C22) R/W Transmit F-Bit Error - Bit 7/UDL Bit # 2 (C22): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 7: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 7th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 7th F-bit. The results of this calculation will be written back into the 7th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 2 or C22 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit # 2 (or C22)" bit-fields, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data 725 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS into this overhead bit-field. 5 F Bit Mask [5]/ UDL Bit # 1 (C21) R/W Transmit F-Bit Error - Bit 6/UDL Bit # 1 (C21): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 6: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 6th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 6th F-bit. The results of this calculation will be written back into the 6th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for UDL Bit # 1 or C21 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "UDL Bit # 1 (or C21)" bit-field, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 4 F Bit Mask [4]/ X Bit # 2 R/W Transmit F-Bit Error - Bit 5/X Bit # 2: The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 5: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 5th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 5th F-bit. The results of this calculation will be written back into the 5th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for X Bit # 2: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "X-Bit # 2" bitfield, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 3 F Bit Mask [3]/ FEAC Bit (C13) R/W Transmit F-Bit Error - Bit 4/FEAC Bit (C13): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 4: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 4th F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 4th F-bit. The results of this calculation will be 20 0 Rev2...0...0 200 726 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS written back into the 4th F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for FEAC or C13 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "FEAC (or C13)" bit-field, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 2 F Bit Mask [2]/ NA Bit (C12) R/W Transmit F-Bit Error - Bit 3/NA Bit (C12): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 3: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. This F-bit corresponds with the 3rd F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 3rd F-bit. The results of this calculation will be written back into the 3rd F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for NA or C12 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "NA (or C12)" bitfield, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 1 F Bit Mask [1]/ AIC Bit (C11) R/W Transmit F-Bit Error - Bit 2/AIC Bit (C11): The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 2: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. nd This F-bit corresponds with the 2 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of nd this bit-field and value of the 2 F-bit. The results of this calculation will be nd written back into the 2 F-bit position, within each outbound DS3 frame. The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for AIC or C11 bit: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "AIC (or C11)" bit-field, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 727 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 F Bit Mask [0]/ X Bit # 1 R/W Transmit F-Bit Error - Bit 1/X Bit # 1: The exact function of this register bit depends upon whether Bit 7 (TxOHSrc), within the "Test Register" (Address Location= 0xN30C) is set to "1" or "0". If "TxOHSrc" = 0 - Transmit F-Bit Error - Bit 1: This READ/WRITE bit-field permits the user to configure the Frame Generator block to transmit DS3 frames with an erred F bit. st This F-bit corresponds with the 1 F-bit, within a given outbound DS3 frame. The Frame Generator block will perform an XOR operation with the contents of this bit-field and value of the 1st F-bit. The results of this calculation will be st written back into the 1 F-bit position, within each outbound DS3 frame. 20 0 Rev2...0...0 200 The user should set this bit-field to "0" for normal (e.g., un-erred) operation. If "TxOHSrc" = 1 - Insert Enable for X Bit # 1: This READ/WRITE bit-field permits the user to configure the Frame Generator block to externally accept an overhead bit and insert it into the "X-Bit # 1" bitfield, within the outbound DS3 data-stream. 0 - Configures the Frame Generator to externally accept and insert data into this overhead bit-field. 1- Configures the Frame Generator to NOT externally accept and insert data into this overhead bit-field. 728 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 628: Transmit DS3 Pattern Register (Address Location= 0xN34C) BIT 7 TxAIS Unframed All Ones R/W 0 R/O 0 BIT 6 Unused BIT 5 BIT 4 TxLOS Pattern R/O 0 R/W 0 R/W 1 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_Idle_Pattern[3:0] R/W 1 R/W 0 R/W 0 BIT NUMBER 7 NAME TxAIS - Unframed All Ones TYPE R/W DESCRIPTION Transmit AIS - Unframed All Ones: This READ/WRITE bit-field permits the user to configure the "Frame Generator" block to transmit either of the following pattern, anytime it is configured to transmit an AIS signal. * * A "Framed, repeating 1, 0, 1, 0... pattern (per Bellcore GR-499CORE) or An "Unframed All Ones" pattern. 0 - Configures the Frame Generator to transmit the "Framed, Repeating 1, 0, 1, 0, ... pattern; whenever it is configured to transmit an AIS pattern. 1- Configures the Frame Generator to transmit an "Unframed, All-Ones" pattern, whenever it is configured to transmit an AIS signal. 6-5 4 Unused TxLOS Pattern R/W R/W Transmit LOS Pattern: This READ/WRITE bit-field permits the user to configure the "Frame Generator" block to transmit either an "All Zeros" or an "All Ones" pattern, anytime it is configured to transmit an "LOS Pattern". 0 - Configures the Frame Generator to transmit an "All Zeros" pattern, whenever it is configured to transmit an LOS pattern. 1 - Configures the Frame Generator to transmit an "All Ones" pattern, whenever it is configured to transmit an LOS pattern. 3-0 Tx_Idle Pattern[3:0] R/W Transmit Idle Pattern: These READ/WRITE bit-fields permit the user to specify the type of pattern the Frame Generator should send, whenever it is transmitting the "DS3 Idle" pattern. Note: Setting these bit-fields to "[1, 1, 0, 0] configure the Frame Generator block to transmit a "Framed, repeating "1, 1, 0, 0, ..." pattern (per Bellcore GR-499-CORE) requirements. 729 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.12.7 TRANSMIT E3, ITU-T G.751 RELATED REGISTERS 20 0 Rev2...0...0 200 Table 629: TxE3 Configuration Register - G.751 (Address Location= 0xN330) BIT 7 TxBIP-4 Enable R/W 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 TxAIS Enable R/W 0 BIT 1 TxLOS Enable R/W 0 BIT 0 TxFAS Source Sel R/W 0 TxASrcSel[1:0] R/W 0 R/W 0 TxNSrcSel[1:0] R/W 0 R/W 0 BIT NUMBER 7 NAME TxBIP-4 Enable TYPE R/W Transmit BIP-4 Enable: DESCRIPTION This READ/WRITE bit-field permits the user to configure the Frame Generator block to do the following: * * Compute the BIP-4 value over a given E3 frame. Insert this BIP-4 value into the last nibble-field within the very next E3 frame. 0 - Does not configure this option. In this case, the last nibble (of each "outbound" E3 frame) will contain payload data. 1 - Configures the Frame Generator block to compute and insert the BIP4 value. 6-5 TxASrcSel[1:0] R/W Transmit A Bit Source Select[1:0]: These two READ/WRITE bit-fields permit the user to specify the source or type of data that is being carried via the "A" bits, within each "outbound" E3 data stream, as indicated below. TxASrcSel[1:0] 0 0 Resulting Source of A Bit The "TxA" bit-field, within the "TxE3 Service Bit" register (Address Location= 0xN335). Not Valid - Do not use. The "A" bit is sourced via the "Payload Data Input Interface" block. This is discussed in greater detail in Section _. 0 1 1 0 1 1 The Companion Frame Synchronizer block. In this case, the A bit will transmit the FEBE indicator to the remote terminal equipment. The A bit will be set to "1" when the companion Frame Synchronizer detects a BIP-4 error, and will be set to "0" when the Frame Synchronizer detects un-erred E3 frames. 4-3 TxNSrcSel[1:0] R/W Transmit N Bit Source Select[1:0]: These two READ/WRITE bit-fields permit the user to specify the source or 730 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS type of data that is being carried via the "N" bits, within each "outbound" E3 data stream, as indicated below. TxNSrcSel[1:0] 0 0 Resulting Source of N Bit The "TxN" bit-field, within the "TxE3 Service Bit" register (Address Location= 0xN335). Not Valid - Do not use. The LAPD Transmitter In this case, the N bit will function as the LAPD/PMDL channel. 0 1 1 0 1 1 The "N" bit is sourced via the "Payload Data Input Interface" block. This is discussed in greater detail in Section _. 2 TxAIS Enable R/W Transmit AIS Indicator: This READ/WRITE bit-field permits the user to (by software control) force the Frame Generator to generate and transmit the AIS indicator to the remote terminal equipment. 0 - Does not configure the Frame Generator to generate and transmit the AIS indicator. 1 - Configures the Frame Generator to generate and transmit the AIS indicator. In this case, the Frame Generator will force all bits (within the "outbound" E3 data stream) to an "All Ones" pattern. Note: This bit-field is ignored if the Frame Generator has been configured to transmit the LOS pattern. 1 TxLOS Enable R/W Transmit LOS (Pattern) Enable: This READ/WRITE bit-field permits the user to (by software control) force the Frame Generator block to transmit the LOS (Loss of Signal) pattern to the remote terminal equipment. 0 - Does not configure the Frame Generator block to generate and transmit the LOS pattern. 1 - Configures the Frame Generator block to generate and transmit the LOS pattern. In this case, the Frame Generator block will force all bits (within the "outbound" E3 data stream) to an "All Zeros" pattern. 0 TxFAS Source Sel R/W Transmit FAS Source Select: This READ/WRITE bit-field permits the user to specify the source of the FAS (Framing Alignment Signal), to be used in the "outbound" E3 datastream, as indicated below. 0 - FAS bits are inserted internally by the Frame Generator block. 1 - FAS bits are sourced by the "Payload Data Input Interface" block. This is discussed in greater detail in Section _. 731 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 630: TxE3 LAPD Configuration Register - G.751 (Address Location= 0xN333) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 Auto Retransmit R/O 0 R/O 0 R/W 1 BIT 2 Reserved BIT 1 TxLAPD Message Length R/W 0 BIT 0 TxLAPD Enable R/W 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused Auto Retransmit TYPE R/O R/W DESCRIPTION Auto-Retransmit of LAPD Message: This READ/WRITE bit-field permits the user to configure the LAPD Transmitter to transmit PMDL messages, repeatedly at one-second intervals. Once the user enables this feature, and then commands the LAPD Transmitter to transmit a given PMDL Message; the LAPD Transmitter will then proceed to transmit this PMDL Message (based upon the contents within the Transmit LAPD Message Buffer) repeatedly at one second intervals. 0 - Disables the Auto-Retransmit Feature. In this case, the PMDL Message will only be transmitted once, afterwards the LAPD Transmitter will proceed to transmit a continuous stream of Flag Sequence octets (0x7E) via the DL bits, within each output DS3 frame. No more PMDL Messages will be transmitted until the user commands another transmission. 1 - Enables the Auto-Retransmit Feature. In this case, the LAPD Transmitter will transmit PMDL messages (based upon the contents within the Transmit LAPD Buffer) repeatedly at one-second intervals. Note: This bit-field is ignored if the LAPD Transmitter is disabled. 2 1 Reserved TxLAPD Message Length R/O R/W Transmit LAPD Message Length Select: This READ/WRITE bit-field permits the user to specify the length of the payload data within the outbound LAPD/PMDL Message, as indicated below. 0 - Configures the LAPD Transmitter to transmit a LAPD/PMDL message that has a payload data size of 76 bytes. 1 - Configures the LAPD Transmitter to transmit a LAPD/PMDL message that has a payload data size of 82 bytes. 0 TxLAPD Enable R/W LAPD Transmitter Enable: This READ/WRITE bit-field permits the user to enable the LAPD Transmitter, within the channel. Once the user enables the LAPD Transmitter, it will immediately begin transmitting the Flag Sequence octet (0x7E) to the remote terminal via the outbound "DL" bits, within each DS3 data stream. The LAPD Transmitter will continue to do this until the user commands the LAPD Transmitter to transmit a PMDL Message. 0 - Disables the LAPD Transmitter. 1 - Enables the LAPD Transmitter. 732 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 631: TxE3 LAPD Status/Interrupt Register - G.751 (Address Location= 0xN334) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 TxDL Start BIT 2 TxDL Busy BIT 1 TxLAPD Interrupt Enable R/W 0 BIT 0 TxLAPD Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 R/O 0 R/W 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused TxDL Start TYPE R/O R/W DESCRIPTION Transmit LAPD Message Command: A "0" to "1" transition, within this bit-field commands the LAPD Transmitter to begin the following activities: * Reading out the contents of the Transmit LAPD Message Buffer. * Zero-Stuffing of this data * FCS Calculation and Insertion * Fragmentation of this composite PMDL Message, and insertion into the "DL" bit-fields, within each outbound DS3 frame. 2 TxDL Busy R/O Transmit LAPD Controller Busy Indicator: This "READ-ONLY" bit-field indicates whether or not the Transmit LAPD Controller is currently busy transmitting a PMDL Message to the remote terminal equipment. The user can continuously poll this bit-field in order to check for completion of transmission of the LAPD/PMDL Message. 0 - LAPD Transmitter is NOT busy transmitting a PMDL Message. 1 - LAPD Transmitter is currently busy transmitting a PMDL Message. 1 TxLAPD Interrupt Enable R/W Transmit LAPD Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit LAPD Interrupt". If the user enables this interrupt, then the channel will generate an interrupt anytime the LAPD Transmitter has completed its transmission of a given LAPD/PMDL Message to the remote terminal. 0 - Disables Transmit LAPD Interrupt. 1 - Enables Transmit LAPD Interrupt. 0 TxLAPD Interrupt Status RUR Transmit LAPD Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit LAPD Interrupt" has occurred since the last read of this register. 0 - Transmit LAPD Interrupt has NOT occurred since the last read of this register. 1 - Transmit LAPD Interrupt has occurred since the last read of this register. 733 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 632: TxE3 Service Bits Register - G.751 (Address Location= 0xN335) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 TxA R/W 0 BIT 0 TxN R/W 0 20 0 Rev2...0...0 200 BIT NUMBER 7-2 1 NAME Unused TxA TYPE R/O R/W Transmit A Bit: DESCRIPTION This READ/WRITE bit-field permits the user to control the state of the "A" bit, within each "outbound" E3 frame, as indicated below. 0 - Forces each A bit (within the "outbound" E3 frame) to "0". 1 - Forces each A bit (within the "outbound" E3 frame) to "1". Note: This bit-field is only valid if the Frame Generator block has been configured to use this bit-field as the source of the "A" bit (e.g., if "TxASrcSel[1:0] = "0, 0"). 0 TxN R/W Transmit N Bit: This READ/WRITE bit-field permits the user to control the state of the "N" bit, within each "outbound" E3 frame, as indicated below. 0 - Forces each N bit (within the "outbound" E3 frame) to "0". 1 - Forces each N bit (within the "outbound" E3 frame) to "1". Note: This bit-field is only valid if the Frame Generator block has been configured to use this bit-field as the source of the "N" bit (e.g., if "TxNSrcSel[1:0] = "0, 0"). 734 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 633: TxE3 FAS Error Mask Upper Register - G.751 (Address Location= 0xN348) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxFAS_Error_Mask_Upper[4:0] BIT NUMBER 7-5 4-0 NAME Unused TxFAS_Error_Mask_ Upper[4:0] TYPE R/O R/W DESCRIPTION TxFAS Error Mask Upper[4:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the upper five bits, within the FAS (Framing Alignment Signal), within the outbound E3 data stream. The Frame Generator will perform an XOR operation with the contents of these FAS bits, and this register. The results of this calculation will be inserted into the upper 5 FAS bit positions within the "outbound" E3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the FAS will be in error. Note: For normal operation, the user should set this register to 0x00. Table 634: TxE3 FAS Error Mask Lower Register - G.751 (Address Location= 0xN349) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxFAS_Error_Mask_Lower[4:0] BIT NUMBER 7-5 4-0 NAME Unused TxFAS_Error_Mask_Lower[4:0] TYPE R/O R/W DESCRIPTION TxFAS Error Mask Lower[4:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the lower five bits, within the FAS (Framing Alignment Signal), within the outbound E3 data stream. The Frame Generator will perform an XOR operation with the contents of these FAS bits, and this register. The results of this calculation will be inserted into the lower 5 FAS bit positions within the "outbound" E3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the FAS will be in error. Note: For normal operation, the user should set this register to 0x00. 735 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 635: TxE3 BIP-4 Mask Register - G.751 (Address Location= 0xN34A) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 TxBIP-4_Mask[3:0] BIT NUMBER 7-4 3-0 NAME Unused TxBIP-4_Mask_[3:0] TYPE R/O R/W DESCRIPTION TxBIP-4 Error Mask[3:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the BIP-4 bits, within the outbound E3 data stream. The Frame Generator will perform an XOR operation with the contents of the BIP-4 bits, and this register. The results of this calculation will be inserted into the BIP-4 bit positions within the "outbound" E3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the BIP-4 will be in error. Note: For normal operation, the user should set this register to 0x00. 736 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TRANSMIT E3, ITU-T G.832 RELATED REGISTERS 1.12.8 Table 636: TxE3 Configuration Register - G.832 (Address Location= 0xN330) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 TxDL in NR R/W 0 BIT 3 Reserved R/O 0 BIT 2 TxAIS Enable R/W 0 BIT 1 TxLOS Enable R/W 0 BIT 0 TxMA Rx R/W 0 BIT NUMBER 7-5 4 NAME Unused TxDL in NR TYPE R/O R/W DESCRIPTION Transmit DL (Data Link Channel) in NR Byte: This READ/WRITE bit-field permits the user to configure the Frame Generator to use either the NR or the GC byte as the LAPD/PMDL channel. 0 - Configures the Frame Generator to transmit all "outbound" LAPD/PMDL Messages via the GC byte. 1 - Configures the Frame Generator to transmit all "outbound" LAPD/PMDL Messages via the NR byte. 3 2 Unused TxAIS Enable R/O R/W Transmit AIS Indicator: This READ/WRITE bit-field permits the user to (by software control) force the Frame Generator to generate and transmit the AIS indicator to the remote terminal equipment. 0 - Does not configure the Frame Generator to generate and transmit the AIS indicator. 1 - Configures the Frame Generator to generate and transmit the AIS indicator. In this case, the Frame Generator will force all bits (within the "outbound" E3 data stream) to an "All Ones" pattern. Note: This bit-field is ignored if the Frame Generator has been configured to transmit the LOS pattern. 1 TxLOS Enable R/W Transmit LOS (Pattern) Enable: This READ/WRITE bit-field permits the user to (by software control) force the Frame Generator block to transmit the LOS (Loss of Signal) pattern to the remote terminal equipment. 0 - Does not configure the Frame Generator block to generate and transmit the LOS pattern. 1 - Configures the Frame Generator block to generate and transmit the LOS pattern. In this case, the Frame Generator block will force all bits (within the "outbound" E3 data stream) to an "All Zeros" pattern. 0 TxMA Rx R/W Transmit MA Byte from Receiver (Frame Synchronizer) Select: This READ/WRITE bit-field permits the user to configure the Frame Generator block to use either the Frame Synchronizer block or the "Tx MA Byte" Register as the source of the FERF and FEBE bit-fields (within the MA byte-field of the "outbound" E3 data stream); as indicated below. 0 - Configures the Frame Generator to read in the contents of the "Tx MA Byte" register (Address Location= 0xN336), and write it into the "MA" byte-field 737 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS within each "outbound" E3 frame. Note: This option permits the user to send FERF and FEBE indicators, under software control. 20 0 Rev2...0...0 200 1 - Configures the Frame Generator to set the FERF and FEBE bit-fields to values, based upon conditions detected by the companion Frame Synchronizer block. 738 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 637: TxE3 LAPD Configuration Register - G.832 (Address Location= 0xN333) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Auto Retransmit R/O 0 R/O 0 R/W 1 BIT 2 Reserved R/O 0 BIT 1 TxLAPD Message Length R/W 0 BIT 0 TxLAPD Enable R/W 0 Unused R/O 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused Auto Retransmit TYPE R/O R/W DESCRIPTION Auto-Retransmit of LAPD Message: This READ/WRITE bit-field permits the user to configure the LAPD Transmitter to transmit PMDL messages, repeatedly at one-second intervals. Once the user enables this feature, and then commands the LAPD Transmitter to transmit a given PMDL Message; the LAPD Transmitter will then proceed to transmit this PMDL Message (based upon the contents within the Transmit LAPD Message Buffer) repeatedly at one second intervals. 0 - Disables the Auto-Retransmit Feature. In this case, the PMDL Message will only be transmitted once, afterwards the LAPD Transmitter will proceed to transmit a continuous stream of Flag Sequence octets (0x7E) via the DL bits, within each output DS3 frame. No more PMDL Messages will be transmitted until the user commands another transmission. 1 - Enables the Auto-Retransmit Feature. In this case, the LAPD Transmitter will transmit PMDL messages (based upon the contents within the Transmit LAPD Buffer) repeatedly at one-second intervals. Note: This bit-field is ignored if the LAPD Transmitter is disabled. 2 1 Reserved TxLAPD Message Length R/O R/W Transmit LAPD Message Length Select: This READ/WRITE bit-field permits the user to specify the length of the payload data within the outbound LAPD/PMDL Message, as indicated below. 0 - Configures the LAPD Transmitter to transmit a LAPD/PMDL message that has a payload data size of 76 bytes. 1 - Configures the LAPD Transmitter to transmit a LAPD/PMDL message that has a payload data size of 82 bytes. 0 TxLAPD Enable R/W LAPD Transmitter Enable: This READ/WRITE bit-field permits the user to enable the LAPD Transmitter, within the channel. Once the user enables the LAPD Transmitter, it will immediately begin transmitting the Flag Sequence octet (0x7E) to the remote terminal via the outbound "DL" bits, within each DS3 data stream. The LAPD Transmitter will continue to do this until the user commands the LAPD Transmitter to transmit a PMDL Message. 0 - Disables the LAPD Transmitter. 1 - Enables the LAPD Transmitter. Table 638: TxE3 LAPD Status/Interrupt Register - G.832 (Address Location= 0xN334) 739 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 TxDL Start BIT 2 TxDL Busy BIT 1 TxLAPD Interrupt Enable R/W 0 20 0 Rev2...0...0 200 BIT 0 TxLAPD Interrupt Status RUR 0 R/O 0 R/O 0 R/O 0 R/O 0 R/W 0 R/O 0 BIT NUMBER 7-4 3 NAME Unused TxDL Start TYPE R/O R/W DESCRIPTION Transmit LAPD Message Command: A "0" to "1" transition, within this bit-field commands the LAPD Transmitter to begin the following activities: * Reading out the contents of the Transmit LAPD Message Buffer. * Zero-Stuffing of this data * FCS Calculation and Insertion * Fragmentation of this composite PMDL Message, and insertion into the "DL" bit-fields, within each outbound DS3 frame. 2 TxDL Busy R/O Transmit LAPD Controller Busy Indicator: This "READ-ONLY" bit-field indicates whether or not the Transmit LAPD Controller is currently busy transmitting a PMDL Message to the remote terminal equipment. The user can continuously poll this bit-field in order to check for completion of transmission of the LAPD/PMDL Message. 0 - LAPD Transmitter is NOT busy transmitting a PMDL Message. 1 - LAPD Transmitter is currently busy transmitting a PMDL Message. 1 TxLAPD Interrupt Enable R/W Transmit LAPD Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Transmit LAPD Interrupt". If the user enables this interrupt, then the channel will generate an interrupt anytime the LAPD Transmitter has completed its transmission of a given LAPD/PMDL Message to the remote terminal. 0 - Disables Transmit LAPD Interrupt. 1 - Enables Transmit LAPD Interrupt. 0 TxLAPD Interrupt Status RUR Transmit LAPD Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Transmit LAPD Interrupt" has occurred since the last read of this register. 0 - Transmit LAPD Interrupt has NOT occurred since the last read of this register. 1 - Transmit LAPD Interrupt has occurred since the last read of this register. 740 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 639: TxE3 GC Byte Register - G.832 (Address Location= 0xN335) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxGC_Byte[7:0] BIT NUMBER 7-0 NAME TxGC_Byte[7:0] TYPE R/W Transmit GC Byte: DESCRIPTION This READ/WRITE bit-field permits the user to specify the contents of the GC byte, within the "outbound" E3 data stream. The Frame Generator block will load the contents of this register in the GC byte-field, within each outbound E3 frame. Note: This register is ignored if the GC byte is configured to be the "LAPD/PMDL" channel. Table 640: TxE3 MA Byte Register - G.832 (Address Location= 0xN336) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 1 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxMA Byte[7:0] BIT NUMBER 7-0 NAME TxMA_Byte[7:0] TYPE R/W Transmit MA Byte: DESCRIPTION This READ/WRITE bit-field permits the user to specify the contents of the MA byte, within the "outbound" E3 data stream. The Frame Generator block will load the contents of this register in the MA byte-field, within each outbound E3 frame. Note: This register is ignored if the "Transmit MA Byte - from Receiver" option is selected (e.g., by setting "TxMA Rx = 1"). This feature permits the user to transmit FERF and FEBE indicators upon software command. 741 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 641: TxE3 NR Byte Register - G.832 (Address Location= 0xN337) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME TxNR_Byte[7:0] BIT 5 R/W 0 TYPE R/W Transmit NR Byte: This READ/WRITE bit-field permits the user to specify the contents of the NR byte, within the "outbound" E3 data stream. The Frame Generator block will load the contents of this register in the NR byte-field, within each outbound E3 frame. Note: This register is ignored if the NR byte is configured to be the "LAPD/PMDL" channel. BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 TxNR_Byte[7:0] Table 642: TxE3 TTB-0 Register - G.832 (Address Location= 0xN338) BIT 7 R/W 1 BIT NUMBER 7-0 BIT 6 R/W 0 NAME TxTTB_Byte_0[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 0: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 0" within the outbound E3 data stream. By default, the MSB (Most Significant Bit) of this register bit will be set to "1" in order to permit the remote terminal to be able to identify this particular byte, as being the first byte of the "Trail-Trace Buffer" Message. BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_0 Table 643: TxE3 TTB-1 Register - G.832 (Address Location = 0xN339) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME TxTTB_Byte_1[7:0] BIT 5 R/W 0 TYPE R/W BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 1: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 1" within the outbound E3 data stream. BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_1 742 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 644: TxE3 TTB-2 Register - G.832 (Address Location= 0xN33A) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_2 BIT NUMBER 7-0 NAME TxTTB_Byte_2[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 2: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 2" within the outbound E3 data stream. Table 645: TxE3 TTB-3 Register - G.832 (Address Location= 0xN33B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_3 BIT NUMBER 7-0 NAME TxTTB_Byte_3[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 3: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 3" within the outbound E3 data stream. Table 646: TxE3 TTB-4 Register - G.832 (Address Location= 0xN33C) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_4 BIT NUMBER 7-0 NAME TxTTB_Byte_4[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 4: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 4" within the outbound E3 data stream. 743 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 647: TxE3 TTB-5 Register - G.832 (Address Location= 0xN33D) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 TxTTB_Byte_5 BIT NUMBER 7-0 NAME TxTTB_Byte_5[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 5: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 5" within the outbound E3 data stream. Table 648: TxE3 TTB-6 Register - G.832 (Address Location= 0xN33E) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_6 BIT NUMBER 7-0 NAME TxTTB_Byte_6[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 6: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 6" within the outbound E3 data stream. Table 649: TxE3 TTB-7 Register - G.832 (Address Location= 0xN33F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_7 BIT NUMBER 7-0 NAME TxTTB_Byte_7[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 7: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 7" within the outbound E3 data stream. 744 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 650: TxE3 TTB-8 Register - G.832 (Address Location = 0xN340) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_8 BIT NUMBER 7-0 NAME TxTTB_Byte_8[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 8: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 8" within the outbound E3 data stream. Table 651: TxE3 TTB-9 Register - G.832 (Address Location= 0xN341) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_9 BIT NUMBER 7-0 NAME TxTTB_Byte_9[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 9: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 9" within the outbound E3 data stream. Table 652: TxE3 TTB-10 Register - G.832 (Address Location= 0xN342) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_10 BIT NUMBER 7-0 NAME TxTTB_Byte_10[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 10: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 10" within the outbound E3 data stream. 745 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 653: TxE3 TTB-11 Register - G.832 (Address Location= 0xN343) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 TxTTB_Byte_11 BIT NUMBER 7-0 NAME TxTTB_Byte_11[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 11: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 11" within the outbound E3 data stream. Table 654: TxE3 TTB-12 Register - G.832 (Address Location= 0xN344) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_12 BIT NUMBER 7-0 NAME TxTTB_Byte_12[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 12: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 12" within the outbound E3 data stream. Table 655: TxE3 TTB-13 Register - G.832 (Address Location= 0xN345) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_13 BIT NUMBER 7-0 NAME TxTTB_Byte_13[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 13: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 13" within the outbound E3 data stream. 746 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 656: TxE3 TTB-14 Register - G.832 (Address Location= 0xN346) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_14 BIT NUMBER 7-0 NAME TxTTB_Byte_14[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 14: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 14" within the outbound E3 data stream. Table 657: TxE3 TTB-15 Register - G.832 (Address Location= 0xN347) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxTTB_Byte_15 BIT NUMBER 7-0 NAME TxTTB_Byte_15[7:0] TYPE R/W DESCRIPTION Transmit TTB (Trail-Trace Buffer) Byte 15: These READ/WRITE bits permit the user to specify the contents of "Trail-Trace Buffer Byte 15" within the outbound E3 data stream. 747 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 658: TxE3 FA1 Error Mask Register - G.832 (Address Location= 0xN348) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 TxFA1_Mask_Byte[7:0] BIT NUMBER 7-0 NAME TxFA1_Mask_Byte[7:0] TYPE R/W DESCRIPTION TxFA1 Error Mask Byte[7:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the FA1 bytes, within the outbound E3 data stream. The Frame Generator will perform an XOR operation with the contents of the FA1 byte, and this register. The results of this calculation will be inserted into the FA1 byte position within the "outbound" E3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the FA1 byte will be in error. Note: For normal operation, the user should set this register to 0x00. Table 659: TxE3 FA2 Error Mask Register - G.832 (Address Location= 0xN349) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxFA2_Mask_Byte[7:0] BIT NUMBER 7-0 NAME TxFA2_Mask_Byte[7:0] TYPE R/W DESCRIPTION TxFA2 Error Mask Byte[7:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the FA2 bytes, within the outbound E3 data stream. The Frame Generator will perform an XOR operation with the contents of the FA2 byte, and this register. The results of this calculation will be inserted into the FA2 byte position within the "outbound" E3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the FA2 byte will be in error. Note: For normal operation, the user should set this register to 0x00. 748 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 660: TxE3 BIP-8 Error Mask Register - G.832 (Address Location= 0xN34A) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxBIP-8_Mask_Byte[7:0] BIT NUMBER 7-0 NAME TxBIP-8_Mask_Byte[7:0] TYPE R/W DESCRIPTION TxBIP-8 (B1) Error Mask[7:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the B1 bytes, within the outbound E3 data stream. The Frame Generator will perform an XOR operation with the contents of the B1 byte, and this register. The results of this calculation will be inserted into the B1 byte position within the "outbound" E3 data stream. For each bit-field (within this register) that is set to "1", the corresponding bit, within the B1 byte will be in error. Note: For normal operation, the user should set this register to 0x00. Table 661: TxE3 SSM Register - G.832 (Address Location= 0xN34B) BIT 7 TxSSM Enable R/W 0 R/O 0 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/W 0 R/W 0 BIT 4 BIT 3 BIT 2 BIT 1 R/W 0 BIT 0 R/W 0 TxSSM[3:0] BIT NUMBER 7 NAME TxSSM Enable TYPE R/W DESCRIPTION Transmit SSM Enable: This READ/WRITE bit-field permits the user to configure the Frame Generator block to operate in either the "Old ITU-T G.832 Framing" format or in the "New ITU-T G.832 Framing" format. 0 - Configures the Frame Generator block to support the "Pre October 1998" version of the E3, ITU-T G.832 framing format. 1 - Configures the Frame Generator block to support the "October 1998" version of the E3, ITU-T G.832 framing format. 6-4 3-0 Unused TxSSM[3:0] R/O R/W Transmit Synchronization Status Message[3:0]: These READ/WRITE bit-fields permit the user to exercise software control over the contents of the "SSM" bits, within the MA byte of the "outbound" E3 data-stream. Note: These bit-fields are only active if the DS3/E3 Frame Generator block is active, and if Bit 7 (TxSSM Enable) of this register is set to "1". 1.12.9 AIS/PDI-P ALARM ENABLE REGISTER Table 662: Receive DS3/E3 AIS/PDI-P Alarm Enable Register (Address Location= 0xN34D) 749 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS BIT 7 BIT 6 BIT 5 Transmit PDIP(Downstream) upon LOS R/W 0 NAME Unused Transmit PDI-P (Down-stream) upon LOS TYPE R/O R/W Transmit PDI-P (Down-stream) upon LOS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block and the Transmit SONET POH Processor block to automatically transmit the PDI-P (Path - Payload Defect Indicator) anytime the LOS defect is declared within the DS3 Ingress Path. More specifically, if this configuration is implemented then the following events will occur. If the Primary Frame Synchronizer block is operating the in "DS3/E3 Ingress" path If the Primary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the LOS defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator, by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0xFC". Once the Primary Frame Synchronizer block clears the LOS defect, then the Transmit SONET POH Processor block will automatically setting the C2 byte (within each "down-stream" STS-1 SPE) to the "0x04". If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the LOS defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0xFC". Once the Secondary Frame Synchronizer block clears the LOS defect, then the Transmit SONET POH Processor block will automatically terminate its transmission of the PDI-P indicator by setting the C2 byte (within each "down-stream" STS-1 SPE) to the value "0x04". 0 - Disables this "Transmit PDI-P (Down-stream) upon LOS feature. 1 - Enables this "Transmit PDI-P (Down-stream) upon LOS feature. 4 Transmit AIS (Down-stream) upon LOS R/W Transmit AIS (Down-stream) upon LOS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to do all of the following, if the LOS defect is declared. If the Primary Frame Synchronizer block declares LOS: If the Primary Frame Synchronizer block declares the LOS detect (within its Receive Path) then it will automatically transmit the AIS indicator, via its output Path. If the Secondary Frame Synchronizer block declares LOS: If the Secondary Frame Synchronizer block declares the LOS defect (within its Receive Path) then it will automatically force the "Frame 0 BIT 4 Transmit AIS (Downstream) upon LOS R/W 0 BIT 3 Transmit PDIP (Downstream) upon LOF R/W 0 BIT 2 Transmit AIS (Downstream) upon LOF R/W 0 DESCRIPTION BIT 1 Transmit PDIP (Downstream) upon AIS R/W 0 20 0 Rev2...0...0 200 BIT 0 Transmit AIS (Downstream) upon AIS R/W 0 Unused R/O 0 BIT NUMBER 7-6 5 R/O 750 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Generator" block to generate and transmit the AIS indicator. 0 - Disables the "Transmit AIS (Down-stream) upon LOS feature. 1 - Enables the "Transmit AIS (Down-stream) upon LOS feature. 3 Transmit PDI-P (Down-stream) upon LOF R/W Transmit PDI-P (Down-stream) upon LOF: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block and the Transmit SONET POH Processor block to automatically transmit the PDI-P (Path - Payload Defect Indicator) anytime the LOF defect is declared within the DS3 Ingress Path. More specifically, if this configuration is implemented then the following events will occur. If the Primary Frame Synchronizer block is operating the in "DS3/E3 Ingress" path If the Primary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the LOF defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator, by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0xFC". Once the Primary Frame Synchronizer block clears the LOF defect, then the Transmit SONET POH Processor block will automatically setting the C2 byte (within each "down-stream" STS-1 SPE) to the "0x04". If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the LOF defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0xFC". Once the Secondary Frame Synchronizer block clears the LOF defect, then the Transmit SONET POH Processor block will automatically terminate its transmission of the PDI-P indicator by setting the C2 byte (within each "down-stream" STS-1 SPE) to the value "0x04". 0 - Disables this "Transmit PDI-P (Down-stream) upon LOF feature. 1 - Enables this "Transmit PDI-P (Down-stream) upon LOF feature. 2 Transmit AIS (Down-stream) upon LOF R/W Transmit AIS (Down-stream) upon LOF: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to do all of the following, if the LOF defect is declared. If the Primary Frame Synchronizer block declares LOF: If the Primary Frame Synchronizer block declares the LOF detect (within its Receive Path) then it will automatically transmit the AIS indicator, via its output Path. If the Secondary Frame Synchronizer block declares LOS: If the Secondary Frame Synchronizer block declares the LOF defect (within its Receive Path) then it will automatically force the "Frame Generator" block to generate and transmit the AIS indicator. 0 - Disables the "Transmit AIS (Down-stream) upon LOF feature. 1 - Enables the "Transmit AIS (Down-stream) upon LOF feature. 1 Transmit PDI-P (Down-stream) upon AIS R/W Transmit PDI-P (Down-stream) upon AIS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block and the Transmit SONET POH Processor block to 751 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 automatically transmit the PDI-P (Path - Payload Defect Indicator) anytime the AIS defect is declared within the DS3 Ingress Path. More specifically, if this configuration is implemented then the following events will occur. If the Primary Frame Synchronizer block is operating the in "DS3/E3 Ingress" path If the Primary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the AIS defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator, by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0xFC". Once the Primary Frame Synchronizer block clears the AIS defect, then the Transmit SONET POH Processor block will automatically setting the C2 byte (within each "down-stream" STS-1 SPE) to the "0x04". If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the AIS defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0xFC". Once the Secondary Frame Synchronizer block clears the AIS defect, then the Transmit SONET POH Processor block will automatically terminate its transmission of the PDI-P indicator by setting the C2 byte (within each "down-stream" STS-1 SPE) to the value "0x04". 0 - Disables this "Transmit PDI-P (Down-stream) upon AIS feature. 1 - Enables this "Transmit PDI-P (Down-stream) upon AIS feature. 0 Transmit AIS (Down-stream) upon AIS R/W Transmit AIS (Down-stream) upon AIS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to do all of the following, if the AIS defect is declared. If the Primary Frame Synchronizer block declares AIS: If the Primary Frame Synchronizer block declares the AIS detect (within its Receive Path) then it will automatically transmit the AIS indicator, via its output Path. If the Secondary Frame Synchronizer block declares AIS: If the Secondary Frame Synchronizer block declares the AIS defect (within its Receive Path) then it will automatically force the "Frame Generator" block to generate and transmit the AIS indicator. 0 - Disables the "Transmit AIS (Down-stream) upon AIS feature. 1 - Enables the "Transmit AIS (Down-stream) upon AIS feature. 752 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 663: Receive DS3/E3 AIS/PDI-P Alarm Enable Register - Secondary Frame Synchronizer (Address Location= 0xN3F2) BIT 7 BIT 6 BIT 5 Transmit PDIP (Downstream) upon LOS R/W 0 NAME Unused Transmit PDIP (Downstream) upon LOS TYPE R/O R/W Transmit PDI-P (Down-stream) upon LOS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block and the Transmit SONET POH Processor block to automatically transmit the PDI-P (Path - Payload Defect Indicator) anytime the LOS defect is declared within the DS3 Ingress Path. If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the LOS defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator by setting the C2 byte (within each "down-stream" STS-1 SPE) to the value "0xFC". Once the Secondary Frame Synchronizer block clears the LOS defect, then the Transmit SONET POH Processor block will automatically terminate its transmission of the PDI-P indicator by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0x04". 0 - Disables this "Transmit PDI-P (Down-stream) upon LOS feature. 1 - Enables this "Transmit PDI-P (Down-stream) upon LOS feature. 4 Transmit AIS (Down-stream) upon LOS R/W Transmit AIS (Down-stream) upon LOS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to do the following, if the LOS defect is declared. If the Secondary Frame Synchronizer block declares LOS: If the Secondary Frame Synchronizer block declares the LOS defect (within its Receive Path) then it will automatically force the "Frame Generator" block to generate and transmit the AIS indicator. 0 - Disables the "Transmit AIS (Down-stream) upon LOS feature. 1 - Enables the "Transmit AIS (Down-stream) upon LOS feature. 3 Transmit PDIP (Downstream) upon LOF R/W Transmit PDI-P (Down-stream) upon LOF: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block and the Transmit SONET POH Processor block to automatically transmit the PDI-P (Path - Payload Defect Indicator) anytime the LOF defect is declared within the DS3 Ingress Path. If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the LOF defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator by setting the C2 byte (within each "down-stream" STS-1 SPE) to the 0 BIT 4 Transmit AIS (Downstream) upon LOS R/W 0 BIT 3 Transmit PDIP (Downstream) upon LOF R/W 0 BIT 2 Transmit AIS (Downstream) upon LOF R/W 0 DESCRIPTION BIT 1 Transmit PDIP (Downstream) upon AIS R/W 0 BIT 0 Transmit AIS (Downstream) upon AIS R/W 0 Unused R/O 0 BIT NUMBER 7-6 5 R/O 753 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS value "0xFC". Once the Secondary Frame Synchronizer block clears the LOF defect, then the Transmit SONET POH Processor block will automatically terminate its transmission of the PDI-P indicator by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0x04". 0 - Disables this "Transmit PDI-P (Down-stream) upon LOF feature. 1 - Enables this "Transmit PDI-P (Down-stream) upon LOF feature. 2 Transmit AIS (Down-stream) upon LOF R/W Transmit AIS (Down-stream) upon LOF: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to do the following, if the LOF defect is declared. If the Secondary Frame Synchronizer block declares LOS: If the Secondary Frame Synchronizer block declares the LOF defect (within its Receive Path) then it will automatically force the "Frame Generator" block to generate and transmit the AIS indicator. 0 - Disables the "Transmit AIS (Down-stream) upon LOF feature. 1 - Enables the "Transmit AIS (Down-stream) upon LOF feature. 1 Transmit PDIP (Downstream) upon AIS R/W Transmit PDI-P (Down-stream) upon AIS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block and the Transmit SONET POH Processor block to automatically transmit the PDI-P (Path - Payload Defect Indicator) anytime the AIS defect is declared within the DS3 Ingress Path. If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path If the Secondary Frame Synchronizer block is operating in the "DS3/E3 Ingress" path, and if it were to declare the AIS defect (within the Ingress Path), then the Transmit SONET POH Processor block will automatically transmit the PDI-P indicator by setting the C2 byte (within each "down-stream" STS-1 SPE) to the value "0xFC". Once the Secondary Frame Synchronizer block clears the AIS defect, then the Transmit SONET POH Processor block will automatically terminate its transmission of the PDI-P indicator by setting the C2 byte (within each "downstream" STS-1 SPE) to the value "0x04". 0 - Disables this "Transmit PDI-P (Down-stream) upon AIS feature. 1 - Enables this "Transmit PDI-P (Down-stream) upon AIS feature. 0 Transmit AIS (Down-stream) upon AIS R/W Transmit AIS (Down-stream) upon AIS: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to do the following, if the AIS defect is declared. If the Secondary Frame Synchronizer block declares AIS: If the Secondary Frame Synchronizer block declares the AIS defect (within its Receive Path) then it will automatically force the "Frame Generator" block to generate and transmit the AIS indicator. 0 - Disables the "Transmit AIS (Down-stream) upon AIS feature. 1 - Enables the "Transmit AIS (Down-stream) upon AIS feature. 20 0 Rev2...0...0 200 754 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS PERFORMANCE MONITOR REGISTERS 1.12.10 Table 664: PMON Excessive Zero Count Registers - MSB (Address Location= 0xN34E) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_EXZ_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_EXZ_Count_Upper_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - Excessive Zero Event Count - Upper Byte: These RESET-upon-READ bits, along with that within the "PMON Excessive Zero Count Register - LSB" combine to reflect the cumulative number of instances that a string of three or more consecutive zeros (for DS3 applications) or four or more consecutive zeros (for E3 applications) has been detected by the "Primary Frame Synchronizer" block since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Table 665: PMON Excessive Zero Count Registers - LSB (Address Location= 0xN34F) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_EXZ_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_EXZ_Count_Upper_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - Excessive Zero Event Count - Lower Byte: These RESET-upon-READ bits, along with that within the "PMON Excessive Zero Count Register - MSB" combine to reflect the cumulative number of instances that a string of three or more consecutive zeros (for DS3 applications) or four or more consecutive zeros (for E3 applications) has been detected by the "Primary Frame Synchronizer" block since the last read of this register. This register contains the Least Significant byte of this 16-bit expression. 755 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 666: PMON Line Code Violation Count Registers - MSB (Address Location= 0xN350) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 20 0 Rev2...0...0 200 PMON_LCV_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON LCV Count Upper Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor- Line Code Violation Count Register - Upper Byte: These RESET-upon-READ bits along with that within the "PMON Line Code Violation Count - LSB" combine to reflect the cumulative number of Line Code Violations that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Table 667: PMON Line Code Violation Count Registers - LSB (Address Location= 0xN351) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_LCV_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON LCV Count Lower Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor- Line Code Violation Count Register - Lower Byte: These RESET-upon-READ bits along with that within the "PMON Line Code Violation Count - MSB" combine to reflect the cumulative number of Line Code Violations that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Least Significant byte of this 16-bit expression. 756 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 668: PMON Framing Bit/Byte Error Count Register - MSB (Address Location= 0xN352) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_Framing_Bit/Byte_Error_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_Framing Bit/Byte Error_Count_Upper Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - Framing Bit/Byte Error Count - Upper Byte: These RESET-upon-READ bits, along with that within the "PMON Framing Bit/Byte Error Count Register - LSB" combine to reflect the cumulative number of Framing bit (or byte) errors that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Note: For DS3 applications, this register will increment for each F or M bit error detected. For E3, ITU-T G.751 applications, this register will increment for each FAS error detected. For E3, ITU-T G.832 applications, this register will increment for each FA1 or FA2 byte error detected. These register bits are not active if the Primary Frame Synchronizer block has been by-passed. 757 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 669: PMON Framing Bit/Byte Error Count Register - LSB (Address Location= 0xN353) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 20 0 Rev2...0...0 200 PMON_Framing_Bit/Byte_Error_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_Framing Bit/Byte Error_Count_Lower Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - Framing Bit/Byte Error Count - Lower Byte: These RESET-upon-READ bits, along with that within the "PMON Framing Bit/Byte Error Count Register - MSB" combine to reflect the cumulative number of Framing bit (or byte) errors that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Least Significant byte of this 16-bit expression. Note: For DS3 applications, this register will increment for each F or M bit error detected. For E3, ITU-T G.751 applications, this register will increment for each FAS error detected. For E3, ITU-T G.832 applications, this register will increment for each FA1 or FA2 byte error detected. These register bits are not active if the Primary Frame Synchronizer block has been by-passed. 758 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 670: PMON Parity/P-Bit Error Count Register - MSB (Address Location= 0xN354) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_Parity_Error_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_P-Bit/Parity Bit Error_Count_Upper Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - P Bit/Parity Bit Error Count - Upper Byte: These RESET-upon-READ bits, along with that within the "PMON PBit/Parity Bit Error Count Register - LSB" combine to reflect the cumulative number of P bit errors (for DS3 applications) or BIP-8/BIP4 errors (for E3 applications) that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been by-passed. Table 671: PMON Parity/P-Bit Error Count Register - LSB (Address Location= 0xN355) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_Parity_Error_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_P-Bit/Parity Bit Error_Count_Lower Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - P Bit/Parity Bit Error Count - Lower Byte: These RESET-upon-READ bits, along with that within the "PMON PBit/Parity Bit Error Count Register - MSB" combine to reflect the cumulative number of P bit errors (for DS3 applications) or BIP-8/BIP4 errors (for E3 applications) that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Least Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been by-passed. 759 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 672: PMON FEBE Event Count Register - MSB (Address Location= 0xN356) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 20 0 Rev2...0...0 200 PMON_FEBE_Event_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_FEBE Event_Count_Upper Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - FEBE Event Count - Upper Byte: These RESET-upon-READ bits, along with that within the "PMON FEBE Event Count Register - LSB" combine to reflect the cumulative number of "erred" FEBE events that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been by-passed. Table 673: PMON FEBE Event Count Register - LSB (Address Location= 0xN357) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_FEBE_Event_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_FEBE Event_Count_Lower Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - FEBE Event Count - Lower Byte: These RESET-upon-READ bits, along with that within the "PMON FEBE Event Count Register - MSB" combine to reflect the cumulative number of "erred" FEBE events that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Least Significant byte of this 16bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been by-passed. 760 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 674: PMON CP-Bit Error Count Register - MSB (Address Location= 0xN358) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_CP-Bit_Error_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_CP-Bit Error_Count_Upper Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - CP Bit Error Count - Upper Byte: These RESET-upon-READ bits, along with that within the "PMON CP-Bit Error Count Register - LSB" combine to reflect the cumulative number of CP bit errors that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed, or if the Frame Synchronizer has not been configured to operate in the DS3 C-Bit Parity Framing format. Table 675: PMON CP-Bit Error Count Register - LSB (Address Location= 0xN359) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_CP-Bit_Error_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_CP-Bit Error_Count_Lower Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - CP Bit Error Count - Lower Byte: These RESET-upon-READ bits, along with that within the "PMON CP-Bit Error Count Register - MSB" combine to reflect the cumulative number of CP bit errors that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Least Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed, or if the Frame Synchronizer has not been configured to operate in the DS3 C-Bit Parity Framing Format. 761 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 676: PMON PLCP BIP-8 Error Count Register - MSB (Address Location= 0xN35A) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 20 0 Rev2...0...0 200 PMON_BIP-8_Error_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_BIP-8_ Error_Count_Upper_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - BIP-8 Error Count - Upper Byte: This "Reset-upon-Read" register, along with the "PMON BIP-8 Error Count Register - LSB" (Address = N35B) contains a 16-bit representation of the total number of BIP-8 Errors (in the incoming B1 byte) that have been detected by the Receive PLCP Processor, since the last read of these registers. This register contains the MSB (or Upper Byte) value of this 16 bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed. Table 677: PMON PLCP BIP-8 Error Count Register - LSB (Address Location= 0xN35B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_BIP-8_Error_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_BIP-8_ Error_Count_Lower_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - BIP-8 Error Count - Lower Byte: This "Reset-upon-Read" register, along with the "PMON BIP-8 Error Count Register - MSB" (Address = N35A) contains a 16-bit representation of the total number of BIP-8 Errors (in the incoming B1 byte) that have been detected by the Receive PLCP Processor, since the last read of these registers. This register contains the LSB (or Lower Byte) value of this 16 bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed. 762 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 678: PMON PLCP Framing Byte Error Count Register - MSB (Address Location= 0xN35C) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_Framing_Byte_Error_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_Framing Byte_ Error_Count_Upper_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - Framing Byte Error Count - Upper Byte: This "Reset-upon-Read" register, along with the "PMON Framing Byte Error Count Register - LSB" (Address = 0xN35D) contains a 16-bit representation of the total number of Framing Byte Errors (in the incoming A1 and A2 bytes) that have been detected by the Receive PLCP Processor, since the last read of these registers. This register contains the MSB (or Upper Byte) value of this 16 bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed. Table 679: PMON PLCP Framing Byte Error Count Register - LSB (Address Location= 0xN35D) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_Framing_Byte_Error_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_Framing Byte_ Error_Count_Lower_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor - Framing Byte Error Count - Lower Byte: This "Reset-upon-Read" register, along with the "PMON Framing Byte Error Count Register - MSB" (Address = 0xN35C) contains a 16-bit representation of the total number of Framing Byte Errors (in the incoming A1 and A2 bytes) that have been detected by the Receive PLCP Processor, since the last read of these registers. This register contains the LSB (or Lower Byte) value of this 16 bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed. 763 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 680: PMON PLCP FEBE Event Count Register - MSB (Address Location= 0xN35E) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 20 0 Rev2...0...0 200 PMON_PLCP_FEBE_Event_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PMON_PLCP_FEBE_Event_ Count_Upper_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor -PCLP FEBE Event Count - Upper Byte: This "Reset-upon-Read" register, along with the "PMON PLCP FEBE Event Count Register - LSB" (Address = 0xN35F) contains a 16-bit representation of the total of data within the FEBE field of the G1 Byte, that have been read by the Receive PLCP Processor, since the last read of these registers. This register contains the MSB (or Upper byte) value of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been by-passed. Table 681: PMON PLCP FEBE Event Count Register - LSB (Address Location= 0xN35F) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PMON_PLCP_FEBE_Event_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PMON_PLCP_FEBE_Event_ Count_Lower_Byte[7:0] TYPE RUR DESCRIPTION Performance Monitor -PCLP FEBE Event Count - Lower Byte: This "Reset-upon-Read" register, along with the "PMON PLCP FEBE Event Count Register - MSB" (Address = 0xN35E) contains a 16-bit representation of the total of data within the FEBE field of the G1 Byte, that have been read by the Receive PLCP Processor, since the last read of these registers. This register contains the LSB (or Lower byte) value of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been by-passed. 764 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 682: PRBS Error Count Register - MSB (Address Location= 0xN368) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PRBS_Error_Count_Upper_Byte[7:0] BIT NUMBER 7-0 NAME PRBS Error_Count_Upper Byte[7:0] TYPE RUR DESCRIPTION PRBS Error Count - Upper Byte: These RESET-upon-READ bits, along with that within the "PRBS Error Count Register - LSB" combine to reflect the cumulative number of PRBS bit errors that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Most Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed, and if the PRBS Receiver has not been enabled. Table 683: PRBS Error Count Register - LSB (Address Location= 0xN369) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 PRBS_Error_Count_Lower_Byte[7:0] BIT NUMBER 7-0 NAME PRBS Error_Count_Lower Byte[7:0] TYPE RUR DESCRIPTION PRBS Error Count - Lower Byte: These RESET-upon-READ bits, along with that within the "PRBS Error Count Register - MSB" combine to reflect the cumulative number of PRBS bit errors that have been detected by the Primary Frame Synchronizer block, since the last read of this register. This register contains the Least Significant byte of this 16-bit expression. Note: These register bits are not active if the Primary Frame Synchronizer block has been bypassed, and if the PRBS Receiver has not been enabled. 765 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 684: PMON Holding Register (Address Location= 0xN3, 0x6C; Address Location= 0xN36C) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 PMON_Hold_Value[7:0] BIT NUMBER 7-0 NAME PMON Holding Value TYPE R/O DESCRIPTION PMON Holding Value: These READ-ONLY bit-fields were specifically allocated to support READ operations to the PMON (Performance Monitor) Registers, within the DS3/E3 Framer blocks. Since the PMON Register (within the DS3/E3 Framer block) are 16bit registers. Therefore, given that the bi-directional data bus of the XRT94L33 is only 8-bits wide, it will require two read operations in order to read out the entire 16 bit content of these registers. The other thing to note is that the PMON Registers (within the DS3/E3 Framer blocks) are RESET-upon-READ type registers. As consequence, the entire 16-bit contents of a given PMON Register will be cleared to "0x0000" immediately after the user has executed the first (of two) read operations to this register. In order to avoid losing the contents of the other byte, the contents of the "un-read" byte is automatically loaded into this register. Hence, once the user reads a register, from a given PMON Register, he/she is suppose to obtain the contents of the other byte, by reading the contents of this register. 766 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 685: One Second Error Status Register (Address Location= 0xN36D) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 Errored Second R/O 0 BIT 0 Severe Errored Second R/O 0 Unused BIT NUMBER 7-2 1 NAME Unused Errored Second TYPE R/O R/O Errored Second Indicator: DESCRIPTION This READ-ONLY bit-field indicates whether or not the DS3/E3 Framer block has declared the last one-second accumulation period as a "Errored Second". The DS3/E3 Framer block will declare a "errored second" if it detects any of the following events. For DS3 Applications * P-Bit Errors * CP Bit Errors * Framing Bit (F or M bit) Errors For E3 Applications * BIP-4/BIP-8 Errors * FAS or Framing Byte (FA1, FA2) Errors 0 - Indicates that the DS3/E3 Framer block has NOT declared the last onesecond accumulation period as being an errored second. 1 - Indicates that the DS3/E3 Framer block has declared the last onesecond accumulation period as being an errored second. Note: 0 Severely Errored Second R/O This bit-field is only active if the Primary Frame Synchronizer block is enabled. Severely Errored Second Indicator: This READ-ONLY bit-field indicates whether or not the DS3/E3 Framer block has declared the last one second accumulation period as being a "Severely Errored Second". The DS3/E3 Framer block will declare a given second as being a "severely errored" second if it determines that the BER (Bit Error Rate) during this "one-second accumulation" period is greater than 10-3 errors/second. 0 - Indicates that the DS3/E3 Framer block has not declared the last onesecond accumulation period as being a "severely-errored" second. 1 - Indicates that the DS3/E3 Framer block has declared the last onesecond accumulation period as being a "severely-errored" second. Note: This bit-field is only active if the Primary Frame Synchronizer block is enabled. 767 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 686: One Second - LCV Count Accumulator Register - MSB (Address Location= 0xN36E) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 One_Second_LCV_Count_Accum_MSB[7:0] BIT NUMBER 7-0 NAME One_Second_LCV_Count Accum_LSB[7:0] TYPE R/O DESCRIPTION One Second LCV Count Accumulator Register - MSB: These READ-ONLY bits, along with that within the "One Second LCV Count Accumulator Register - MSB" combine to reflect the cumulative number of "Line Code Violations" that have been detected by the Frame Synchronizer block, in the last "one second" accumulation period. This register contains the Most Significant byte of this 16-bit expression. Table 687: One Second - LCV Count Accumulator Register - LSB (Address Location= 0xN36F) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 One_Second_LCV_Count_Accum_LSB[7:0] BIT NUMBER 7-0 NAME One_Second_LCV_Count Accum_LSB[7:0] TYPE R/O DESCRIPTION One Second LCV Count Accumulator Register - LSB: These READ-ONLY bits, along with that within the "One Second LCV Count Accumulator Register - LSB" combine to reflect the cumulative number of "Line Code Violations" that have been detected by the Frame Synchronizer block, in the last "one second" accumulation period. This register contains the Least Significant byte of this 16-bit expression. 768 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 688: One Second - Parity Error Accumulator Register - MSB (Address Location= 0xN370) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 One_Second_Parity_Error_Accum_MSB[7:0] BIT NUMBER 7-0 NAME One_Second_Parity Error Accum_MSB[7:0] TYPE R/O DESCRIPTION One Second Parity Error Accumulator Register - MSB: These READ-ONLY bits, along with that within the "One Second Parity Error Accumulator Register - LSB" combine to reflect the cumulative number of "Parity Errors" that have been detected by the Frame Synchronizer block, in the last "one second" accumulation period. This register contains the Most Significant byte of this 16-bit expression. Note: For DS3 applications, the register will reflect the number of P-bit errors, detected within the last "one second" accumulation period. For E3, ITU-T G.751 applications, this register will reflect the number of BIP-4 errors, detected within the last "one second" accumulation period. For E3, ITU-T G.832 applications, this register will reflect the number of BIP-8 (B1 Byte) errors detected within the last "one second" accumulation period. 769 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 689: One Second - Parity Error Accumulator Register - LSB (Address Location= 0xN371) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 One_Second_Parity_Error_Accum_LSB[7:0] BIT NUMBER 7-0 NAME One_Second_Parity Error Accum_LSB[7:0] TYPE R/O DESCRIPTION One Second Parity Error Accumulator Register - LSB: These READ-ONLY bits, along with that within the "One Second Parity Error Accumulator Register - MSB" combine to reflect the cumulative number of "Parity Errors" that have been detected by the Frame Synchronizer block, in the last "one second" accumulation period. This register contains the Least Significant byte of this 16-bit expression. Note: For DS3 applications, the register will reflect the number of P-bit errors, detected within the last "one second" accumulation period. For E3, ITU-T G.751 applications, this register will reflect the number of BIP-4 errors, detected within the last "one second" accumulation period. For E3, ITU-T G.832 applications, this register will reflect the number of BIP-8 (B1 Byte) errors detected within the last "one second" accumulation period. 770 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 690: One Second - CP Bit Error Accumulator Register - MSB (Address Location= 0xN372) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 One_Second_CP_Bit_Error_Accum_MSB[7:0] BIT NUMBER 7-0 NAME One_Second_CP Bit Error Accum_MSB[7:0] TYPE R/O DESCRIPTION One Second CP Bit Error Accumulator Register - MSB: These READ-ONLY bits, along with that within the "One Second CP-Bit Error Accumulator Register - LSB" combine to reflect the cumulative number of "CP Bit Errors" that have been detected by the Frame Synchronizer block, in the last "one second" accumulation period. This register contains the Most Significant byte of this 16-bit expression. Note: This register is inactive if the Frame Synchronizer block is "by-passed" or if the Frame Synchronizer block has not been configured to operate in the DS3, C-Bit Parity framing format. Table 691: One Second - CP Bit Error Accumulator Register - LSB (Address Location= 0xN373) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 One_Second_CP_Bit_Error_Accum_LSB[7:0] BIT NUMBER 7-0 NAME One_Second_CP Bit Error Accum_LSB[7:0] TYPE R/O DESCRIPTION One Second CP Bit Error Accumulator Register - LSB: These READ-ONLY bits, along with that within the "One Second CP-Bit Error Accumulator Register - MSB" combine to reflect the cumulative number of "CP Bit Errors" that have been detected by the Frame Synchronizer block, in the last "one second" accumulation period. This register contains the Least Significant byte of this 16-bit expression. Note: This register is inactive if the Frame Synchronizer block is "by-passed" or if the Frame Synchronizer block has not been configured to operate in the DS3, C-Bit Parity framing format. 771 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.12.11 GENERAL PURPOSE I/O PIN CONTROL REGISTERS 20 0 Rev2...0...0 200 Table 692: Line Interface Drive Register (Address Location= 0xN380) BIT 7 Internal Remote Loop-back R/W 0 R/O 0 R/O 0 R/O 0 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 R/O 1 R/O 0 R/O 0 R/O 0 BIT NUMBER 7 NAME Internal Remote Loopback TYPE R/W DESCRIPTION Internal Remote Loop-back Mode: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block to operate in the "Remote Loop-back" Mode. If the user enables this feature, then the Receive Input of the Primary Frame Synchronizer block will automatically be routed to the Transmit Output of the Frame Generator block. 0 - Disables the Remote Loop-back Mode. 1 - Enables the Remote Loop-back Mode. Note: This feature is only available if both the Frame Generator and the Primary Frame Synchronizer blocks are enabled. 6-0 Unused R/O 772 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS LAPD CONTROLLER BYTE COUNT REGISTERS 1.12.12 Table 693: TxLAPD Byte Count Register (Address Location= 0xN383) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxLAPD_MESSAGE_SIZE[7:0] BIT NUMBER 7-0 NAME TxLAPD_MESSAGE_SIZE[7:0] TYPE R/W DESCRIPTION Transmit LAPD Message Size: These READ/WRITE bit-fields permit the user to specify the size of the information payload (in terms of bytes) within the very next outbound LAPD/PMDL Message, whenever Bit 7 (TxLAPD Any) within the "Transmit Tx LAPD Configuration" Register has been set to "1". Table 694: RxLAPD Byte Count Register (Address Location= 0xN384) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 RxLAPD_MESSAGE_SIZE[7:0] BIT NUMBER 7-0 NAME RxLAPD_MESSAGE_SIZE[7:0] TYPE R/O DESCRIPTION Receive LAPD Message Size: These READ-ONLY bit-fields indicate the size of the most recently received LAPD/PMDL Message, whenever Bit 7 (RxLAPD Any) within the "Rx LAPD Control" Register; has been set to "1". The contents of these register bits, reflects the Received LAPD Message size, in terms of bytes. 773 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 695: Receive PLCP Configuration and Status Register (Address Location= 0xN390) BIT 7 Unused BIT 6 BIT 5 Nibble Boundary Shift R/O 0 R/W 0 BIT 4 Speed Count R/W 0 BIT 3 Reframe BIT 2 POOF Status R/O 0 BIT 1 PLOF Status R/O 0 BIT 0 Yellow Status R/O 0 20 0 Rev2...0...0 200 R/O 0 R/W 0 BIT NUMBER 7-6 5 4 3 NAME Unused Nibble Boundary Shift Speed Count Reframe TYPE R/O R/W R/W R/W DESCRIPTION Receive PLCP Processor Reframe Operation: This "Read/Write" bit-field allows the user to command the Receive PLCP Processor to perform a "Reframe" operation. If the user invokes this command, the Receive PLCP Processor will transition from the "In-Frame" state to the "Loss-of-Frame" state. Afterwards, it will attempt to reacquire framing. 1 - The Receive PLCP Processor will perform a "reframe: operation 0 - The Receive PLCP Processor will NOT perform a "Reframe" operation 2 POOF Status R/O POOF (Receive PLCP Processor Out-of-Frame) Status: This "Read-Only" bit-field indicates whether or not the Receive PLCP Processor is in the "Out-of-Frame (OOF)" condition or not. 0 - Receive PLCP Processor is either in the "In-Frame" condition or in the "Loss-of-Frame" condition. 1 - Receive PLCP is currently in the "OOF Condition". 1 PLOF Status R/O PLOP (Receive PLCP Processor Loss of Frame) Status: This "Read-Only" bit-field indicates whether or not the Receive PLCP Processor is in the "Loss of Frame (LOF) condition or not. PLCP Loss of Frame is declared if PLCP Out-of-Frame (POOF), in bit 2 of this register, is declared for more than 1ms. PLOF is deasserted if POOF is off for more than 12 ms. 0 - Receive PLCP Processor is either in the "In-Frame" condition or in the "Out-of-Frame" condition. 1 - Receive Condition". PLCP Processor is currently in the "LOF 0 Yellow Status R/O Yellow Status: This "Read-Only" bit field indicates whether or not the Receive PLCP Processor has detected a prolonged "Yellow Alarm" indication in the G1 bytes of the incoming PLCP frames. 774 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS If a "Far-End" Receive PLCP Processor has trouble receiving valid PLCP data from the "Near-End" Transmit PLCP Processor, it (the Far End Transmit PLCP Processor) will begin to transmit PLCP frames that contain G1 bytes with the asserted "Yellow Alarm - RAI" indicators. If the "Near-End" Receive PLCP Processor determines that it has been receiving PLCP frames with these kind of G1 bytes for a 10 or more consecutive frames; then the Receive PLCP Processor will set this bit-field to "1". 1 - Indicates 10 or more consecutive frames received contain Yellow Alarm Indicators in G1 bytes. 0 - Indicates 10 or more consecutive frames received without Yellow Alarm Indicators in G1 bytes. Table 696: Receive PLCP Interrupt Enable Register (Address Location= 0xN391) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 POOF Interrupt Enable R/O 0 R/O 0 R/O 0 R/W 0 BIT 0 PLOF Interrupt Enable R/W 0 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused POOF Interrupt Enable TYPE R/O R/W DESCRIPTION POOF Interrupt Enable: This "Read-Write" bit-field allows the user to enable or disable the "Change in POOF Condition" interrupt. 0 - Disables PLCP Out-of-Frame (OOF) interrupt condition 1 - Enables PLCP Out-of-Frame (OOF) interrupt condition 0 PLOF Interrupt Enable R/W PLOF Interrupt Enable: This "Read-Write" bit-field allows the user to enable or disable the "Change in PLOF Condition" interrupt. 0 - Disables PLCP Loss-of-Frame (LOF) interrupt condition 1 - Enables PLCP Loss-of-Frame (LOF) interrupt condition 775 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 697: Receive PLCP Interrupt Status Register (Address Location= 0xN392) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 POOF Interrupt Status R/O 0 R/O 0 R/O 0 R/O 0 BIT 0 PLOF Interrupt Status R/O 0 20 0 Rev2...0...0 200 R/O 0 R/O 0 R/O 0 BIT NUMBER 7-2 1 NAME Unused POOF Interrupt Status TYPE R/O R/W POOF Interrupt Status: DESCRIPTION This "Read-Only" bit-field indicates whether a "Change in POOF (Receive PLCP Processor Out of Frame) condition" interrupt has been generated since the last read of this register. If this bit-field is "0", then the "Change in POOF Condition" interrupt has not occurred since the last read of this register. However, if this bit-field is "1", then the "Change in POOF Condition" interrupt has occurred since the last read of this register. This bit-field will be asserted under the following two conditions: 1. The Receive PLCP Processor transitions from the "InFrame" or "Loss of Frame" condition to the "Out of Frame" condition. 2. The Receive PLCP Processor transitions from the "Outof-Frame" condition to the "In-Frame" condition. The local P can read the "Rx PLCP Configuration/Status" Register (Address = 0xN390), in order to determine the current "POOF" status.condition 0 PLOF Interrupt Status R/W PLOF Interrupt Status: This "Read Only" bit-field indicates whether a "Change in PLOF (Receive PLCP Processor Loss of Frame) condition" interrupt has been generated since the last read of this register. If this bit-field is "0", then the "Change in PLOF Condition" interrupt has not occurred since the last read of this register. However, if this bit-field is "1", then the "Change in PLOF Condition" interrupt has occurred since the last read of this register. This bit-field will be asserted under the following two conditions: 1. The Receive PLCP Processor transitions from the "InFrame" condition to the "Loss of Frame" condition. 2. The Receive PLCP Processor transitions from the "Loss of Frame" or "Out of Frame" condition to the "In-Frame" 776 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS condition. The local P can read the "Rx PLCP Configuration/Status" Register (Address = 0xN390), in order to determine the current "PLOF" status. 777 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 698: Transmit PLCP A1 Byte Error Mask Register (Address Location= 0xN398) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/w 0 BIT 0 R/W 0 20 0 Rev2...0...0 200 A1_Byte_Error_Mask [7:0] BIT NUMBER 7-0 NAME A1_Byte_Error_Mask [7:0] TYPE R/W DESCRIPTION A1_Byte_Error_Mask [7:0]: This register allows the user to insert errors into the A1 Byte of each outgoing PLCP Frame. The Transmit PLCP Processor automatically performs the XOR operation on the A1 byte of every outbound PLCP frame with the contents of this register. Therefore, if this register contains any "1s", then errors will be inserted into the A1 byte. If the user wishes to operate the Transmit PLCP in a normal mode (e.g., by NOT inserting errors into the A1 byte), then he/she must insure that this register contains the default value, 00h. Table 699: Transmit PLCP A2 Byte Error Mask Register (Address Location= 0xN399) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/w 0 BIT 0 R/W 0 A2_Byte_Error_Mask [7:0] BIT NUMBER 7-0 NAME A2_Byte_Error_Mask [7:0] TYPE R/W DESCRIPTION A2_Byte_Error_Mask [7:0]: This register allows the user to insert errors into the A2 Byte of each outgoing PLCP Frame. The Transmit PLCP Processor automatically performs the XOR operation on the A2 byte of every outbound PLCP frame with the contents of this register. Therefore, if this register contains any "1s", then errors will be inserted into the A2 byte. If the user wishes to operate the Transmit PLCP in a normal mode (e.g., by NOT inserting errors into the A2 byte), then he/she must insure that this register contains the default value, 00h. 778 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 700: Transmit PLCP B1 Byte (BIP-8) Error Mask Register (Address Location= 0xN39A) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/w 0 BIT 0 R/W 0 B1_Byte_Error_Mask [7:0] BIT NUMBER 7-0 NAME B1_Byte_Error_Mask [7:0] TYPE R/W B1_Byte_Error_Mask [7:0]: DESCRIPTION This register allows the user to insert errors into the B1 Byte of each outgoing PLCP Frame. The Transmit PLCP Processor automatically performs the XOR operation on the B1 byte of every outbound PLCP frame with the contents of this register. Therefore, if this register contains any "1s", then errors will be inserted into the B1 byte. If the user wishes to operate the Transmit PLCP in a normal mode (e.g., by NOT inserting errors into the B1 byte), then he/she must insure that this register contains the default value, 00h. 779 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 701: Transmit PLCP G1 Byte Register (Address Location= 0xN39B) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 Tx FEBE Mask R/W 0 BIT 3 Yellow Alarm R/W 0 R/W 0 BIT 2 BIT 1 LSS [2:0] R/W 0 R/W 0 BIT 0 20 0 Rev2...0...0 200 BIT NUMBER 7-5 4 NAME Unused Tx FEBE Mask TYPE R/O R/W Tx FEBE Mask: DESCRIPTION This "Read/Write" bit-field allows the user to command the Transmit PLCP Processor to insert a value of "0000" into the FEBE field of the G1 byte in the outbound PLCP Frame. 1 - Transmit FEBE count with the value of "0000" overwritten by the Transmit PLCP Processor 0 - Transmit Received FEBE count 3 Yellow Alarm R/W Yellow Alarm: This "Read/Write" bit-field allows the user to command the Transmit PLCP to send a "Yellow Alarm" via the G1 byte (within the outbound PLCP frame) to the far-end Receive PLCP Processor. 1 - The Transmit PLCP will force the "RAI" bit (Yellow Alarm) , within the G1 byte, to "1" 0 - "RAI" bit (Yellow Alarm) will NOT be forced. 2-0 LSS [2:0] R/W LSS (Link Status Signal) 2:0]: This "Read/Write" bit-fields allows the user to transmit their own "proprietary" data link messages, via the 3 unused bits within the G1 bytes, of each outbound PLCP frame. 780 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 702: Receive DS3/E3 Configuration Register - Secondary Frame Synchronizer (Address Location= 0xN3F0) BIT 7 BIT 6 Unused BIT 5 BIT 4 Primary Frame - Clock Output Invert R/O 0 R/W 0 BIT 3 Primary Frame - Transmit AIS Enable R/W 0 BIT 2 Secondary Frame - Single-Rail Input R/W 0 BIT 1 Primary Frame - DualRail Output R/W 0 BIT 0 Primary Frame - Idle Pattern Insert R/W 0 R/O 0 R/O 0 BIT NUMBER 7-5 4 NAME Unused Primary Frame - Clock Output Invert TYPE R/O R/W DESCRIPTION Primary Frame Synchronizer - Clock Output Invert: This READ/WRITE bit-field permits the user to configure the Primary Frame Synchronizer block to update the "DS3/E3/STS1_DATA_OUT_n" output pins upon either the rising or falling edge of "DS3/E3/STS1_CLK_OUT_n. 0 - DS3/E3/STS1_DATA_OUT_n is updated upon the rising edge of "DS3/E3/STS1_Clk_OUT_n". The user should insure that the LIU IC will sample "DS3/E3/STS1_DATA_OUT_n" upon the falling edge of "DS3/E3/STS1_CLK_OUT_n" 1 - DS3/E3/STS1_DATA_OUT_n" is updated upon the falling edge of "DS3/E3/STS1_Clk_OUT_n". The user should insure that the LIU IC will sample "DS3/E3/STS1_DATA_OUT_n" upon the rising edge of "DS3/E3/STS1_CLK_OUT_n". Note: This bit-field is only active if the "Primary Frame Synchronizer" block has been configured to operate in the "Egress" Direction. 3 Primary Frame - Transmit AIS Enable R/W Primary Frame Synchronizer Block - Transmit AIS Enable: This READ/WRITE bit-field permits the user to either enable or disable the AIS Pattern Generator, within the Primary Frame Synchronizer block.. If the user enables the "AIS Pattern Generator", then the data, that is output via the Primary Frame Synchronizer block, will be overwritten with the AIS Pattern. 0 -Disables the "AIS Pattern Generator" within the Primary Frame Synchronizer block. 1 - Enables the "AIS Pattern Generator" within the Primary Frame Synchronizer block. 2 Secondary Frame - Single-Rail Input R/W Secondary Frame Synchronizer Block -Single-Rail/Dual Rail Input Select: This READ/WRITE bit-field permits the user to configure the Secondary Frame Synchronizer block to accept data via either the "Single-Rail" or "Dual-Rail" manner. 0 - Configures the Secondary Frame Synchronizer block to accept data via the "Single-Rail" Mode. 1 - Configures the Secondary Frame Synchronizer block to accept data via the "Dual-Rail" Mode. Note: This register bit is only valid if the Secondary Frame Synchronizer block has been configured to operate in the "Ingress" Direction. 781 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 Primary Frame - Dual-Rail Output R/W Primary Frame Synchronizer - Dual-Rail Output: This READ/WRITE bit-field permits the user configure the Primary Frame Synchronizer block to output data (to the LIU IC) in either the Single-Rail or Dual-Rail Manner. 0 - Configures the Primary Frame Synchronizer block to output data (to the LIU IC) in a Single-Rail Manner. 1 - Configures the Primary Frame Synchronizer block to output data (to the LIU IC) in a Dual-Rail Manner. Note: 0 Primary Frame - Idle Pattern Insert R/O This register bit is only valid if the Primary Frame Synchronizer block has been configured to operate in the "Egress" Direction. 20 0 Rev2...0...0 200 Primary Frame Synchronizer Block - Idle Pattern Insert: This READ/WRITE bit-field permits the user to either enable or disable the Idle Pattern Generator, within the Primary Frame Synchronizer block.. If the user enables the "Idle Pattern Generator", then the data, that is output via the Primary Frame Synchronizer block, will be overwritten with the Idle Pattern. 0 -Disables the "Idle Pattern Generator" within the Primary Frame Synchronizer block. 1 - Enables the "Idle Pattern Generator" within the Primary Frame Synchronizer block. 782 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 703: Receive DS3/E3 Status Register - Secondary Frame Synchronizer (Address Location= 0xN3F1) BIT 7 Secondary Frame Synchronizer - AIS Defect Declared R/O 0 BIT 6 Secondary Frame Synchronizer - LOS Defect Declared R/O 0 BIT 5 Secondary Frame Synchronizer - DS3 Idle Pattern Detected R/O 0 BIT 4 Secondary Frame Synchronizer - OOF Defect Declared R/O 1 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 Unused R/O 0 R/O 0 BIT NUMBER 7 NAME Secondary Frame Synchronizer - AIS Defect Declared TYPE R/O DESCRIPTION Secondary Frame Synchronizer Block - AIS Defect Declared: This READ/WRITE bit-field indicates whether or not the Secondary Frame Synchronizer block is currently declaring the AIS condition. 0 - Indicates that the Secondary Frame Synchronizer block is NOT declaring the AIS defect. 1 - Indicates that the Secondary Frame Synchronizer block is currently declaring the AIS defect 6 Secondary Frame Synchronizer - LOS Defect Declared R/O Secondary Frame Synchronizer Block - LOS Defect Declared: This READ/WRITE bit-field indicates whether or not the Secondary Frame Synchronizer block is currently declaring the LOS condition. 0 - Indicates that the Secondary Frame Synchronizer block is NOT declaring the LOS defect. 1 - Indicates that the Secondary Frame Synchronizer block is currently declaring the LOS defect. 5 Secondary Frame Synchronizer - Idle Pattern Detected R/O Secondary Frame Synchronizer Block - Idle Pattern Detected: This READ/WRITE bit-field indicates whether or not the Secondary Frame Synchronizer block is currently detecting the DS3 Idle Pattern, within its incoming Receive Path. 0 - Indicates that the Secondary Frame Synchronizer block is NOT detecting the DS3 Idle Pattern. 1 - Indicates that the Secondary Frame Synchronizer block is currently detecting the DS3 Idle Pattern. Note: This bit-field is only valid if the DS3/E3 Frame Synchronizer block has been configured to operate in the DS3 Mode. 4 Secondary Frame Synchronizer - OOF Defect Declared R/O Secondary Frame Synchronizer Block - OOF Defect Declared: This READ/WRITE bit-field indicates whether or not the Secondary Frame Synchronizer block is currently declaring the OOF condition. 0 - Indicates that the Secondary Frame Synchronizer block is NOT declaring the OOF defect. 1 - Indicates that the Secondary Frame Synchronizer block is currently declaring the OOF defect. 3-0 Unused R/O 783 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 704: Receive DS3/E3 Interrupt Enable Register - Secondary Frame Synchronizer Block (Address Location= 0xN3F8) BIT 7 Unused BIT 6 Change of LOS Condition Interrupt Enable R/W 0 BIT 5 Change of AIS Condition Interrupt Enable R/W 0 BIT 4 Change of DS3 Idle Condition Interrupt Enable R/W 0 R/O 0 BIT 3 Unused BIT 2 BIT 1 Change of OOF Condition Interrupt Enable BIT 0 Unused R/O 0 R/O 0 R/W 0 R/O 0 BIT NUMBER 7 6 NAME Unused Change of LOS Condition Interrupt Enable TYPE R/O R/W DESCRIPTION Change of LOS Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of LOS Condition" Interrupt for the Secondary Frame Synchronizer block. If the user enables this interrupt, then the Secondary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * Whenever the Secondary Frame Synchronizer block declares the LOS defect. * Whenever the Secondary Frame Synchronizer block clears the LOS defect. 0 - Disables the "Change of LOS Condition" Interrupt. 1 - Enables the "Change of LOS Condition" Interrupt. 5 Change of AIS Condition Interrupt Enable R/W Change of AIS Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS Condition" Interrupt for the Secondary Frame Synchronizer block. If the user enables this interrupt, then the Secondary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * Whenever the Secondary Frame Synchronizer block declares the AIS defect. * Whenever the Secondary Frame Synchronizer block clears the AIS defect. 0 - Disables the "Change of AIS Condition" Interrupt. 1 - Enables the "Change of AIS Condition" Interrupt. 4 Change in DS3 Idle Condition Interrupt Enable R/W Change of DS3 Idle Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of DS3 Idle Condition" Interrupt for the Secondary Frame Synchronizer block. If the user enables this interrupt, then the Secondary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * Whenever the Secondary Frame Synchronizer block detects the DS3 784 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Idle pattern within its receive path. * Whenever the Secondary Frame Synchronizer block ceases to detect the DS3 Idle pattern within its receive path. 0 - Disables the "Change of DS3 Idle Condition" Interrupt. 1 - Enables the "Change of DS3 Idle Condition" Interrupt. Note: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3 Mode. 3-2 1 Unused Change of OOF Condition Interrupt Enable R/O R/W Change of OOF Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of OOF Condition" Interrupt for the Secondary Frame Synchronizer block. If the user enables this interrupt, then the Secondary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. * Whenever the Secondary Frame Synchronizer block declares the OOF defect. * Whenever the Secondary Frame Synchronizer block clears the OOF defect. 0 - Disables the "Change of OOF Condition" Interrupt. 1 - Enables the "Change of OOF Condition" Interrupt. 0 Unused R/O 785 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 705: Receive DS3/E3 Interrupt Status Register - Secondary Frame Synchronizer Block (Address Location= 0xN3F9) BIT 7 Unused BIT 6 Change of LOS Condition Interrupt Status RUR 0 BIT 5 Change of AIS Condition Interrupt Status RUR 0 BIT 4 Change of DS3 Idle Condition Interrupt Status RUR 0 R/O 0 BIT 3 Unused BIT 2 BIT 1 Change of OOF Condition Interrupt Status R/O 0 RUR 0 BIT 0 Unused R/O 0 R/O 0 BIT NUMBER 7 6 NAME Unused Change of LOS Condition Interrupt Status TYPE R/O RUR DESCRIPTION Change of LOS Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of LOS Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. 0 - Indicates that the "Change of LOS Condition" Interrupt (per the Secondary Frame Synchronizer block) has NOT occurred since the last read of this register. 1 - Indicates that the "Change of LOS Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. Note: The user can determine the current state of "LOS" (per the Secondary Frame Synchronizer" block) by reading out the state of Bit 6 (Secondary Frame Synchronizer - LOS Defect Declared) within the Receive DS3/E3 Status Register - Secondary Frame Synchronizer block" register (Address Location= 0xN3F1). 5 Change of AIS Condition Interrupt Status RUR Change of AIS Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. 0 - Indicates that the "Change of AIS Condition" Interrupt (per the Secondary Frame Synchronizer block) has NOT occurred since the last read of this register. 1 - Indicates that the "Change of AIS Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. Note: The user can determine the current state of "LOS" (per the Secondary Frame Synchronizer" block) by reading out the state of Bit 7 (Secondary Frame Synchronizer - AIS Defect Declared) within the Receive DS3/E3 Status Register - Secondary Frame Synchronizer block" register (Address Location= 0xN3F1). 4 Change of DS3 Idle Condition Interrupt Status RUR Change of DS3 Idle Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of DS3 Idle Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this 786 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS register. 0 - Indicates that the "Change of DS3 Idle Condition" Interrupt (per the Secondary Frame Synchronizer block) has NOT occurred since the last read of this register. 1 - Indicates that the "Change of DS3 Idle Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. Note: The user can determine the current "DS3 Idle" state (per the Secondary Frame Synchronizer" block) by reading out the state of Bit 5 (Secondary Frame Synchronizer - DS3 Idle Pattern Detected) within the Receive DS3/E3 Status Register - Secondary Frame Synchronizer block" register (Address Location= 0xN3F1). 3-2 1 Unused Change of OOF Condition Interrupt Status R/O RUR Change of OOF Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of OOF Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. 0 - Indicates that the "Change of OOF Condition" Interrupt (per the Secondary Frame Synchronizer block) has NOT occurred since the last read of this register. 1 - Indicates that the "Change of OOF Condition" Interrupt (per the Secondary Frame Synchronizer block) has occurred since the last read of this register. Note: The user can determine the current state of "LOS" (per the Secondary Frame Synchronizer" block) by reading out the state of Bit 4 (Secondary Frame Synchronizer - OOF Defect Declared) within the Receive DS3/E3 Status Register - Secondary Frame Synchronizer block" register (Address Location= 0xN3F1). 0 Unused R/O 787 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.13 RECEIVE STS-3C POH PROCESSOR BLOCK 20 0 Rev2...0...0 200 The register map for the Receive STS-3c POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Receive STS-3c POH Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "Receive STS-3c POH Processor Block "highlighted" is presented below in Figure 14. Figure 14: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive STS-3c POH Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 788 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS RECEIVE STS-3C POH PROCESSOR BLOCK REGISTER 1.13.1 Table 706: Receive STS-3c POH Processor Block - Register Address Map INDIVIDUAL REGISTER ADDRESS 0x00 - 0x81 0x82 0x83 0x84, 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 - 0x92 0x93 0x94, 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 - 0xA2 ADDRESS LOCATION 0x1000 - 0x1181 0x1182 0x1183 0x1184, 0x1185 0x1186 0x1187 0x1188 0x1189 0x118A 0x118B 0x118C 0x118D 0x118E 0x118F 0x1190 - 0x1192 0x1193 0x1194, 0x1195 0x1196 0x1197 0x1198 0x1199 0x119A 0x119B 0x119C 0x119D 0x119E 0x119F 0x11A0 - 0x11A2 Reserved Receive STS-3c Path - Control Register - Byte 1 Receive STS-3c Path - Control Register - Byte 0 Reserved Receive STS-3c Path - Status Register - Byte 1 Receive STS-3c Path - Status Register - Byte 0 Reserved Receive STS-3c Path - Interrupt Status Register - Byte 2 Receive STS-3c Path - Interrupt Status Register - Byte 1 Receive STS-3c Path - Interrupt Status Register - Byte 0 Reserved Receive STS-3c Path - Interrupt Enable Register - Byte 2 Receive STS-3c Path - Interrupt Enable Register - Byte 1 Receive STS-3c Path - Interrupt Enable Register - Byte 0 Reserved Receive STS-3c Path - SONET Receive RDI-P Register Reserved Receive STS-3c Path - Received Path Label Byte (C2) Register Receive STS-3c Path - Expected Path Label Byte (C2) Register Receive STS-3c Path - B3 Error Count Register - Byte 3 Receive STS-3c Path - B3 Error Count Register - Byte 2 Receive STS-3c Path - B3 Error Count Register - Byte 1 Receive STS-3c Path - B3 Error Count Register - Byte 0 Receive STS-3c Path - REI-P Error Count Register - Byte 3 Receive STS-3c Path - REI-P Error Count Register - Byte 2 Receive STS-3c Path - REI-P Error Count Register - Byte 1 Receive STS-3c Path - REI-P Error Count Register - Byte 0 Reserved REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 789 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS INDIVIDUAL REGISTER ADDRESS 0xA3 0xA4, 0xA5 0xA6 0xA7 0xA8 - 0xAA 0xAB 0xAC - 0xB2 0xB3 0xB4 - 0xBA 0xBB 0xBC - 0xBE 0xBF 0xC0 - 0xC2 0xC3 0xC4 - 0xD2 0xD3 0xD4 - 0xD6 0xD7 0xD8 - 0xDA 0xDB 0xDC - 0xDE 0xDF 0xE0 - 0xE2 0xE3 0xE4 - 0xE6 0xE7 ADDRESS LOCATION 0x11A2 0x11A3 0x11A4, 0x11A5 0x11A6 0x11A7 0x11A8 - 0x11AA 0x11AB 0x11AC - 0x11B2 0x11B3 0x11B4 - 0x11BA 0x11BB 0x11BC - 0x11BE 0x11BF 0x11C0 - 0x11C2 0x11C3 0x11C4 - 0x11D2 0x11D3 0x11D4 - 0x11D6 0x11D7 0x11D8 - 0x11DA 0x11DB 0x11DC - 0x11DE 0x11DF 0x11E0 - 0x11E2 0x11E3 0x11E4 - 0x11E6 0x11E7 Receive STS-3c Path - Receive J1 Byte Control Register Reserved Receive STS-3c Path - Pointer Value Register - Byte 1 Receive STS-3c Path - Pointer Value Register - Byte 0 Reserved Receive STS-3c Path - Loss of Pointer - Concatenation Status Register Reserved Receive STS-3c Path - AIS - Concatenation Status Register Reserved Receive STS-3c Path - AUTO AIS Control Register Reserved Receive STS-3c Path - Serial Port Control Register Reserved Receive STS-3c Path - SONET Receive Auto Alarm Register - Byte 0 Reserved Receive STS-3c Path - Receive J1 Byte Capture Register Reserved Receive STS-3c Path - Receive B3 Byte Capture Register Reserved Receive STS-3c Path - Receive C2 Byte Capture Register Reserved Receive STS-3c Path - Receive G1 Byte Capture Register Reserved Receive STS-3c Path - Receive F2 Byte Capture Register Reserved Receive STS-3c Path - Receive H4 Byte Capture Register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 REGISTER NAME 20 0 Rev2...0...0 200 DEFAULT VALUES 790 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0x11E8 - 0x11EA 0x11EB 0x11EC - 0x11EE 0x11EF 0x11F0 - 0x11F2 0x11F3 0x11F4 - 0x11FF Reserved Receive STS-3c Path - Receive Z3 Byte Capture Register Reserved Receive STS-3c Path - Receive Z4 (K3) Byte Capture Register Reserved Receive STS-3c Path - Receive Z5 Byte Capture Register Reserved REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 INDIVIDUAL REGISTER ADDRESS 0xE8 - 0xEA 0xEB 0xEC - 0xEE 0xEF 0xF0 - 0xF2 0xF3 0xF4 - 0xFF 791 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.13.2 RECEIVE STS-3C POH PROCESSOR BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 707: Receive STS-3c Path - Control Register - Byte 0 (Address Location= 0x1183) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 Check Stuff R/W 0 BIT 2 RDI-P Type R/W 0 BIT 1 REI-P Error Type R/W 0 BIT 0 B3 Error Type R/W 0 BIT NUMBER 7-4 3 NAME Unused Check Stuff TYPE R/O R/W DESCRIPTION Check (Pointer Adjustment) Stuff Select: This READ/WRITE bit-field permits the user to enable/disable the SONET standard recommendation that a pointer increment or decrement operation, detected within 3 SONET frames of a previous pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. 0 - Disables this SONET standard implementation. In this mode, all pointer-adjustment operations that are detected will be accepted. 1 - Enables this "SONET standard" implementation. In this mode, all pointer-adjustment operations that are detected within 3 SONET frame periods of a previous pointer-adjustment operation, will be ignored. 2 RDI-P Type R/W Path - Remote Defect Indicator Type Select: This READ/WRITE bit-field permits the user to configure the Receive STS3c POH Processor block to support either the "Single-Bit" or the "Enhanced" RDI-P, as described below. 0 - Configures the Receive STS-3c POH Processor block to support the Single-Bit RDI-P. In this mode, the Receive STS-3c POH Processor block will only monitor Bit 5, within the G1 byte (of incoming SPE data), in order to declare and clear the RDI-P indicator. 1 - Configures the Receive STS-3c POH Processor block to support the Enhanced RDI-P (ERDI-P). In this mode, the Receive STS-3c POH Processor block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare and clear the RDI-P indicator. 1 REI-P Error Type R/W REI-P Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Path REI-P Error Count" register is incremented. 0 - Configures the Receive STS-3c POH Processor block to count REI-P Bit Errors. In this case, the "Receive Path REI-P Error Count" register will be incremented by the value of the lower nibble within the G1 byte. 1 - Configures the Receive STS-3c POH Processor block to count REI-P Frame Errors. In this case, the "Receive Path REI-P Error Count" register will be incremented by a single count each time the Receive STS-3c POH Processor block receives a G1 byte, in which bits 1 through 4 are set to a "non-zero" value. 792 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS B3 Error Type R/W B3 Error Type: This READ/WRITE bit-field permits the user to specify how the "Receive Path B3 Error Count" register is incremented. 0 - Configures the Receive STS-3c POH Processor block to count B3 bit errors. In this case, the "Receive Path B3 Error Count" register will be incremented by the number of bits, within the B3 value, that is in error. 1 - Configures the Receive STS-3c POH Processor block to count B3 frame errors. In this case, the "Receive Path B3 Error Count" register will be incremented by the number of erred STS-3c frames. 0 793 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 708: Receive STS-3c Path - Control Register - Byte 0 (Address Location= 0x1186) BIT 7 BIT 6 BIT 5 BIT 4 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 3 BIT 2 BIT 1 BIT 0 J1 Unstable Indicator R/W 0 20 0 Rev2...0...0 200 BIT NUMBER 7-1 0 NAME Unused J1 Unstable Indicator TYPE R/O R/O DESCRIPTION J1 - Path Trace Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the Path Trace Unstable condition. The Receive STS-3c POH Processor block will declare a J1 (Path Trace) Unstable condition, whenever the "J1 Unstable" counter reaches the value "8". The "J0 Unstable" counter will be incremented for each time that it receives a J1 message that differs from the previously received message. The "J1 Unstable" counter is cleared to "0" whenever the Receive STS-3c POH Processor block has received a given J1 Message 3 (or 5) consecutive times. Note: Receiving a given J1 Message 3 (or 5) consecutive times also sets this bit-field to "0". 0 - Path Trace Instability condition is NOT declared. 1 - Path Trace Instability condition is currently declared. 794 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 709: Receive STS-3c Path - SONET Receive POH Status - Byte 0 (Address Location= 0x1187) BIT 7 TIM-P Defect Declared R/O 0 BIT 6 C2 Byte Unstable Condition R/O 0 BIT 5 UNEQ-P Defect Declared R/O 0 BIT 4 PLM-P Defect Declared R/O 0 BIT 3 RDI-P Defect Declared R/O 0 BIT 2 RDI-P Unstable Condition R/O 0 BIT 1 LOP-P Defect Declared R/O 0 BIT 0 AIS-P Defect Declared R/O 0 BIT NUMBER 7 NAME TIM-P Defect Declared TYPE R/O DESCRIPTION Trace Identification Mismatch (TIM-P) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the "Trace Identification Mismatch" (TIM-P) condition. The Receive STS-3c POH Processor block will declare the "TIM-P" condition, when none of the received 64 byte string (received via the J1 byte) matches the expected 64 byte message. The Receive STS-3c POH Processor block will clear the "TIM-P" condition, when 80% of the received 64 byte string (received via the J1 byte) matches the expected 64 byte message. 0 - Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the TIM-P condition. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the TIM-P condition. 6 C2 Byte Unstable Condition R/O C2 Byte (Path Signal Label Byte) Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the "Path Signal Label Byte" Unstable condition. The Receive STS-3c POH Processor block will declare a C2 (Path Signal Label Byte) Unstable condition, whenever the "C2 Unstable" counter reaches the value "5". The "C2 Unstable" counter will be incremented for each time that it receives an STS-3c SPE with a C2 byte value that differs from the previously received C2 byte value. The "C2 Unstable" counter is cleared to "0" whenever the Receive STS-3c POH Processor block has received 3 (or 5) consecutive SPEs of the same C2 byte value. Note: Receiving a given C2 byte value in 3 (or 5) consecutive SPEs also sets this bit-field to "0". 0 - C2 (Path Signal Label Byte) Unstable condition is NOT declared. 1 - C2 (Path Signal Label Byte) Unstable condition is currently declared. 5 UNEQ-P R/O Path - Unequipped Indicator (UNEQ-P): This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the UNEQ-P condition. The Receive STS-3c POH Processor block will declare a UNEQ-P condition, if it receives at least five (5) consecutive STS-3c frames, in which the C2 byte was set to 0x00 (which indicates that the SPE is "Unequipped"). The Receive STS-3c POH Processor block will clear the UNEQ-P condition, if it receives at least five (5) consecutive STS-3c frames, in which the C2 byte was set to a value other than 0x00. 0 - Indicates that the Receive STS-3c POH Processor block is NOT declaring 795 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS the UNEQ-P condition. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the UNEQ-P condition. Note: 1. The Receive STS-3c POH Processor block will not declare the UNEQ-P condition if it configured to expect to receive SONET frames with C2 bytes being set to "0x00" (e.g., if the "Receive STS-3c Path - Expected Path Label Value" Register is set to "0x00". 2. The Address Locations of the "Receive STS-3c Path - Expected Path Label Value" Register is 0x1197 4 PLM-P Defect Declared R/O Path Payload Mismatch Indicator (PLM-P): This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the PLM-P condition. The Receive STS-3c POH Processor block will declare an PLM-P condition, if it receives at least five (5) consecutive STS-3c frames, in which the C2 byte was set to a value other than that which it is expecting to receive. Whenever the Receive STS-3c POH Processor block is determine whether or not it should declare the PLM-P defect, it checks the contents of the following two registers. * The "Receive STS-3c Path - Received Path Label Value" Register * The "Receive STS-3c Path - Expected Path Label Value" Register The "Receive STS-3c Path - Expected Path Label Value" Register contains the value of the C2 bytes, that the Receive STS-3c POH Processor blocks expects to receive. The "Receive STS-3c Path - Received Path Label Value" Register contains the value of the C2 byte, that the Receive STS-3c POH Processor block has most received "validated" (by receiving this same C2 byte in five consecutive SONET frames). The Receive STS-3c POH Processor block will declare the PLM-P defect, if the contents of these two register do not match. The Receive STS-3c POH Processor block will clear the PLM-P condition if whenever the contents of these two registers do match. 0 - PLM-P defect is currently not being declared. 1 - PLM-P defect is currently being declared. Note: 1. The Receive STS-3c POH Processor block will clear the PLM-P defect, upon detecting the UNEQ-P condition. 2. The Address Location of the "Receive STS-3c Path - Received Path Label Value" Register is 0x1196 3. The Address Location of the Receive STS-3c Path - Expected Path Label Value" Register is 0x1196 3 RDI-P R/O Path Remote Defect Indicator (RDI-P): This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the RDI-P condition. If the Receive STS-3c POH Processor block is configured to support the "Single-bit RDI-P" function, then it will declare an RDI-P condition if Bit 5 (within the G1 byte of the incoming STS-3c frame) is set to "1" for "RDIP_THRD" number of consecutive STS-3c frames. If the Receive STS-3c POH Processor block is configured to support the Enhanced RDI-P" (ERDI-P) function, then it will declare an RDI-P condition if 20 0 Rev2...0...0 200 796 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Bits 5, 6 and 7 (within the G1 byte of the incoming STS-3c frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for "RDI-P_THRD" number of consecutive STS-3c frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT declaring an RDI-P condition. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring an RDI-P condition. Note: 1. The user can specify the value for "RDI-P_THRD" by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the "Receive STS3c Path - SONET Receive RDI-P Register. 2. The Address Location of the "Receive STS-3c Path - SONET Receive RDI-P Registers is 0x1193 2 RDI-P Unstable R/O RDI-P (Path - Remote Defect Indicator) Unstable: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the "RDI-P Unstable" condition. The Receive STS-3c POH Processor block will declare a "RDI-P I Unstable" condition whenever the "RDI-P Unstable Counter" reaches the value "RDI-P THRD". The "RDI-P Unstable" counter is incremented for each time that the Receive STS-3c POH Processor block receives an RDI-P value that differs from that of the previous STS-3c frame. The "RDI-P Unstable" counter is cleared to "0" whenever the same RDI-P value is received in "RDI-P_THRD" consecutive STS-3c frames. Note: Receiving a given RDI-P value, in "RDI-P_THRD" consecutive STS3c frames also clears this bit-field to "0". 0 - RDI-P Unstable condition is NOT declared. 1 - RDI-P Unstable condition is currently declared. Note: 1. The user can specify the value for "RDI-P_THRD" by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the "Receive STS3c Path - SONET Receive RDI-P Register. 2. The Address Location of the Receive STS-3c Path - SONET Receive RDIP Registers is 0x1193 1 LOP-P Defect Declared R/O Loss of Pointer Indicator (LOP-P): This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the LOP-P (Loss of Pointer) condition. The Receive STS-3c POH Processor block will declare the LOP-P condition, if it cannot detect a valid pointer (H1 and H2 bytes, within the TOH) within 8 to 10 consecutive SONET frames. Further, the Receive STS-3c POH Processor block will declare the LOP-P condition, if it detects 8 to 10 consecutive NDF events. The Receive STS-3c POH Processor block will clear the LOP-P condition, whenever the Receive STS-3c POH Processor detects valid pointer bytes (e.g., the H1 and H2 bytes, within the TOH) and normal NDF value for three consecutive SONET frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT declaring the LOP-P condition. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the LOP-P condition. 0 AIS-P R/O Path AIS (AIS-P) Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH 797 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Processor block is currently declaring an AIS-P condition. The Receive STS3c POH Processor block will declare an AIS-P if it detects all of the following conditions for three consecutive STS-3c frames. a. b. The H1, H2 and H3 bytes are set to an "All Ones" pattern. The entire SPE is set to an "All Ones" pattern. The Receive STS-3c POH Processor block will clear the AIS-P indicator when it detects a valid STS-3c pointer (H1 and H2 bytes) and a "set" or "normal" NDF for three consecutive STS-3c frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the AIS-P defect. 1 - Indicates that the Receive STS-3c POH Processor block declaring the AIS-P defect. Note: is currently The Receive STS-3c POH Processor block will NOT declare the LOP-P condition if it detects an "All Ones" pattern in the H1, H2 and H3 bytes. It will, instead, declare the AIS-P condition. 798 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 710: Receive STS-3c Path - SONET Receive Path Interrupt Status - Byte 2 (Address Location= 0x1189) BIT 7 Unused BIT 6 Change in AIS-C Condition Interrupt Status RUR 0 BIT 5 Change in LOP-C Condition Interrupt Status RUR 0 BIT 4 Detection of AIS Pointer Interrupt Status RUR 0 BIT 3 Detection of Pointer Change Interrupt Status RUR 0 BIT 2 POH Capture Interrupt Status RUR 0 BIT 1 Change in TIM-P Condition Interrupt Status RUR 0 BIT 0 Change in J1 Unstable Condition Interrupt Status RUR 0 R/O 0 BIT NUMBER 7 6 NAME Unused Change in AIS-C Condition Interrupt Status TYPE R/O RUR DESCRIPTION Change in AIS-C (AIS Concatenation) Condition Interrupt Status: This RESET-upon-READ bit-field permits indicates whether or not the "Change in AIS-C Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then an interrupt will be generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares an AIS-C condition with one of the STS-1 signals; within the incoming STS-3c signal. Whenever the Receive STS-3c POH Processor block clears the AIS-C condition with one of the STS-1 signals; within the incoming STS-3c signal. b. 0 - Indicates that the "Change in AIS-C Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in AIS-C Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of AIS-C by reading out the contents of the "Receive STS-3c Path - AIS-C Status" Register (Address Locations: 0x11B3). Concatenation) 5 Change in LOP-C Condition Interrupt Status RUR Change in LOP-C (Loss of Pointer Condition Interrupt Status: This RESET-upon-READ bit-field permits indicates whether or not the "Change in LOP-C Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then an interrupt will be generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares an LOP-C condition with one of the STS-1 signals; within the incoming STS-3c signal. Whenever the Receive STS-3c POH Processor block clears the LOP-C condition with one of the STS-1 signals; within the incoming STS-3c signal. b. 0 - Indicates that the "Change in LOP-C Condition" Interrupt has NOT occurred since the last read of this register. 799 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 1 - Indicates that the "Change in LOP-C Condition" Interrupt has occurred since the last read of this register. Note: The user can determine the current state of AIS-C by reading out the contents of the "Receive STS-3c Path - LOP-C Status" Register (Address Locations: 0x11AB). 4 Detection of AIS Pointer Interrupt Status RUR Detection of AIS Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of AIS Pointer" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate this interrupt anytime it detects an "AIS Pointer" in the incoming STS-3c data stream. Note: An "AIS Pointer" is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an "All Ones" pattern. 0 - Indicates that the "Detection of AIS Pointer" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of AIS Pointer" interrupt has occurred since the last read of this register. 3 Detection of Pointer Change Interrupt Status RUR Detection of Pointer Change Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Change" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it accepts a new pointer value (e.g., H1 and H2 bytes, in the TOH bytes). 0 - Indicates that the "Detection of Pointer Change" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Change" Interrupt has occurred since the last read of this register. 2 POH Capture Interrupt Status RUR Path Overhead Data Capture Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "POH Capture" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt once the Z5 byte (e.g., the last POH byte) has been loaded into the POH Capture Buffer. The contents of the POH Capture Buffer will remain intact for one SONET frame period. Afterwards, the POH data, for the next SPE will be loaded into the "POH Capture" buffer. 0 - Indicates that the "POH Capture" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "POH Capture" Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the POH, within the most recently received SPE by reading out the contents of address locations "0xN0D3" through "0xN0F3"). 1 Change in TIM-P Condition Interrupt Status RUR Change in TIM-P (Trace Identification Mismatch) Condition Interrupt. 800 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS This RESET-upon-READ bit-field indicates whether or not the "Change in TIM-P" Condition interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. * If the TIM-P condition is declared. * If the TIM-P condition is cleared. 0 - Indicates that the "Change in TIM-P Condition" Interrupt has not occurred since the last read of this register. 1 - Indicates that the "Change in TIM-P Condition" Interrupt has occurred since the last read of this register. 0 Change in J1 Unstable Condition Interrupt Status RUR Change in "J1 (Trace Identification Message) Unstable Condition" Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in J1 Unstable Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-3c POH Processor block declare the "J1 Unstable" Condition. * When the Receive STS-3c POH Processor block clears the "J1 Unstable" condition. 0 - Indicates that the "Change in J1 Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in J1 Unstable Condition" Interrupt has occurred since the last read of this register. 801 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 711: Receive STS-3c Path - SONET Receive Path Interrupt Status - Byte 1 (Address Location= 0x118A) BIT 7 New J1 Message Interrupt Status BIT 6 Detection of REI-P Event Interrupt Status BIT 5 Change in UNEQ-P Condition Interrupt Status RUR 0 BIT 4 Change in PLM-P Condition Interrupt Status RUR 0 BIT 3 New C2 Byte Interrupt Status BIT 2 Change in C2 Byte Unstable Condition Interrupt Status RUR 0 BIT 1 Change in RDI-P Unstable Condition Interrupt Status RUR 0 BIT 0 New RDI-P Value Interrupt Status RUR 0 RUR 0 RUR 0 RUR 0 BIT NUMBER 7 NAME NEW J1 Message Interrupt Status TYPE RUR DESCRIPTION New J1 (Trace Identification) Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New J1 Message" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted (or validated) and new J1 (Trace Identification) Message. 0 - Indicates that the "New J1 Message" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New J1 Message" Interrupt has occurred since the last read of this register. 6 Detection of REI-P Event Interrupt Status RUR Detection of REI-P Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of REI-P Event" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an REI-P condition in the coming STS-3c data-stream. 0 - Indicates that the "Detection of REI-P Event" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of REI-P Event" Interrupt has occurred since the last read of this register. 5 Change in UNEQP Condition Interrupt Status RUR Change in UNEQ-P (Path - Unequipped) Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in UNEQ-P Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-3c POH Processor block declares the UNEQ-P Condition. * When the Receive STS-3c POH Processor block clears the UNEQ-P Condition. 0 - Indicates that the "Change in UNEQ-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in UNEQ-P Condition" Interrupt has occurred since the last read of this register. Note: 802 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1. The user can determine the current state of UNEQ-P by reading out the state of Bit 5 (UNEQ-P Defect Declared) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register. 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status - Byte 0" Registers is 0x1187 4 Change in PLM-P Condition Interrupt Status RUR Change in PLM-P (Path - Payload Mismatch) Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the "Change in PLMP Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-3c POH Processor block declares the "PLM-P" Condition. * When the Receive STS-3c POH Processor block clears the "PLM-P" Condition. 0 - Indicates that the "Change in PLM-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in PLM-P Condition" Interrupt has occurred since the last read of this register. 3 New C2 Byte Interrupt Status RUR New C2 Byte Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New C2 Byte" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 - Indicates that the "New C2 Byte" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New C2 Byte" Interrupt has occurred since the last read of this register. 2 Change in C2 Byte Unstable Condition Interrupt Status RUR Change in C2 Byte Unstable Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in C2 Byte Unstable Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-3c POH Processor block declares the "C2 Byte Unstable" condition. * When the Receive STS-3c POH Processor block clears the "C2 Byte Unstable" condition. 0 - Indicates that the "Change in C2 Byte Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in C2 Byte Unstable Condition" Interrupt has occurred since the last read of this register. Note: 1. The user can determine the current state of "C2 Byte Unstable Condition" by reading out the state of Bit 6 (C2 Byte Unstable Condition) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register. 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register is 0x1187 803 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1 Change in RDI-P Unstable Condition Interrupt Status RUR Change in RDI-P Unstable Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in RDI-P Unstable Condition" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-3c POH Processor block declares an "RDI-P Unstable" condition. * When the Receive STS-3c POH Processor block clears the "RDI-P Unstable" condition. 0 - Indicates that the "Change in RDI-P Unstable Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in RDI-P Unstable Condition" Interrupt has occurred since the last read of this register. Note: 1. The user can determine the current state of "RDI-P Unstable" by reading out the state of Bit 2 (RDI-P Unstable Condition) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register. 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register is 0x1187 0 New RDI-P Value Interrupt Status RUR New RDI-P Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "New RDI-P Value" interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate this interrupt anytime it receives and "validates" a new RDI-P value. 0 - Indicates that the "New RDI-P Value" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "New RDI-P Value" Interrupt has occurred since the last read of this register. Note: 1. The user can obtain the "New RDI-P Value" by reading out the contents of the "RDI-P ACCEPT[2:0]" bit-fields. These bit-fields are located in Bits 6 through 4, within the "Receive STS-3c Path - SONET Receive RDI-P Register". 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register is 0x1193 20 0 Rev2...0...0 200 804 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 712: Receive STS-3c Path - SONET Receive Path Interrupt Status - Byte 0 (Address Location= 0x118B) BIT 7 Detection of B3 Byte Error Interrupt Status RUR 0 BIT 6 Detection of New Pointer Interrupt Status RUR 0 BIT 5 Detection of Unknown Pointer Interrupt Status RUR 0 BIT 4 Detection of Pointer Decrement Interrupt Status RUR 0 BIT 3 Detection of Pointer Increment Interrupt Status RUR 0 BIT 2 Detection of NDF Pointer Interrupt Status RUR 0 BIT 1 Change of LOP-P Condition Interrupt Status RUR 0 BIT 0 Change of AIS-P Condition Interrupt Status RUR 0 BIT NUMBER 7 NAME Detection of B3 Byte Error Interrupt Status TYPE RUR DESCRIPTION Detection of B3 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of B3 Byte Error" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a B3 byte error in the incoming STS-3c data stream. 0 - Indicates that the "Detection of B3 Byte Error" Interrupt has NOT occurred since the last read of this interrupt. 1 - Indicates that the "Detection of B3 Byte Error" Interrupt has occurred since the last read of this interrupt. 6 Detection of New Pointer Interrupt Status RUR Detection of New Pointer Interrupt Status: This RESET-upon-READ indicates whether the "Detection of New Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-3c frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 - Indicates that the "Detection of New Pointer" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of New Pointer" Interrupt has occurred since the last read of this register. 5 Detection of Unknown Pointer Interrupt Status RUR Detection of Unknown Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Unknown Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime that it detects a "pointer" that does not fit into any of the following categories. * An Increment Pointer * A Decrement Pointer * An NDF Pointer * An AIS (e.g., All Ones) Pointer * New Pointer 0 - Indicates that the "Detection of Unknown Pointer" interrupt has NOT 805 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS occurred since the last read of this register. 1 - Indicates that the "Detection of Unknown Pointer" interrupt has occurred since the last read of this register. 4 Detection of Pointer Decrement Interrupt Status RUR Detection of Pointer Decrement Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Decrement" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a "Pointer Decrement" event. 0 - Indicates that the "Detection of Pointer Decrement" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Decrement" interrupt has occurred since the last read of this register. 3 Detection of Pointer Increment Interrupt Status RUR Detection of Pointer Increment Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of Pointer Increment" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a "Pointer Increment" event. 0 - Indicates that the "Detection of Pointer Increment" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of Pointer Increment" interrupt has occurred since the last read of this register. 2 Detection of NDF Pointer Interrupt Status RUR Detection of NDF Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Detection of NDF Pointer" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 - Indicates that the "Detection of NDF Pointer" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Detection of NDF Pointer" interrupt has occurred since the last read of this register. 1 Change of LOPP Condition Interrupt Status RUR Change of LOP-P Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change in LOP-P Condition" interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. a. b. When the Receive STS-3c POH Processor block declares the "Loss of Pointer" defect. When the Receive "STS-3c POH Processor" block clears the "Loss of Pointer" defect. 20 0 Rev2...0...0 200 0 - Indicates that the "Change in LOP-P Condition" interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change in LOP-P Condition" interrupt has occurred since the last read of this register. 806 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Note: 1. The user can determine the current state of LOP-P by reading out the state of Bit 1 (LOP-P Defect Declared) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register. 2. The Address Location of the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register is 0x1187 0 Change of AISP Condition Interrupt Status RUR Change of AIS-P Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the "Change of AIS-P Condition" Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-3c POH Processor block declares an AIS-P condition. * When the Receive STS-3c POH Processor block clears the AIS-P condition. 0 - Indicates that the "Change of AIS-P Condition" Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the "Change of AIS-P Condition" Interrupt has occurred since the last read of this register. Note: 1. The user can determine the current state of AIS-P by reading out the state of Bit 0 (AIS-P Defect Declared) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register. 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status - Byte 0" Registers is 0x1187 807 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 713: Receive STS-3c Path - SONET Receive Path Interrupt Enable - Byte 2 (Address Location= 0x118D) BIT 7 New K3 Byte Interrupt Enable R/W 0 BIT 6 Change in AIS-C Condition Interrupt Enable R/W 0 BIT 5 Change in LOP-C Condition Interrupt Enable R/W 0 BIT 4 Detection of AIS Pointer Interrupt Enable R/W 0 BIT 3 Detection of Pointer Change Interrupt Enable R/W 0 BIT 2 POH Capture Interrupt Enable R/W 0 BIT 1 Change in TIM-P Condition Interrupt Enable R/W 0 BIT 0 Change in J1 Unstable Condition Interrupt Enable R/W 0 BIT NUMBER 7 NAME New K3 Byte Interrupt Enable TYPE R/W DESCRIPTION New K3 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New K3 Byte" Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it has accepted (or validated) and new K3 Byte. 0 - Disables the "New K3 Byte" Interrupt. 1 - Enables the "New K3 Byte" Interrupt. 6 Change in AIS-C Condition Interrupt Enable R/W Change in AIS-C (AIS Concatenation) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in AIS-C Condition" Interrupt. If this interrupt is enabled, then an interrupt will generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares an AIS-C condition with one of the STS-1 signals; within the incoming STS-3c signal. Whenever the Receive STS-3c POH Processor block clears the AIS-C condition with one of the STS-1 signals; within the incoming STS-3c signal. b. 0 - Disables the "Change in AIS-C Condition" Interrupt. 1 - Enables the "Change in AIS-C Condition" Interrupt Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3 signal that contains one or more STS-3c signals. This bit-field is only valid for the following Address Locations: "0x118D" (for STS-3c ) 5 Change in LOP-C Condition Interrupt Enable R/W Change in LOP-C (Loss of Pointer - Concatenation) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOP-C Condition" Interrupt. If this interrupt is enabled, then an interrupt will generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares an LOP-C condition with one of the STS-1 signals; 808 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS within the incoming STS-3c signal. b. Whenever the Receive STS-3c POH Processor block clears the LOP-C condition with one of the STS-1 signals; within the incoming STS-3c signal. 0 - Disables the "Change in LOP-C Condition" Interrupt. 1 - Enables the "Change in LOP-C Condition" Interrupt Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3 signal that contains one or more STS-3c signals. This bit-field is only valid for the following Address Locations: "0x118D" (for STS-3c) 4 Detection of AIS Pointer Interrupt Enable R/W Detection of AIS Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of AIS Pointer" interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an "AIS Pointer", in the incoming STS-3c data stream. Note: An "AIS Pointer" is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an "All Ones" Pattern. 0 - Disables the "Detection of AIS Pointer" Interrupt. 1 - Enables the "Detection of AIS Pointer" Interrupt. 3 Detection of Pointer Change Interrupt Enable R/W Detection of Pointer Change Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Pointer Change" Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted a new pointer value. 0 - Disables the "Detection of Pointer Change" Interrupt. 1 - Enables the "Detection of Pointer Change" Interrupt. 2 POH Capture Interrupt Enable R/W Path Overhead Data Capture Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "POH Capture" Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt once the Z5 byte (e.g., the last POH byte) has been loaded into the POH Capture Buffer. The contents of the POH Capture Buffer will remain intact for one SONET frame period. Afterwards, the POH data for the next SPE will be loaded into the "POH Capture" Buffer. 0 - Disables the "POH Capture" Interrupt 1 - Enables the "POH Capture" Interrupt. 1 Change in TIM-P Condition Interrupt Enable R/W Change in TIM-P (Trace Identification Mismatch) Condition Interrupt: This READ/WRITE bit-field permits the user to either enable or disable the "Change in TIM-P Condition" interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following 809 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS events. * If the TIM-P condition is declared. * If the TIM-P condition is cleared. 0 - Disables the "Change in TIM-P Condition" Interrupt. 1 - Enables the "Change in TIM-P Condition" Interrupt. 0 Change in J1 Unstable Condition Interrupt Enable R/W Change in "J1 (Trace Identification Condition" Interrupt Status: Message) Unstable 20 0 Rev2...0...0 200 This READ/WRITE bit-field permits the user to either enable or disable the "Change in J1 (Trace Identification) Message Unstable Condition" Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-3c POH Processor block declares the "J1 Unstable" Condition. * When the Receive STS-3c POH Processor block clears the "J1 Unstable" Condition. 0 - Disables the "Change in J1 Message Unstable Condition" interrupt. 1 - Enables the "Change in J1 Message Unstable Condition" interrupt. 810 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 714: Receive STS-3c Path - SONET Receive Path Interrupt Enable - Byte 1 (Address Location= 0x118E) BIT 7 New J1 Message Interrupt Enable BIT 6 Detection of REI-P Event Interrupt Enable BIT 5 Change in UNEQ-P Condition Interrupt Enable R/W 0 BIT 4 Change in PLM-P Condition Interrupt Enable R/W 0 BIT 3 New C2 Byte Interrupt Enable BIT 2 Change in C2 Byte Unstable Condition Interrupt Enable R/W 0 BIT 1 Change in RDI-P Unstable Condition Interrupt Enable R/W 0 BIT 0 New RDI-P Value Interrupt Enable R/W 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 NAME NEW J1 Message Interrupt Enable TYPE R/W DESCRIPTION New J1 (Trace Identification) Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New J1 Message" Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted (or validated) and new J1 (Trace Identification) Message. 0 - Disables the "New J1 Message" Interrupt. 1 - Enables the "New J1 Message" Interrupt. 6 Detection of REI-P Event Interrupt Enable R/W Detection of REI-P Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of REI-P Event" Interrupt. If this interrupt is enabled, then he Receive STS-3c POH Processor block will generate an interrupt anytime it detects an REI-P condition in the coming STS-3c data-stream. 0 - Disables the "Detection of REI-P Event" Interrupt. 1 - Enables the "Detection of REI-P Event" Interrupt. 5 Change in UNEQ-P Condition Interrupt Enable R/W Change in UNEQ-P (Path - Unequipped) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in UNEQ-P Condition" interrupt. If this interrupt is enabled , then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-3c POH Processor block declares the UNEQ-P Condition. * When the Receive STS-3c POH Processor block clears the UNEQ-P Condition. 0 - Disables the "Change in UNEQ-P Condition" Interrupt. 1 - Enables the "Change in UNEQ-P Condition" Interrupt. 4 Change in PLMP Condition Interrupt Enable R/W Change in PLM-P (Path - Payload Mismatch) Condition Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the "Change in PLM-P Condition" interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block 811 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 will generate an interrupt in response to either of the following conditions. * When the Receive STS-3c POH Processor block declares the "PLM-P" Condition. * When the Receive STS-3c POH Processor block clears the "PLM-P" Condition. 0 - Disables the "Change in PLM-P Condition" Interrupt. 1 - Enables the "Change in PLM-P Condition" Interrupt. 3 New C2 Byte Interrupt Enable R/W New C2 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New C2 Byte" Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 - Disables the "New C2 Byte" Interrupt. 1 - Enables the "New C2 Byte" Interrupt. Note: 1. The user can obtain the value of this "New C2" byte by reading the contents of the "Receive STS-3c Path - Received Path Label Value" Register. 2. The Address Location of the Receive STS-3c Path - Received Path Label Value" Register is 0x1196 2 Change in C2 Byte Unstable Condition Interrupt Enable R/W Change in C2 Byte Unstable Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in C2 Byte Unstable Condition" Interrupt. If this interrupt is enabled , then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. * When the Receive STS-3c POH Processor block declares the "C2 Byte Unstable" condition. * When the Receive STS-3c POH Processor block clears the "C2 Byte Unstable" condition. 0 - Disables the "Change in C2 Byte Unstable Condition" Interrupt. 1 - Enables the "Change in C2 Byte Unstable Condition" Interrupt. 1 Change in RDIP Unstable Condition Interrupt Enable R/W Change in RDI-P Unstable Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in RDI-P Unstable Condition" interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. * When the Receive STS-3c POH Processor block declares an "RDI-P Unstable" condition. * When the Receive STS-3c POH Processor block clears the "RDI-P Unstable" condition. 0 - Disables the "Change in RDI-P Unstable Condition" Interrupt. 1 - Enables the "Change in RDI-P Unstable Condition" Interrupt. 0 New RDI-P Value Interrupt Enable R/W New RDI-P Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "New RDI-P Value" interrupt. 812 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate this interrupt anytime it receives and "validates" a new RDI-P value. 0 - Disables the "New RDI-P Value" Interrupt. 1 - Enable the "New RDI-P Value" Interrupt. 813 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 715: Receive STS-3c Path - SONET Receive Path Interrupt Enable - Byte 0 (Address Location= 0x118F) BIT 7 Detection of B3 Byte Error Interrupt Enable R/W 0 BIT 6 Detection of New Pointer Interrupt Enable R/W 0 BIT 5 Detection of Unknown Pointer Interrupt Enable R/W 0 BIT 4 Detection of Pointer Decrement Interrupt Enable R/W 0 BIT 3 Detection of Pointer Increment Interrupt Enable R/W 0 BIT 2 Detection of NDF Pointer Interrupt Enable R/W 0 BIT 1 Change of LOP-P Condition Interrupt Enable R/W 0 BIT 0 Change of AIS-P Condition Interrupt Enable R/W 0 BIT NUMBER 7 NAME Detection of B3 Byte Error Interrupt Enable TYPE R/W DESCRIPTION Detection of B3 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of B3 Byte Error" Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a B3-byte error in the incoming STS-3c datastream. 0 - Disables the "Detection of B3 Byte Error" interrupt. 1 - Enables the "Detection of B3 Byte Error" interrupt. 6 Detection of New Pointer Interrupt Enable R/W Detection of New Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of New Pointer" interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-3c frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 - Disables the "Detection of New Pointer" Interrupt. 1 - Enables the "Detection of New Pointer" Interrupt. 5 Detection of Unknown Pointer Interrupt Enable R/W Detection of Unknown Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Unknown Pointer" interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a "Pointer Adjustment" that does not fit into any of the following categories. * An Increment Pointer. * A Decrement Pointer * An NDF Pointer * AIS Pointer * New Pointer. 0 - Disables the "Detection of Unknown Pointer" Interrupt. 1 - Enables the "Detection of Unknown Pointer" Interrupt. 4 Detection of Pointer Decrement Interrupt Enable R/W Detection of Pointer Decrement Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the "Detection of Pointer Decrement" Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an 814 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS interrupt anytime it detects a "Pointer-Decrement" event. 0 - Disables the "Detection of Pointer Decrement" Interrupt. 1 - Enables the "Detection of Pointer Decrement" Interrupt. 3 Detection of Pointer Increment Interrupt Enable R/W Detection of Pointer Increment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of Pointer Increment" Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a "Pointer Increment" event. 0 - Disables the "Detection of Pointer Increment" Interrupt. 1 - Enables the "Detection of Pointer Increment" Interrupt. 2 Detection of NDF Pointer Interrupt Enable R/W Detection of NDF Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Detection of NDF Pointer" Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 - Disables the "Detection of NDF Pointer" interrupt. 1 - Enables the "Detection of NDF Pointer" interrupt. 1 Change of LOPP Condition Interrupt Enable R/W Change of LOP-P Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change in LOP (Loss of Pointer)" Condition interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor will generate an interrupt in response to either of the following events. a. b. When the Receive STS-3c POH Processor block declares a "Loss of Pointer" condition. When the Receive STS-3c POH Processor block clears the "Loss of Pointer" condition. 0 - Disable the "Change of LOP-P Condition" Interrupt. 1 - Enables the "Change of LOP-P Condition" Interrupt. Note: 1. The user can determine the current state of "LOP-P" by reading out the contents of Bit 1 (LOP-P) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0". 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status Byte 0" Register is 0x1187 0 Change of AIS-P Interrupt Enable R/W Change of AIS-P Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the "Change of AIS-P (Path AIS)" interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. a. b. When the Receive STS-3c POH Processor block declares an "AIS-P" condition. When the Receive STS-3c POH Processor block clears the "AISP" condition. 0 - Disables the "Change of AIS-P" Interrupt. 1 - Enables the "Change of AIS-P" Interrupt. Note: 1. The user can determine the current state of "AIS-P" by reading out the 815 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 contents of Bit 0 (AIS-P) within the "Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register. 2. The Address Location of the Receive STS-3c Path - SONET Receive POH Status - Byte 0" Register is 0x1187 816 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 716: Receive STS-3c Path - SONET Receive RDI-P Register (Address Location= 0x1193) BIT 7 Unused R/O 0 R/O 0 BIT 6 BIT 5 RDI-P_ACCEPT[2:0] R/O 0 R/O 0 R/W 0 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 RDI-P THRESHOLD[3:0] BIT NUMBER 7 6-4 NAME Unused RDIP_ACCEPT[2:0] TYPE R/O R/O Accepted RDI-P Value: DESCRIPTION These READ-ONLY bit-fields contain the value of the most recently "accepted" RDI-P (e.g., bits 5, 6 and 7 within the G1 byte) value. Note: A given RDI-P value will be "accepted" by the Receive STS-3c POH Processor block, if this RDI-P value has been consistently received in "RDI-P THRESHOLD[3:0]" number of SONET frames. 3-0 RDI-P THRESHOLD[3:0] R/W RDI-P Threshold: These READ/WRITE bit-fields permit the user to defined the "RDI-P Acceptance Threshold" for the Receive STS-3c POH Processor Block. The "RDI-P Acceptance Threshold" is the number of consecutive SONET frames, in which the Receive STS-3c POH Processor block must receive a given RDI-P value, before it "accepts" or "validates" it. The most recently "accepted" RDI-P value is written into the "RDI-P ACCEPT[2:0]" bit-fields, within this register. 817 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 717: Receive STS-3c Path - Received Path Label Value (Address Location= 0x1196) BIT 7 R/O 1 BIT 6 R/O 1 BIT 5 R/O 1 BIT 4 R/O 1 BIT 3 R/O 1 BIT 2 R/O 1 BIT 1 R/O 1 BIT 0 R/O 1 20 0 Rev2...0...0 200 Received_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Received C2 Byte Value[7:0] TYPE R/O DESCRIPTION Received "Filtered" C2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently "accepted" C2 byte, via the Receive STS-3c POH Processor block. The Receive STS-3c POH Processor block will "accept" a C2 byte value (and load it into these bit-fields) if it has received a consistent C2 byte, in five (5) consecutive SONET frames. Note: 1. The Receive STS-3c POH Processor block uses this register, along the "Receive STS-3c Path - Expected Path Label Value" Register, when declaring or clearing the UNEQ-P and PLM-P alarm conditions. 2. The Address Location of the Receive STS-3c Path - Expected Path Label Value" Register is 0x1197 Table 718: Receive STS-3c Path - Expected Path Label Value (Address Location= 0x1197) BIT 7 R/W 1 BIT 6 R/W 1 BIT 5 R/W 1 BIT 4 R/W 1 BIT 3 R/W 1 BIT 2 R/W 1 BIT 1 R/W 1 BIT 0 R/W 1 Expected_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Expected C2 Byte Value[7:0] TYPE R/W DESCRIPTION Expected C2 Byte Value: These READ/WRITE bit-fields permits the user to specify the C2 (Path Label Byte) value, that the Receive STS-3c POH Processor block should expect when declaring or clearing the UNEQ-P and PLM-P alarm conditions. If the contents of the "Received C2 Byte Value[7:0]" (see "Receive STS-3c Path - Received Path Label Value" register) matches the contents in these register, then the Receive STS3c POH will not declare any alarm conditions. 818 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 719: Receive STS-3c Path - B3 Error Count Register - Byte 3 (Address Location= 0x1198) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[31:24] BIT NUMBER 7-0 NAME B3_Error_Count[31:24] TYPE RUR B3 Error Count - MSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-3c Path - B3 Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: If the B3 Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. If the B3 Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 720: Receive STS-3c Path - B3 Error Count Register - Byte 2 (Address Location= 0x1199) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[23:16] BIT NUMBER 7-0 NAME B3_Error_Count[23:16] TYPE RUR DESCRIPTION B3 Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-3c Path - B3 Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: If the B3 Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. If the B3 Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 721: Receive STS-3c Path - B3 Error Count Register - Byte 1 (Address Location= 0x119A) BIT 7 RUR BIT 6 RUR BIT 5 RUR BIT 4 RUR BIT 3 RUR BIT 2 RUR BIT 1 RUR BIT 0 RUR B3_Error_Count[15:8] 819 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 0 0 0 0 0 0 20 0 Rev2...0...0 200 0 BIT NUMBER 7-0 NAME B3_Error_Count[15:8] TYPE RUR DESCRIPTION B3 Error Count - (Bits 15 through 8): This RESET-upon-READ register, along with "Receive STS-3c Path - B3 Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: If the B3 Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. If the B3 Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. Table 722: Receive STS-3c Path - B3 Error Count Register - Byte 0 (Address Location= 0x119B) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 B3_Error_Count[7:0] BIT NUMBER 7-0 NAME B3_Error_Count[7:0] TYPE RUR B3 Error Count - LSB: DESCRIPTION This RESET-upon-READ register, along with "Receive STS-3c Path - B3 Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: If the B3 Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of bits, within the B3 value that are in error. If the B3 Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain erred B3 bytes. 820 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 723: Receive STS-3c Path - REI-P Error Count Register - Byte 3 (Address Location= 0x119C) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME REI_P_Error_Count[31:24] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION REI-P Error Count - MSB: This RESET-upon-READ register, along with "Receive STS-3c Path - REI-P Error Count Register - Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a Path - Remote Error Indicator. Note: If the REI-P Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[31:24] Table 724: Receive STS-3c Path - REI_P Error Count Register - Byte 2 (Address Location= 0x119D) BIT 7 RUR 0 BIT NUMBER 7-0 BIT 6 RUR 0 NAME REI_P_Error_Count[23:16] BIT 5 RUR 0 TYPE RUR BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 DESCRIPTION REI-P Error Count (Bits 23 through 16): This RESET-upon-READ register, along with "Receive STS-3c Path - REI-P Error Count Register - Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS3c POH Processor block detects a Path - Remote Error Indicator. Note: If the REI-P Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[23:16] Table 725: Receive STS-3c Path - REI_P Error Count Register - Byte 1 (Address Location=0x119E) BIT 7 RUR BIT 6 RUR BIT 5 RUR BIT 4 RUR BIT 3 RUR BIT 2 RUR BIT 1 RUR BIT 0 RUR REI_P_Error_Count[15:8] 821 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 0 0 0 0 0 0 20 0 Rev2...0...0 200 0 BIT NUMBER 7-0 NAME REI_P_Error_Count[15:8] TYPE RUR DESCRIPTION REI-P Error Count - (Bits 15 through 8) This RESET-upon-READ register, along with "Receive STS-3c Path - REI-P Error Count Register - Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS3c POH Processor block detects a Path -Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. Table 726: Receive STS-3c Path - REI_P Error Count Register - Byte 0 (Address Location= 0x119F) BIT 7 RUR 0 BIT 6 RUR 0 BIT 5 RUR 0 BIT 4 RUR 0 BIT 3 RUR 0 BIT 2 RUR 0 BIT 1 RUR 0 BIT 0 RUR 0 REI_P_Error_Count[7:0] BIT NUMBER 7-0 NAME REI_P_Error_Count[7:0] TYPE RUR DESCRIPTION REI-P Error Count - LSB: This RESET-upon-READ register, along with "Receive STS-3c Path - REI-P Error Count Register - Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a Path - Remote Error Indicator. Note: 1. If the REI-P Error Type is configured to be "bit errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the REI-P Error Type is configured to be "frame errors", then the Receive STS-3c POH Processor block will increment this 32 bit counter by the number of frames that contain non-zero REI-P values. 822 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 727: Receive STS-3c Path - Receive J1 Control Register (Address Location=0x11A3) BIT 7 Unused BIT 6 BIT 5 New Message Ready R/O 0 R/O 0 BIT 4 Receive J1 Message Buffer Read Select R/W 0 BIT 3 Accept Threshold BIT 2 Message Type BIT 1 BIT 0 Message Length[1:0] R/O 0 R/W 0 R/W 0 R/O 0 R/O 0 BIT NUMBER 7-5 5 NAME Unused New Message Ready TYPE R/O R/O New Message Ready: DESCRIPTION This READ/WRITE bit-field indicates whether or not the J1 trace buffer has received a new expected value. 0 - Indicates "NO" new expected value has been downloaded into the receive J1 trace buffer. 1 - Indicates a new expected value has been downloaded into the receive J1 trace buffer. 4 Received J1 Message Buffer Read Select R/W J1 Buffer Read Selection: This READ/WRITE bit-field permits a user to specify which of the following buffer segments to read. a. b. Valid Message Buffer Expected Message Buffer 0 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the "Valid Message" buffer. 1 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the "Expected Message Buffer". Note: In the case of the Receive STS-3c POH Processor block, the "Receive J1 Trace Buffer" is located at Address Location = 0x1500 through 0x153F 3 Accept Threshold R/W Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-3c POH Processor block must receive a given J1 Trace Message, before it is accepted, as described below. 0 - The Receive STS-3c POH Processor block accepts the J1 Message after it has received it the third time in succession. 1 - The Receive STS-3c POH Processor block accepts the J1 Message after it has received in the fifth time in succession. 2 Message Type R/O Message Alignment Type: This READ/WRITE bit-field permits a user to specify have the Receive STS3c POH Processor block will locate the boundary of the J1 Trace Message, as indicated below. 0 - Message boundary is indicated by "Line Feed". 1 - Message boundary is indicated by the presence of a "1" in the MSB of a the first byte (within the J1 Trace Message). 823 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1-0 Message Length[1:0] R/W J1 Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the J1 Trace Message, that the Receive STS-3c POH Processor block will receive. The relationship between the content of these bit-fields and the corresponding J1 Trace Message Length is presented below. 20 0 Rev2...0...0 200 MSG LENGTH 00 01 10/11 Resulting J1 Trace Message Length 1 Byte 16 Bytes 64 Bytes 824 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 728: Receive STS-3c Path - Pointer Value - Byte 1 (Address Location= 0x11A6) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1 R/O 0 BIT 0 R/O 0 Current_Pointer Value MSB[9:8] BIT NUMBER 7-2 1-0 NAME Unused Current_Pointer_Value_MSB[1:0] TYPE R/O R/O DESCRIPTION Current Pointer Value - MSB: These READ-ONLY bit-fields, along with that from the "Receive STS-3c Path - Pointer Value - Byte 0" Register combine to reflect the current value of the pointer that the "Receive STS-3c POH Processor" block is using to locate the SPE within the incoming SONET data stream. Note: These register bits comprise the significant bits of the Pointer Value. two-most Table 729: Receive STS-3c Path - Pointer Value - Byte 0 (Address Location=0x11A7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Current_Pointer_Value_LSB[7:0] BIT NUMBER 7-0 NAME Current_Pointer_Value_LSB[7:0] TYPE R/O DESCRIPTION Current Pointer Value - LSB: These READ-ONLY bit-fields, along with that from the "Receive STS-3c Path - Pointer Value - Byte 1" Register combine to reflect the current value of the pointer that the "Receive STS-3c POH Processor" block is using to locate the SPE within the incoming SONET data stream. Note: These register bits comprise the Lower Byte value of the Pointer Value. 825 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 730: Receive STS-3c Path - LOP-C Status Register (Address Location=0x11AB) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 LOP-C Status STS-1 # 3 R/O 0 BIT 1 LOP-C Status STS-1 # 2 R/O 0 BIT 0 Unused R/O 0 20 0 Rev2...0...0 200 BIT NUMBER 7-3 2 NAME Unused LOP-C Status - STS-1 # 3 TYPE R/O R/O DESCRIPTION Loss of Pointer - Concatenation Status - STS-1 # 3 This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the LOP-C (Loss of Pointer - Concatenation) defect with STS-1 # 3 (within an STS3c signal). The Receive STS-3c POH Processor block will declare the LOPC condition, with STS-1 # 3; if it does not receive the "Concatenation Indicator" value of "0x93FF" in the H1, H2 bytes (associated with STS-1 # 3) for 8 consecutive SONET frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the LOP-C condition with STS-1 # 3. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the LOP-C condition with STS-1 # 3. Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3 signal that contains one or more STS-3c signals. 1 LOP-C Status - STS-1 # 2 R/O Loss of Pointer - Concatenation Status - STS-1 # 2 This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the LOP-C (Loss of Pointer - Concatenation) condition with STS-1 # 2 (within an STS-3c signal). The Receive STS-3c POH Processor block will declare the LOPC condition, with STS-1 # 2; if it does not receive the "Concatenation Indicator" value of "0x93FF" in the H1, H2 bytes (associated with STS-1 # 2) for 8 consecutive SONET frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the LOP-C condition with STS-1 # 2. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the LOP-C condition with STS-1 # 2. Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3 signal that contains one or more STS-3c signals. 0 Unused R/O 826 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 731: Receive STS-3c Path - AIS-C Status Register (Address Location=0x11B3) BIT 7 BIT 6 BIT 5 Unused R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 AIS-C Status STS-1 # 3 R/O 0 BIT 1 AIS-C Status STS-1 # 2 R/O 0 BIT 0 Unused R/O 0 BIT NUMBER 7-3 2 NAME Unused AIS-C Status - STS-1 # 3 TYPE R/O R/O DESCRIPTION AIS - Concatenation Status - STS-1 # 3 This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the LOP-C (AIS - Concatenation) condition with STS-1 # 3 (within an STS-3c signal). The Receive STS-3c POH Processor block will declare the AISC condition, with STS-1 # 3; if it receives an "All Ones" string; in the H1, H2 bytes (associated with STS-1 # 3) for 3 consecutive SONET frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the AIS-C condition with STS-1 # 3. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the AIS-C condition with STS-1 # 3. Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3 signal that contains one or more STS-3c signals. 1 AIS-C Status - STS-1 # 2 R/O AIS - Concatenation Status - STS-1 # 2 This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the AIS-C (Loss of Pointer - Concatenation) condition with STS-1 # 2 (within an STS-3c signal). The Receive STS-3c POH Processor block will declare the AISC condition, with STS-1 # 2; if it receives an "All Ones" string in the H1, H2 bytes (associated with STS-1 # 2) for 3 consecutive SONET frames. 0 - Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the AIS-C condition with STS-1 # 2. 1 - Indicates that the Receive STS-3c POH Processor block is currently declaring the AIS-C condition with STS-1 # 2. Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3 signal that contains one or more STS-3c signals. 0 Unused R/O 827 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 732: Receive STS-3c Path - AUTO AIS Control Register (Address Location= 0x11BB) BIT 7 Unused BIT 6 Transmit AIS-P (Downstream) Upon C2 Byte Unstable R/W 0 BIT 5 Transmit AIS-P (Downstream) Upon UNEQ-P R/W 0 BIT 4 Transmit AIS-P (Downstream) Upon PLMP R/W 0 BIT 3 Transmit AIS-P (Downstream) Upon J1 Message Unstable R/W 0 BIT 2 Transmit AIS-P (Downstream) Upon TIM-P BIT 1 Transmit AIS-P (Downstream) upon LOP-P BIT 0 Transmit AIS-P (Downstream) Enable 20 0 Rev2...0...0 200 R/O 0 R/W 0 R/W 0 R/W 0 BIT NUMBER 7 6 NAME Unused Transmit AIS-P (Downstream) upon C2 Byte Unstable TYPE R/O R/W DESCRIPTION Transmit Path AIS upon Detection of Unstable C2 Byte: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-3/STM-1 Telecom Bus Interface), anytime it detects an Unstable C2 Byte condition in the "incoming" STS-3c data-stream. 0 - Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable C2 Byte" condition. 1 - Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable C2 Byte" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 5 Transmit AIS-P (Downstream) upon UNEQ-P R/W Transmit Path AIS upon Detection of Path-Unequipped Defect (UNEQ-P): This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-3/STM-1 Telecom Bus Interface), anytime it declares an UNEQ-P condition. 0 - Does not configure the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the UNEQ-P defect. 1 - Configures the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the UNEQ-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Downstream) upon PLM-P R/W Transmit Path AIS upon Detection of Path-Payload Label Mismatch Defect (PLM-P): This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS 828 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-3/STM-1 Telecom Bus Interface), anytime it declares an PLM-P condition. 0 - Does not configure the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the PLM-P defect. 1 - Configures the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the PLM-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 3 Transmit AIS-P (Downstream) upon J1 Message Unstable R/W Transmit Path AIS upon Detection of Unstable 1 Message: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-3/STM-1 Telecom Bus Interface), anytime it detects an Unstable J1 Message condition in the "incoming" STS-3c datastream. 0 - Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable J1 Message" condition. 1 - Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) whenever it detects an "Unstable J1 Message" condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 2 Transmit AIS-P (Downstream) upon TIM-P R/W Transmit Path AIS upon Detection of Path-Trace Identification Message Mismatch Defect (TIM-P): This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-3/STM-1 Telecom Bus Interface), anytime it declares an TIM-P condition. 0 - Does not configure the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the TIM-P defect. 1 - Configures the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the TIM-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 1 Transmit AIS-P (Downstream) upon LOP-P R/W Transmit Path AIS upon Detection of Loss of Pointer (LOP-P): This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the "downstream" traffic (e.g., towards the Receive STS-3/STM-1 Telecom Bus Interface), anytime it declares an LOP-P condition. 829 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 0 - Does not configure the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOP-P defect. 1 - Configures the Receive STS-3c POH Processor block to transmit the AIS-P indicator (via the "downstream" traffic) upon declaration of the LOP-P defect. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to "1" to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 0 Transmit AIS-P (Downstream) Enable R/W Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS indicator, via the down-stream traffic (e.g., towards the Receive STS3/STM-1 Telecom Bus Interface), upon detection of an AIS-P, UNEQP, PLM-P, TIM-P, LOP-P, Trace Identification Message Mismatch or J1 Message Unstable conditions. 0 - Configures the Receive STS-3c POH Processor block to NOT automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" conditions. 1 - Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the "downstream" traffic) upon detection of any of the "above-mentioned" condition. Note: The user must also set the corresponding bit-fields (within this register) to "1" in order to configure the Receive STS3c POH Processor block to automatically transmit the AISP indicator upon detection of a given alarm/defect condition. 830 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 733: Receive STS-3c Path - Serial Port Control Register (Address Location= 0x11BF) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 RxPOH_CLOCK_SPEED[7:0] BIT NUMBER 7-4 3-0 NAME Unused RxPOH_CLOCK_SPEED[7:0] TYPE R/O R/W DESCRIPTION RxPOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the "RxPOHClk output clock signal. The formula that relates the contents of these register bits to the "RxPOHClk" frequency is presented below. FREQ = 19.44 /[2 * (RxPOH_CLOCK_SPEED) Note: For STS-3/STM-1 applications, the frequency of the RxPOHClk output signal must be in the range of 0.304MHz to 9.72MHz 831 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 734: Receive STS-3c Path - SONET Receive Auto Alarm Register - Byte 0 (Address Location= 0x11C3) BIT 7 Transmit AIS-P (via Downstream STS-3c) upon LOP-P R/W 0 BIT 6 Unused BIT 5 Transmit AIS-P (via Downstream STS-3cs) upon PLM-P R/W 0 BIT 4 Unused BIT 3 Transmit AIS-P (via Downstream STS-3c) upon UNEQ-P R/W 0 BIT 2 Transmit AIS-P (via Downstream STS-3c) upon TIM-P R/W 0 BIT 1 Transmit AIS-P (via Downstream STS-3c) upon AIS-P R/W 0 BIT 0 Unused R/O 0 R/O 0 R/W 0 BIT NUMBER 7 NAME Transmit AIS-P (via Downstream STS-3c) upon LOP-P TYPE R/W DESCRIPTION Transmit AIS-P (via Downstream STS-3c) upon LOP-P This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-3c signal, anytime the Receive STS-3c POH Processor block declares the LOP-P defect. 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-3c signals, anytime the Receive STS-3c POH Processor block declares the LOP-P defect. 1 - Configures the corresponding Transmit STS-3c POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-3c signals, anytime the Receive STS-3c POH Processor block declares the LOP-P defect. 6 5 Unused Transmit AIS-P (via Downstream STS-1s) upon PLM-P R/O R/W Transmit AIS-P (via Downstream STS-1s) upon PLM-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive STS3c POH Processor block declares the PLM-P defect. 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the PLM-P defect. 1 - Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the PLM-P defect. 4 3 Unused Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P R/O R/W Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive STS3c POH Processor block declares the UNEQ-P defect. 832 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the UNEQ-P defect. 1 - Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the UNEQ-P defect. 2 Transmit AIS-P (via Downstream STS-1s) upon TIM-P R/W Transmit AIS-P (via Downstream STS-1s) upon TIM-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive STS3c POH Processor block declares the TIM-P defect. 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the TIM-P defect. 1 - Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the TIM-P defect. 1 Transmit AIS-P (via Downstream STS-1s) upon AIS-P R/W Transmit AIS-P (via Downstream STS-1s) upon AIS-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the "downstream" STS-1 signal, anytime the Receive STS3c POH Processor block declares the AIS-P defect. 0 - Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signals, anytime the Receive STS-3c POH Processor block declares the AIS-P defect. 1 - Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the "downstream" STS-1 signal, anytime the Receive STS-3c POH Processor block declares the AIS-P defect. 0 Unused R/O 833 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 735: Receive STS-3c Path - Receive J1 Capture Register (Address Location= 0x11D3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 J1_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME J1_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION J1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the J1 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new J1 byte value. Table 736: Receive STS-3c Path - Receive B3 Capture Register (Address Location= 0x11D7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 B3_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME B3_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION B3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the B3 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new B3 byte value. 834 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 737: Receive STS-3c Path - Receive C2 Capture Register (Address Location= 0x11DB) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 C2_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME C2_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION C2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the C2 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new C2 byte value. Table 738: Receive STS-3c Path - Receive G1 Byte Capture Register (Address Location= 0x11DF) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 G1_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME G1_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION G1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the G1 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new G1 byte value. 835 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 739: Receive STS-3c Path - Receive F2 Byte Capture Register (Address Location=0x11E3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 F2_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME F2_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION G1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the F2 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new F2 byte value. Table 740: Receive STS-3c Path - Receive H4 Capture Register (Address Location=0x11E7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 H4_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME H4_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION H4 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the H4 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new H4 byte value. 836 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 741: Receive STS-3c Path - Receive Z3 Capture Register (Address Location=0x11EB) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z3_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z3_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z3 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z3 byte value. Table 742: Receive STS-3c Path - Receive Z4 (K3) Capture Register (Address Location= 0x11EF) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 Z4(K3)_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z4(K3)_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z4 (K3) Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z4 (K3) byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z4 (K3) byte value. 837 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 743: Receive STS-3c Path - Receive Z5 Capture Register (Address Location= 0x11F3) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 0 BIT 2 R/O 0 BIT 1 R/O 0 BIT 0 R/O 0 20 0 Rev2...0...0 200 Z5_Byte_Captured_Value[7:0] BIT NUMBER 7-0 NAME Z5_Byte_Captured_Value[7:0] TYPE R/O DESCRIPTION Z5 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z5 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z5 byte value. 838 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS TRANSMIT STS-3C POH PROCESSOR BLOCK 1.13.3 The register map for the Transmit STS-3c POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the "Transmit STS-3c POH Processor" block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the "Transmit STS-3c POH Processor Block "highlighted" is presented below in Figure 15. Figure 15: Illustration of the Functional Blo ck Diagram of the XRT94L33, with the Transmit STS-3c POH Processor Block "High-lighted". From Channels 1 & 2 Tx Tx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Tx Cell Tx Cell Processor Processor Block Block Tx PLCP Tx PLCP Processor Processor Block Block Clock Clock Synthesizer Synthesizer Block Block Tx STS-3 Tx STS-3 PECL PECL I/F Block I/F Block Tx STS-3 Tx STS-3 Telecom Telecom Bus Block Bus Block Tx PPP Tx PPP Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Tx SONET Tx SONET POH POH Processor Processor Block Block Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Rx Rx UTOPIA/ UTOPIA/ POS-PHY POS-PHY Interface Interface Block Block Rx PPP Rx PPP Processor Processor Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Mapper Mapper Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Clock & Clock & Data Data Recovery Recovery Block Block Rx Cell Rx Cell Processor Processor Block Block Rx PLCP Rx PLCP Processor Processor Block Block Channel 0 To Channel 1 & 2 Rx STS-3 Rx STS-3 Telecom Telecom Bus Block Bus Block Rx STS-3 Rx STS-3 PECL PECL I/F Block I/F Block 839 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.13.4 TRANSMIT STS-3C POH PROCESSOR BLOCK REGISTER 20 0 Rev2...0...0 200 Table 744: Transmit STS-3c POH Processor Block - Register Address Map INDIVIDUAL REGISTER ADDRESS 0x00 - 0x81 0x82 0x83 0x84- 0x92 0x93 0x94 - 0x96 0x97 0x98 - 0x9A 0x9B 0x9C - 0x9E 0x9F 0xA0 - 0xA2 0xA3 0xA4 - 0xA6 0xA7 0xA8 - 0xAA 0xAB 0xAC - 0xAE 0xAF 0xB0 - 0xB2 0xB3 0xB4 - 0xB6 0xB7 0xB8 - 0xBA 0xBB ADDRESS LOCATION 0x1900 - 0x1981 0x1982 0x1983 0x1984 - 0x1992 0x1993 0x1994 - 0x1996 0x1997 0x1998 - 0x199A 0x199B 0x199C - 0x199E 0x199F 0x19A0 - 0x19A2 0x19A3 0x19A4 - 0x19A6 0x19A7 0x19A8 - 0x19AA 0x19AB 0x19AC - 0x19AE 0x19AF 0x19B0 - 0x19B2 0x19B3 0x19B4 - 0x19B6 0x19B7 0x19B8 - 0x19BA 0x19BB Reserved Transmit STS-3c Path - SONET Control Register - Byte 1 Transmit STS-3c Path - SONET Control Register - Byte 0 Reserved Transmit STS-3c Path - Transmit J1 Byte Value Register Reserved Transmit STS-3c Path - B3 Byte Mask Register Reserved Transmit STS-3c Path - Transmit C2 Byte Value Register Reserved Transmit STS-3c Path - Transmit G1 Byte Value Register Reserved Transmit STS-3c Path - Transmit F2 Byte Value Register Reserved Transmit STS-3c Path - Transmit H4 Byte Value Register Reserved Transmit STS-3c Path - Transmit Z3 Byte Value Register Reserved Transmit STS-3c Path - Transmit Z4 Byte Value Register Reserved Transmit STS-3c Path - Transmit Z5 Byte Value Register Reserved Transmit STS-3c Path - Transmit Path Control Register - Byte 0 Reserved Transmit STS-3c Path - Transmit J1 Control Register REGISTER NAME DEFAULT VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 840 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS ADDRESS LOCATION 0x19BC - 0x19BE 0x19BF 0x19C0 - 0x19C2 0x19C3 0x19C4 - 0x19C5 0x19C6 0x19C7 0x19C8 0x19C9 0x19CA 0x19CB 0x19CC - 0x19CE 0x19CF 0x19D0 - 0x19FF Reserved Transmit STS-3c Path - Transmit Arbitrary H1 Byte Pointer Register Reserved Transmit STS-3c Path - Transmit Arbitrary H2 Byte Pointer Register Reserved Transmit STS-3c Path - Transmit Pointer Byte Register - Byte 1 Transmit STS-3c Path - Transmit Pointer Byte Register - Byte 0 Reserved Transmit STS-3c Path - RDI-P Control Register - Byte 2 Transmit STS-3c Path - RDI-P Control Register - Byte 1 Transmit STS-3c Path - RDI-P Control Register - Byte 0 Reserved Transmit STS-3c Path - Transmit Path Serial Port Control Register Reserved REGISTER NAME DEFAULT VALUES INDIVIDUAL REGISTER ADDRESS 0xBC - 0xBE 0xBF 0xC0 - 0xC2 0xC3 0xC4, 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC - 0xCE 0xCF 0xD0 - 0xFF 0x00 0x94 0x00 0x00 0x00 0x02 0x0A 0x00 0x40 0xC0 0xA0 0x00 0x00 0x00 841 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 1.13.5 TRANSMIT STS-3C POH PROCESSOR BLOCK REGISTER DESCRIPTION 20 0 Rev2...0...0 200 Table 745: Transmit STS-3c Path - SONET Control Register - Byte 1 (Address Location= 0x1982) BIT 7 BIT 6 Unused R/W 0 R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 Z5 Insertion Type R/W 0 BIT 2 Z4 Insertion Type R/W 0 BIT 1 Z3 Insertion Type R/W 0 BIT 0 H4 Insertion Type R/W 0 BIT NUMBER 7-4 3 NAME Unused Z5 Insertion Type TYPE R/O R/W Z5 Insertion Type: DESCRIPTION This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the "Transmit STS-3c Path - Transmit Z5 Byte Value" Register or the TPOH input pin as the source for the Z5 byte, in the outbound STS-3c SPE. 0 - Configures the Transmit STS-3c POH Processor block to use the "Transmit STS-3c Path - Transmit Z5 Byte Value" Register. 1 - Configures the Transmit STS-3c POH Processor block to use the "TPOH" input as the source for the Z5 byte, in the outbound STS-3c SPE. Note: The Address Location of the Transmit Z5 Byte Value Register is 0x19B3 2 Z4 Insertion Type R/W Z4 Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the "Transmit STS-3c Path - Transmit Z4 Byte Value" Register or the TxPOH input pin as the source for the Z4 byte, in the outbound STS-3c SPE. 0 - Configures the Transmit STS-3c POH Processor block to use the "Transmit STS-3c Path - Transmit Z4 Byte Value" Register. 1 - Configures the Transmit STS-3c POH Processor block to use the "TxPOH" input as the source for the Z4 byte, in the outbound STS-3c SPE. Note: The address location of the Transmit Z4 Byte Value Register is 0x19AF 1 Z3 Insertion Type R/W Z3 Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the "Transmit STS-3c Path - Transmit Z3 Byte Value" Register or the TxPOH input pin as the source for the Z3 byte, in the outbound STS-3c SPE. 0 - Configures the Transmit STS-3c POH Processor block to use the "Transmit STS-3c Path - Transmit Z3 Byte Value" Register. 1 - Configures the Transmit STS-3c POH Processor block to use the "TxPOH" input as the source for the Z3 byte, in the outbound STS-3c SPE. Note: The Address Location of the Transmit Z3 Byte Value Register is 0x19AB 0 H4 Insertion Type R/W H4 Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the "Transmit STS-3c Path - Transmit H4 Byte Value" Register or the TxPOH input pin as the source for the H4 842 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS byte, in the outbound STS-3c SPE. 0 - Configures the Transmit STS-3c POH Processor block to use the "Transmit STS-3c Path - Transmit H4 Byte Value" Register. 1 - Configures the Transmit STS-3c POH Processor block to use the "TPOH" input as the source for the H4 byte, in the outbound STS-3c SPE. Note: The Address Location of the Transmit H4 Byte Value Register is 0x19A7 843 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 746: Transmit STS-3c Path - SONET Control Register - Byte 0 (Address Location= 0x1983) BIT 7 F2 Insertion Type R/W 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 C2 Byte Insertion Type R/W 0 BIT 1 Unused BIT 0 Transmit AISP Enable R/W 0 REI-P Insertion Type[1:0] R/W 0 R/W 0 RDI-P Insertion Type[1:0] R/W 0 R/W 0 R/O 0 BIT NUMBER 7 NAME F2 Insertion Type TYPE R/W F2 Insertion Type: DESCRIPTION This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to use either the "Transmit STS-3c Path - Transmit F2 Byte Value" Register or the TxPOH input pin as the source for the F2 byte, in the outbound STS-3c SPE. 0 - Configures the Transmit STS-3c POH Processor block to use the "Transmit STS-3c Path - Transmit F2 Value" Register. 1 - Configures the Transmit STS-3c POH Processor block to use the "TPOH" input as the source for the F2 byte, in the outbound STS-3c SPE. Note: The Address Location of the Transmit F2 Byte Value Register is 0x19A3 6-5 REI-P Insertion Type[1:0] R/W REI-P Insertion Type[1:0]: These two READ/WRITE bit-fields permit the user to configure the Transmit STS-3c POH Processor block to use one of the three following sources for the REI-P bit-fields (e.g., bits 1 through 4, within the G1 byte of the outbound STS3c SPE). * From the corresponding Receive STS-3c POH Processor block (e g., when it detects B3 bytes in its incoming SPE data). * From the "Transmit G1 Byte Value" Register. * From the "TPOH" input pin. 00/11 - Configures the Transmit STS-3c POH Processor block to set Bits 1 through 4 (in the G1 byte of the outbound SPE) based upon "receive conditions" as detected by the corresponding Receive STS-3c POH Processor block. 01 - Configures the Transmit STS-3c POH Processor block to set Bits 1 through 4 (in the G1 byte of the outbound SPE) based upon the contents within the "Transmit G1 Byte Value" register. 10 - Configures the Transmit STS-3c POH Processor block to use the TPOH input pin as the source of Bits 1 through 4 (in the G1 byte of the outbound SPE). Note: The address location of the Transmit G1 Byte Value Register is 0x199F 4-3 RDI-P Insertion Type[1:0] R/W RDI-P Insertion Type[1:0]: These two READ/WRITE bit-fields permit the user to configure the Transmit STS-3c POH Processor block to use one of the three following sources for the RDI-P bit-fields (e.g., bits 5 through 7, within the G1 byte of the outbound STS3c SPE). * From the corresponding Receive STS-3c POH Processor block (e g., when it detects various alarm conditions within its incoming STS-3c SPE data). * From the "Transmit G1 Byte Value" Register. 844 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS * From the "TPOH" input pin. 00/11 - Configures the Transmit STS-3c POH Processor block to set Bits 5 through 7 (in the G1 byte of the outbound SPE) based upon "receive conditions" as detected by the corresponding Receive STS-3c POH Processor block. 01 - Configures the Transmit STS-3c POH Processor block to set Bits 5 through 7 (in the G1 byte of the outbound SPE) based upon the contents within the "Transmit G1 Byte Value" register. 10 - Configures the Transmit STS-3c POH Processor block to use the TPOH input pin as the source of Bits 5 through 7 (in the G1 byte of the outbound SPE). Note: The address location of the Transmit G1 Byte Value Register is 0x199F 2 C2 Byte Insertion Type R/W C2 Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to use either the "Transmit STS-3c Path - Transmit C2 Byte Value" Register or the TPOH input pin as the source for the C2 byte, in the outbound STS-3c SPE. 0 - Configures the Transmit STS-3c POH Processor block to use the "Transmit STS-3c Path - Transmit C2 Byte Value" Register. 1 - Configures the Transmit STS-3c POH Processor block to use the "TPOH" input as the source for the C2 byte, in the outbound STS-3c SPE. Note: The address location of the Transmit C2 Byte Value Register is 0x199B 1 0 Unused Transmit AIS-P Enable R/O R/W Transmit AIS-P Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to (via software control) transmit an AIS-P indicator to the remote PTE. If this feature is enabled, then the Transmit STS-3c POH Processor block will automatically set the H1, H2, H3 and all the "outbound" STS-3c SPE bytes to an "All Ones" pattern, prior to routing this data to the Transmit STS-3 TOH Processor block. 0 - Configures the Transmit STS-3c POH Processor block to NOT transmit the AIS-P indicator to the remote PTE. 1 - Configures the Transmit STS-3c POH Processor block to transmit the AIS-P indicator to the remote PTE. 845 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 747: Transmit STS-3c Path - Transmitter J1 Byte Value Register (Address Location= 0x1993) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_J1_Byte[7:0] BIT NUMBER 7-0 NAME Transmit J1 Byte Value[7:0] TYPE R/W Transmit J1 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the J1 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the J1 byte, then it will automatically write the contents of this register into the J1 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes the value "[1, 0]" into Bits 1 and 0 (Insertion Method) within the "Transmit STS-3c Path - SONET Path J1 Byte Control Register" register. Note: The Address Location of the Transmit STS-3c Path - SONET J1 Byte Control Register is 0x19BB Table 748: Transmit STS-3c Path - Transmitter B3 Error Mask Register (Address Location= 0x1997) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_B3_Byte_Mask[7:0] BIT NUMBER 7-0 NAME Transmit B3 Byte Mask[7:0] TYPE R/W Transmit B3 Byte Mask[7:0]: DESCRIPTION This READ/WRITE bit-field permits the user to insert errors into the B3 byte, within the "outbound" STS-3c SPE, prior to transmission to the Transmit STS-3 TOH Processor block. The Transmit STS-3c POH Processor block will perform an XOR operation with the contents of this register, and the B3 byte value. The results of this operation will be written back into the B3 byte of the "outbound" STS-3c SPE. If the user sets a particular bit-field, within this register, to "1", then that corresponding bit, within the "outbound" B3 byte will be in error. Note: For normal operation, the user should set this register to 0x00. 846 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 749: Transmit STS-3c Path - Transmit C2 Byte Value Register (Address Location= 0x199B) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_C2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit C2 Byte Value[7:0] TYPE R/W Transmit C2 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the C2 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the C2 byte, then it will automatically write the contents of this register into the C2 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes a "0" into Bit 2 (C2 Insertion Type) within the "Transmit STS-3c Path - SONET Control Register - Byte 0" register. Note: The Address Location of the Transmit STS-3c Path - SONET Control Register - Byte 0" Register is 0x1983 Table 750: Transmit STS-3c Path - Transmit G1 Byte Value Register (Address Location= 0x199F) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_G1_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit G1 Byte Value[7:0] TYPE R/W Transmit G1 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the contents of the RDI-P and REI-P bit-fields, within each G1 byte in the "outbound" STS-3c SPE. If the users sets "REI-P_Insertion_Type[1:0]" and "RDIP_Insertion_Type[1:0]" bits to the value [0, 1], then contents of the REI-P and the RDI-P bit-fields (within each G1 byte of the "outbound" STS-3c SPE) will be dictated by the contents of this register. Note: 1. The "REI-P_Insertion_Type[1:0]" and "RDI-P_Insertion_Type[1:0]" bitfields are located in the "Transmit STS-3c Path - SONET Control Register - Byte 0" Register. 2. The Address Location of the Transmit STS-3c Path - SONET Control Register - Byte 0" Register is 0x1983 847 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 751: Transmit STS-3c Path - Transmit F2 Byte Value Register (Address Location= 0x19A3) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_F2_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit F2 Byte Value[7:0] TYPE R/W Transmit F2 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the F2 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the F2 byte, then it will automatically write the contents of this register into the F2 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes a "0" into Bit 7 (F2 Insertion Type) within the "Transmit STS-3c Path - SONET Control Register - Byte 0" register. Note: The Address Location of the Transmit STS-3c Path - SONET Control Register is 0x1983 Table 752: Transmit STS-3c Path - Transmit H4 Byte Value Register (Address Location= 0x19A7) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_H4_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit H4 Byte Value[7:0] TYPE R/W Transmit H4 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the H4 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the H4 byte, then it will automatically write the contents of this register into the H4 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes a "0" into Bit 0 (H4 Insertion Type) within the "Transmit STS-3c Path - SONET Control Register - Byte 1" register. Note: The Address Location for the "Transmit STS-3c Path - SONET Control Register - Byte 1" register is 0x1982 848 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 753: Transmit STS-3c Path - Transmit Z3 Byte Value Register (Address Location= 0x19AB) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_Z3_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit Z3 Byte Value[7:0] TYPE R/W Transmit Z3 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the Z3 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the Z3 byte, then it will automatically write the contents of this register into the Z3 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes a "0" into Bit 1 (Z3 Insertion Type) within the "Transmit STS-3c Path - SONET Control Register - Byte 1" register. Note: The Address Location for the "Transmit STS-3c Path - SONET Control Register - Byte 1" register is 0x1982 Table 754: Transmit STS-3c Path - Transmit Z4 Byte Value Register (Address Location= 0x19AF) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_Z4_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit Z4 Byte Value[7:0] TYPE R/W Transmit Z4 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the Z4 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the Z4 byte, then it will automatically write the contents of this register into the Z4 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes a "0" into Bit 2 (Z4 Insertion Type) within the "Transmit STS-3c Path - SONET Control Register - Byte 0" register. Note: The Address Location of the Transmit STS-3c Path - SONET Control Register - Byte 0" Register is 0x1982 849 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 755: Transmit STS-3c Path - Transmit Z5 Byte Value Register (Address Location= 0x19B3) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Transmit_Z5_Byte_Value[7:0] BIT NUMBER 7-0 NAME Transmit Z5 Byte Value[7:0] TYPE R/W Transmit Z5 Byte Value: DESCRIPTION These READ/WRITE bit-fields permit the user to have software control over the value of the Z5 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the Z5 byte, then it will automatically write the contents of this register into the Z5 byte location, within each "outbound" STS-3c SPE. This feature is enabled whenever the user writes a "0" into Bit 3 (Z5 Insertion Type) within the "Transmit STS-3c Path - SONET Control Register - Byte 0" register. Note: The Address Location of the Transmit STS-3c Path - SONET Control Register - Byte 0" register is 0x1982 850 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 756: Transmit STS-3c Path - Transmit Path Control Register (Address Location= 0x19B7) BIT 7 Unused BIT 6 BIT 5 Pointer Force R/O 0 R/W 0 BIT 4 Check Stuff BIT 3 Insert Negative Stuff W 0 BIT 2 Insert Positive Stuff W 0 BIT 1 Insert Continuous NDF Events R/W 0 BIT 0 Insert Single NDF Event R/W 0 R/O 0 R/W 0 BIT NUMBER 7-6 5 NAME Unused Pointer Force TYPE R/O R/W Pointer Force: DESCRIPTION This READ/WRITE bit-field permits the user to load the values contained within the "Transmit STS-3c POH Arbitrary H1 Pointer Byte" and "Transmit STS-3c POH Arbitrary H2 Pointer Byte" registers into the H1 and H2 bytes (within the outbound STS-3c data stream). Note: The actual location of the SPE will NOT be adjusted, per the value of H1 and H2 bytes. Hence, this feature should cause the remote terminal to declare an "Invalid Pointer" condition. 0 - Configures the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to transmit STS-3c/STS-3 data with normal and correct H1 and H2 bytes. 1 - Configures the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to overwrite the values of the H1 and H2 bytes (in the outbound STS3c/STS-3 data-stream) with the values in the "Transmit STS-3c POH Arbitrary H1 and H2 Pointer Byte" registers. Note: 1. The Address Location of the Transmit STS-3c Arbitrary H1 Pointer Byte register is 0x19BF 2. The Address Location of the Transmit STS-3c Arbitrary H2 Pointer Byte register is 0x19C3 4 Check Stuff R/W Check Stuff Monitoring: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to only execute a "Positive", "Negative" or "NDF" event (via the "Insert Positive Stuff", "Insert Negative Stuff", "Insert Continuous or Single NDF" options, via software command) if no pointer adjustment (NDF or otherwise) has occurred during the last 3 SONET frame periods. 0 - Disables this feature. In this mode, the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks will execute a "software-commanded" pointer adjustment event, independent of whether a pointer adjustment event has occurred in the last 3 SONET frame periods. 1 - Enables this feature. In this mode, the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks will ONLY execute a "software-commanded" pointer adjustment event, if no pointer adjustment event has occurred during the last 3 SONET frame periods. 3 Insert Negative Stuff R/W Insert Negative Stuff: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c 851 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 POH and Transmit STS-3 TOH Processor blocks to insert a negative-stuff into the outbound STS-3c/STS-3 data stream. This command, in-turn will cause a "Pointer Decrementing" event at the remote terminal. Writing a "0" to "1" transition into this bit-field causes the following to happen. * A negative-stuff will occur (e.g., a single payload byte will be inserted into the H3 byte position within the outbound STS-1/STS-3 data stream). * The "D" bits, within the H1 and H2 bytes will be inverted (to denote a "Decrementing" Pointer Adjustment event). * The contents of the H1 and H2 bytes will be decremented by "1", and will be used as the new pointer from this point on. Note: Once the user writes a "1" into this bit-field, the XRT94L33 will automatically clear this bit-field. Hence, there is no need to subsequently reset this bit-field to "0". 2 Insert Positive Stuff R/W Insert Positive Stuff: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to insert a positive-stuff into the outbound STS-3c/STS-3 data stream. This command, in-turn will cause a "Pointer Incrementing" event at the remote terminal. Writing a "0" to "1" transition into this bit-field causes the following to happen. * A positive-stuff will occur (e.g., a single stuff-byte will be inserted into the STS-3c/STS-3 data-stream, immediately after the H3 byte position within the outbound STS-3c/STS-3 data stream). * The "I" bits, within the H1 and H2 bytes will be inverted (to denote a "Incrementing" Pointer Adjustment event). * The contents of the H1 and H2 bytes will be incremented by "1", and will be used as the new pointer from this point on. Note: Once the user writes a "1" into this bit-field, the XRT94L33 will automatically clear this bit-field. Hence, there is no need to subsequently reset this bit-field to "0". 1 Insert Continuous NDF Events R/W Insert Continuous NDF Events: This READ/WRITE bit-field permits the user configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to continuously insert a New Data Flag (NDF) pointer adjustment into the outbound STS-3c/STS-3 data stream. Note: As the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks insert the NDF event into the STS-1/STS-3 data stream, it will proceed to load in the contents of the "Transmit STS-3c POH Arbitrary H1 Pointer" and "Transmit STS-3c POH Arbitrary H2 Pointer" registers into the H1 and H2 bytes (within the outbound STS-3c/STS-3 data stream). 0 - Configures the "Transmit STS-3c TOH and Transmit STS-3 POH Processor" blocks to not continuously insert NDF events into the "outbound" STS-3c/STS-3 data stream. 1- Configures the "Transmit STS-3c TOH and Transmit STS-3 POH Processor" blocks to continuously insert NDF events into the "outbound" STS3c/STS-3 data stream. 0 Insert Single NDF Event R/W Insert Single NDF Event: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to insert a New Data Flag (NDF) pointer adjustment into the outbound STS-3c/STS-3 data stream. 852 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Writing a "0" to "1" transition into this bit-field causes the following to happen. * The "N" bits, within the H1 byte will set to the value "1001" * The ten pointer-value bits (within the H1 and H2 bytes) will be set to new pointer value per the contents within the "Transmit STS-3c POH - Arbitrary H1 Pointer" and "Transmit STS-3c POH Arbitrary H2 Pointer" registers (Address Location= 0xN9BF and 0xN9C3). * Afterwards, the "N" bits will resume their normal value of "0110"; and this new pointer value will be used as the new pointer from this point on. Note: 1. Once the user writes a "1" into this bit-field, the XRT94L33 will automatically clear this bit-field. Hence, there is no need to subsequently reset this bit-field to "0". 2. The Address Location of the Transmit STS-3c Arbitrary H1 Pointer Byte register is 0x19BF 3. The Address Location of the Transmit STS-3c Arbitrary H2 Pointer Byte register is 0x19C3 853 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 757: Transmit STS-3c Path - SONET Path J1 Byte Control Register (Address Location= 0x19BB) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 Message_Length[1:0] Insertion_Method[1:0] BIT NUMBER 7-4 3-2 NAME Unused Message_Length[1:0] TYPE R/O R/W J1 Message Length[1:0]: DESCRIPTION These READ/WRITE bit-fields permit the user to specify the length of the J1 Trace Message, that the Transmit STS-3c POH Processor block will transmit. The relationship between the content of these bit-fields and the corresponding J1 Trace Message Length is presented below. MSG LENGTH 00 01 10/11 1-0 Insertion_Method[1:0] R/W Resulting J1 Trace Message Length 1 Byte 16 Bytes 64 Bytes J1 Insertion_Method[1:0]: These READ/WRITE bit-fields permit the user to specify the method that he/she will use to insert the J1 byte into the outbound STS-3c SPE. The relationship between the contents of these bit-fields and the corresponding J1 Insertion Method is presented below. J1 Insertion Method[1:0] 00 01 10 Resulting Insertion Method Insert the value "0x00" Insert from the J1 Trace Buffer Insert from the "Transmit STS-3c Path - Transmit J1 Byte Value Register. Insert via the "TxPOH_n" input port 11 854 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS (Address Location= BIT 0 R/W 0 Table 758: Transmit STS-3c Path - Transmit Arbitrary H1 Pointer Register 0x19BF) BIT 7 R/W 0 BIT 6 R/W 0 BIT 5 R/W 0 BIT 4 R/W 0 BIT 3 SS Bits R/W 0 R/W 0 BIT 2 BIT 1 R/W 0 NDF Bits H1 Pointer Value BIT NUMBER 7-4 NAME NDF Bits TYPE R/W NDF (New Data Flag) Bits: DESCRIPTION These READ/WRITE bit-fields permit the user provide the value that will be loaded into the "NDF" bit-field (of the H1 byte), whenever a "0 to 1" transition occurs in Bit 5 (Pointer Force) within the "Transmit STS-3c Path - Transmit Path Control" Register. Note: 3-2 SS Bits R/W SS Bits These READ/WRITE bit-fields permits the user to provide the value that will be loaded into the "SS" bit-fields (of the H1 byte) whenever a "0 to 1" transition occurs in Bit 5 (Pointer Force) within the "Transmit STS-3c Path - Transmit Path Control" Register. Note: 1. The "SS" bits have no functional value, within the H1 byte. 2. The Address Location of the Transmit STS-3c Path - Transmit Path Control register is 0x19B7 1-0 H1 Pointer Value[1:0] R/W H1 Pointer Value[1:0]: These two READ/WRITE bit-fields, along with the constants of the "Transmit STS-3c Path - Transmit Arbitrary H2 Pointer" Register (Address Location= 0xN9C3) permit the user to provide the contents of the Pointer Word. These two READ/WRITE bit-fields permit the user to define the value of the two most significant bits within the Pointer word. Whenever a "0 to 1" transition occurs in Bit 5 (Pointer Force) within the Transmit STS-3c Path - Transmit Path Control" Register, the values of these two bits will be loaded into the two most significant bits within the Pointer Word. Note: The Address Location of the Transmit STS-3c Path - Transmit Path Control register is 0x19B7 The Address Location of the Transmit STS-3c Path - Transmit Path Control register is 0x19B7 855 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 759: Transmit STS-3c Path - Transmit Arbitrary H2 Pointer Register 0x19C3) BIT 7 R/W 0 BIT NUMBER 7-0 BIT 6 R/W 0 NAME H2 Pointer Value[7:0] BIT 5 R/W 0 TYPE R/W H2 Pointer Value[1:0]: These eight READ/WRITE bit-fields, along with the constants of bits 1 and 0 within the "Transmit STS-3c Path - Transmit Arbitrary H1 Pointer" Register permit the user to provide the contents of the Pointer Word. These two READ/WRITE bit-fields permit the user to define the value of the eight least significant bits within the Pointer word. Whenever a "0 to 1" transition occurs in Bit 5 (Pointer Force) within the Transmit STS-3c Path - Transmit Path Control" Register, the values of these eight bits will be loaded into the H2 byte, within the outbound STS-3c/STS-3 data stream. Note: 1. The Address Location of the Transmit STS-3c Path - Transmit Arbitrary H1 Pointer" register is 0x19C3 2. The Address Location of the Transmit STS-3c Path - Transmit Path Control register is 0x19B7 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 DESCRIPTION 20 0 Rev2...0...0 200 (Address Location= BIT 1 R/W 0 BIT 0 R/W 0 H2 Pointer Value[7:0] Table 760: Transmit STS-3c Path - Transmit Current Pointer Byte Register - Byte 1 (Address Location= 0x19C6) BIT 7 R/O 0 BIT NUMBER 7-2 1-0 BIT 6 R/O 0 NAME Unused Tx_Pointer_Hi gh[1:0] BIT 5 Unused R/O 0 TYPE R/O R/O Transmit Pointer Word - High[1:0]: These two READ-ONLY bits, along with the contents of the "Transmit STS-3c Path - Transmit Current Pointer Byte Register - Byte 0" reflect the current value of the pointer (or offset of SPE within the STS-3c frame). These two bits contain the two most significant bits within the "10-bit pointer" word. Note: The Address Location of the Transmit STS-3c Path - Transmit Current Pointer Byte - Byte 0 register is 0x19C7 R/O 0 R/O 0 R/O 0 DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 R/O 1 BIT 0 R/O 0 Tx_Pointer_High[1:0] 856 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 761: Transmit STS-3c Path - Transmit Current Pointer Byte Register - Byte 0 (Address Location= 0x19C7) BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/O 0 BIT 3 R/O 1 BIT 2 R/O 0 BIT 1 R/O 1 BIT 0 R/O 0 Tx_Pointer_Low[7:0] BIT NUMBER 7-0 NAME Tx_Pointer_Lo w[7:0] TYPE R/O DESCRIPTION Transmit Pointer Word - Low[7:0]: These two READ-ONLY bits, along with the contents of the "Transmit STS-3c Path - Transmit Current Pointer Byte Register - Byte 1" reflect the current value of the pointer (or offset of SPE within the STS-3c frame). These two bits contain the eight least significant bits within the "10-bit pointer" word. Note: The Address Location of the Transmit STS-3c Path - Transmit Current Pointer Byte - Byte 0 register is 0x19C6 857 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 762: Transmit STS-3c Path - RDI-P Control Register - Byte 2 (Address Location= 0x19C9) BIT 7 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/O 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit RDI-P upon PLM-P R/W 0 0 PLM-P RDI-P Code[2:0] R/W 0 R/W 0 R/W BIT NUMBER 7-4 3-1 NAME Unused PLM-P RDI-P Code[2:0] TYPE R/O R/W DESCRIPTION PLM-P (Path - Payload Mismatch) - RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within the "outbound" STS3c SPE), whenever the corresponding Receive STS-3c POH Processor block detects and declares a PLM-P condition. Note: In order to enable this feature, the user must set Bit 0 (RDIP upon PLM-P) within this register to "1". 0 Transmit RDI-P upon PLM-P R/W Transmit RDI-P upon PLM-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 3 through 1 - within this register) whenever the corresponding Receive STS-3c POH Processor block declares a PLM-P condition. 0 - Disables the automatic transmission of RDI-P upon detection of PLM-P. 1 - Enables the automatic transmission of RDI-P upon detection of PLM-P. 858 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 763: Transmit STS-3c Path - RDI-P Control Register - Byte 1 (Address Location= 0x19CA) BIT 7 BIT 6 BIT 5 BIT 4 Transmit RDI-P upon TIM-P R/W 0 BIT 3 BIT 2 BIT 1 BIT 0 Transmit RDI-P upon UNEQ-P R/W 0 TIM-P RDI-P Code[2:0] R/W 1 R/W 1 R/W 0 UNEQ-P RDI-P Code[2:0] R/W 0 R/W 0 R/W 0 BIT NUMBER 7-5 NAME TIM-P RDI-P Code[2:0] TYPE R/W DESCRIPTION TIM-P (Path - Trace Identification Mismatch) - RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within the "outbound" STS3c SPE), whenever the corresponding Receive STS-3c POH Processor block detects and declares a TIM-P condition. Note: In order to enable this feature, the user must set Bit 4 (RDIP upon TIM-P) within this register to "1". 4 Transmit RDI-P upon TIM-P R/W Transmit RDI-P upon TIM-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive STS-3c POH Processor block declares a TIM-P condition. 0 - Disables the automatic transmission of RDI-P upon detection of TIM-P. 1 - Enables the automatic transmission of RDI-P upon detection of TIM-P. 3-1 UNEQ-P RDI-P Code[2:0] R/W UNEQ-P (Path - Unequipped) - RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within the "outbound" STS3c SPE), whenever the corresponding Receive STS-3c POH Processor block detects and declares a UNEQ-P condition. Note: In order to enable this feature, the user must set Bit 4 (RDIP upon UNEQ-P) within this register to "1". 0 Transmit RDI-P upon UNEQ-P R/W Transmit RDI-P upon UNEQ-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive STS-3c POH Processor block declares a UNEQ-P condition. 0 - Disables the automatic transmission of RDI-P upon detection of UNEQ-P. 1 - Enables the automatic transmission of RDI-P upon detection of UNEQ-P. 859 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS 20 0 Rev2...0...0 200 Table 764: Transmit STS-3c Path - RDI-P Control Register - Byte 1 (Address Location= 0x19CB) BIT 7 BIT 6 BIT 5 BIT 4 Transmit RDI-P upon LOP-P R/W 0 R/W 0 0 BIT 3 BIT 2 AIS-P RDI-P Code[2:0] BIT 1 BIT 0 Transmit RDIP upon AIS-P R/W 0 R/W 0 LOP-P RDI-P Code[2:0] R/W 1 R/W 1 R/W R/W 0 BIT NUMBER 7-5 NAME LOP-P RDI-P Code[2:0] TYPE R/W DESCRIPTION LOP-P (Path - Loss of Pointer) - RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within the "outbound" STS3c SPE), whenever the corresponding Receive STS-3c POH Processor block detects and declares a LOP-P condition. Note: In order to enable this feature, the user must set Bit 4 (RDIP upon LOP-P) within this register to "1". 4 Transmit RDI-P upon LOP-P R/W Transmit RDI-P upon LOP-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive STS-3c POH Processor block declares a LOP-P condition. 0 - Disables the automatic transmission of RDI-P upon detection of LOP-P. 1 - Enables the automatic transmission of RDI-P upon detection of LOP-P. 3-1 AIS-P RDI-P Code[2:0] R/W AIS-P (Path - AIS) - RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within the "outbound" STS3c SPE), whenever the corresponding Receive STS-3c POH Processor block detects and declares an AIS-P condition. Note: In order to enable this feature, the user must set Bit 4 (RDIP upon AIS-P) within this register to "1". 0 Transmit RDI-P upon AIS-P R/W Transmit RDI-P upon AIS-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive STS-3c POH Processor block declares a AIS-P condition. 0 - Disables the automatic transmission of RDI-P upon detection of AIS-P. 1 - Enables the automatic transmission of RDI-P upon detection of AIS-P. 860 XRT94L33 20 0 Rev2...0...0 200 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS Table 765: Transmit STS-3c Path - Serial Port Control Register (Address Location= 0x19CF) BIT 7 R/O 0 BIT 6 Unused R/O 0 R/O 0 R/O 0 R/W 0 BIT 5 BIT 4 BIT 3 BIT 2 R/W 0 BIT 1 R/W 0 BIT 0 R/W 0 TxPOH Clock Speed [3:0] BIT NUMBER 7-4 3-0 NAME Unused TxPOH Clock Speed [3:0] TYPE R/O R/W DESCRIPTION TxPOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the "TxPOHClk output clock signal. The formula that relates the contents of these register bits to the "TxPOHClk" frequency is presented below. FREQ = 19.44/[2 * (TxPOH_CLOCK_SPEED + 1) Note: For STS-3/STM-1 applications, the frequency of the RxPOHClk output signal must be in the range of 0.304MHz to 9.72MHz 861 XRT94L33 3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER - ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER - ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER - ATM REG STERS NOTES: Rev. 2.0.0 - Added description of bits 4, 5, 6 of register 0x011B. 20 0 Rev2...0...0 200 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation DataSheet March 2007 Reproduction in part or whole, without prior written consent of EXAR Corporation is prohibited 862 |
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